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1. 发明授权

US5960322A Suppression of boron segregation for shallow source and drain junctions in semiconductors 失效
标题翻译：抑制半导体中浅源极和漏极结的硼偏析
公开(公告)号：US5960322A
公开(公告)日：1999-09-28
申请号：US994308
申请日：1997-12-19
申请人： Qi Xiang , Geoffrey Yeap , Srinath Krishnan , Ming-Ren Lin
发明人： Qi Xiang , Geoffrey Yeap , Srinath Krishnan , Ming-Ren Lin
IPC分类号： H01L21/265 , H01L21/336 , H01L21/31 , H01L21/469
CPC分类号： H01L29/6659 , H01L21/2652 , H01L29/6656 , Y10S438/917
摘要： A method in the manufacture of ultra-large scale integrated circuit semiconductor devices suppresses boron loss due to segregation into the screen oxide during the boron activation rapid thermal anneal. A nitridation of the screen oxide is used to incorporate nitrogen into the screen oxide layer prior to boron implantation for ultra-shallow, source and drain extension junctions. A second nitridation of a second screen oxide is used prior to boron implantation for deeper, source and drain junctions. This method significantly suppresses boron diffusion and segregation away from the silicon substrate which reduces series resistance of the complete source and drain junctions.
摘要翻译：制造超大规模集成电路半导体器件的方法抑制了硼激活快速热退火期间由于偏析到屏幕氧化物中的硼损失。在用于超浅，源极和漏极延伸结的硼注入之前，使用屏幕氧化物的氮化将氮掺入屏幕氧化物层中。在硼注入之前，使用第二屏蔽氧化物的第二次氮化用于更深，源极和漏极结。该方法显着抑制了硼扩散和离开硅衬底的偏析，从而降低了整个源极和漏极结的串联电阻。

2. 发明授权

US06204138B1 Method for fabricating a MOSFET device structure which facilitates mitigation of junction capacitance and floating body effects 有权
标题翻译：制造MOSFET器件结构的方法，其有助于缓解结电容和浮体效应
公开(公告)号：US06204138B1
公开(公告)日：2001-03-20
申请号：US09260821
申请日：1999-03-02
申请人： Srinath Krishnan , Witold P. Maszara , Ming-Ren Lin
发明人： Srinath Krishnan , Witold P. Maszara , Ming-Ren Lin
IPC分类号： H01L21336
CPC分类号： H01L29/78612 , H01L29/78621
摘要： A method of forming a MOSFET device is provided. First lightly doped regions are formed, the first lightly doped regions including LDD extension regions of the device. Second very lightly doped regions are formed at least partially below the first lightly doped regions, respectively, the second very lightly doped regions having a dopant concentration less than the first lightly doped regions, and the second very lightly doped regions being implanted at a higher energy level than the first lightly doped regions.
摘要翻译：提供了一种形成MOSFET器件的方法。形成第一轻掺杂区域，第一轻掺杂区域包括器件的LDD延伸区域。第二非常轻掺杂的区域至少部分地形成在第一轻掺杂区域的下方，第二非常轻掺杂的区域具有小于第一轻掺杂区域的掺杂剂浓度，并且第二极轻掺杂区域以较高能量水平比第一轻掺杂区域。

3. 发明授权

US06238960B1 Fast MOSFET with low-doped source/drain 有权
标题翻译：具有低掺杂源极/漏极的快速MOSFET
公开(公告)号：US06238960B1
公开(公告)日：2001-05-29
申请号：US09483400
申请日：2000-01-14
申请人： Witold P. Maszara , Srinath Krishnan , Ming-Ren Lin
发明人： Witold P. Maszara , Srinath Krishnan , Ming-Ren Lin
IPC分类号： H01L21336
CPC分类号： H01L29/66772 , H01L29/6659 , H01L29/7833 , H01L29/78612 , H01L29/78621 , H01L29/78654
摘要： A method (100) of forming a transistor (50, 80) includes forming a gate oxide (120) over a portion of a semiconductor material (56, 122) and forming a doped polysilicon film (124) having a dopant concentration over the gate oxide (122). Subsequently, the doped polysilicon film (124) is etched to form a gate electrode (52) overlying a channel region (58) in the semiconductor material (56, 122), wherein the gate electrode (52) separates the semiconductor material into a first region (60) and a second region (68) having the channel region (58) therebetween. The method (100) further includes forming a drain extension region (64) in the first region (60) and a source extension region (72) in the second region (68), and forming a drain region (62) in the first region (60) and a source region (70) in the second region (68). The source/drain formation is such that the drain and source regions (62, 70) have a dopant concentration which is less than the polysilicon film (124) doping concentration. The lower doping concentration in the source/drain regions (62, 70) lowers the junction capacitance and provides improved control of floating body effects when employed in SOI type processes.
摘要翻译：形成晶体管（50,80）的方法（100）包括在半导体材料（56,122）的一部分上形成栅极氧化物（120），并形成掺杂浓度超过栅极的掺杂多晶硅膜（124）氧化物（122）。随后，蚀刻掺杂多晶硅膜（124）以形成覆盖半导体材料（56,122）中的沟道区域（58）的栅电极（52），其中栅电极（52）将半导体材料分离成第一区域（60）和在其间具有沟道区（58）的第二区域（68）。方法（100）还包括在第一区域（60）中形成漏极延伸区域（64）和在第二区域（68）中形成源极延伸区域（72），并且在第一区域（60）和第二区域（68）中的源极区域（70）。源极/漏极形成使得漏极和源极区域（62,70）具有小于多晶硅膜（124）掺杂浓度的掺杂剂浓度。源极/漏极区域（62,70）中的较低掺杂浓度降低了结电容，并且当用于SOI类型工艺时，提供对浮体效应的改进的控制。

4. 发明授权

US06060364A Fast Mosfet with low-doped source/drain 有权
标题翻译：具有低掺杂源/漏极的快速Mosfet
公开(公告)号：US06060364A
公开(公告)日：2000-05-09
申请号：US260880
申请日：1999-03-02
申请人： Witold P. Maszara , Srinath Krishnan , Ming-Ren Lin
发明人： Witold P. Maszara , Srinath Krishnan , Ming-Ren Lin
IPC分类号： H01L21/336 , H01L29/78 , H01L29/786
CPC分类号： H01L29/66772 , H01L29/6659 , H01L29/7833 , H01L29/78612 , H01L29/78621 , H01L29/78654
摘要： A method (100) of forming a transistor (50, 80) includes forming a gate oxide (120) over a portion of a semiconductor material (56, 122) and forming a doped polysilicon film (124) having a dopant concentration over the gate oxide (122). Subsequently, the doped polysilicon film (124) is etched to form a gate electrode (52) overlying a channel region (58) in the semiconductor material (56, 122), wherein the gate electrode (52) separates the semiconductor material into a first region (60) and a second region (68) having the channel region (58) therebetween. The method (100) further includes forming a drain extension region (64) in the first region (60) and a source extension region (72) in the second region (68), and forming a drain region (62) in the first region (60) and a source region (70) in the second region (68). The source/drain formation is such that the drain and source regions (62, 70) have a dopant concentration which is less than the polysilicon film (124) doping concentration. The lower doping concentration in the source/drain regions (62, 70) lowers the junction capacitance and provides improved control of floating body effects when employed in SOI type processes.
摘要翻译：形成晶体管（50,80）的方法（100）包括在半导体材料（56,122）的一部分上形成栅极氧化物（120），并形成掺杂浓度超过栅极的掺杂多晶硅膜（124）氧化物（122）。随后，蚀刻掺杂多晶硅膜（124）以形成覆盖半导体材料（56,122）中的沟道区域（58）的栅电极（52），其中栅电极（52）将半导体材料分离成第一区域（60）和在其间具有沟道区（58）的第二区域（68）。方法（100）还包括在第一区域（60）中形成漏极延伸区域（64）和在第二区域（68）中形成源极延伸区域（72），并且在第一区域（60）和第二区域（68）中的源极区域（70）。源极/漏极形成使得漏极和源极区域（62,70）具有小于多晶硅膜（124）掺杂浓度的掺杂剂浓度。源极/漏极区域（62,70）中的较低掺杂浓度降低了结电容，并且当用于SOI类型工艺时，提供对浮体效应的改进的控制。

5. 发明授权

US06955969B2 Method of growing as a channel region to reduce source/drain junction capacitance 有权
标题翻译：生长为沟道区域以减少源极/漏极结电容的方法
公开(公告)号：US06955969B2
公开(公告)日：2005-10-18
申请号：US10654497
申请日：2003-09-03
申请人： Ihsan J. Djomehri , Jung-Suk Goo , Srinath Krishnan , Witold P. Maszara , James N. Pan , Qi Xiang
发明人： Ihsan J. Djomehri , Jung-Suk Goo , Srinath Krishnan , Witold P. Maszara , James N. Pan , Qi Xiang
IPC分类号： H01L21/20 , H01L29/06 , H01L29/08 , H01L29/10 , H01L29/78 , H01L21/336 , H01L21/338
CPC分类号： H01L29/0847 , H01L21/02381 , H01L21/0245 , H01L21/02532 , H01L21/0262 , H01L21/02639 , H01L29/0653 , H01L29/1054 , H01L29/78
摘要： A method of forming a channel region for a transistor includes forming a layer of silicon germanium (SiGe) above a substrate, forming an oxide layer above the SiGe layer wherein the oxide layer includes an aperture in a channel area and the aperture is filled with a SiGe feature, depositing a layer having a first thickness above the oxide layer and the SiGe feature, and forming source and drain regions in the layer.
摘要翻译：形成用于晶体管的沟道区的方法包括在衬底上形成硅锗层（SiGe），在SiGe层上形成氧化物层，其中氧化物层包括沟道区中的孔，并且孔填充有 SiGe特征，在氧化物层上沉积具有第一厚度的层和SiGe特征，以及在该层中形成源区和漏区。

6. 发明申请

US20050048743A1 Method of growing as a channel region to reduce source/drain junction capicitance 有权
标题翻译：作为渠道区域生长以减少源/汇交汇率资本的方法
公开(公告)号：US20050048743A1
公开(公告)日：2005-03-03
申请号：US10654497
申请日：2003-09-03
申请人： Ihsan Djomehri , Jung-Suk Goo , Srinath Krishnan , Witold Maszara , James Pan , Qi Xiang
发明人： Ihsan Djomehri , Jung-Suk Goo , Srinath Krishnan , Witold Maszara , James Pan , Qi Xiang
IPC分类号： H01L21/20 , H01L29/06 , H01L29/08 , H01L29/10 , H01L29/78
CPC分类号： H01L29/0847 , H01L21/02381 , H01L21/0245 , H01L21/02532 , H01L21/0262 , H01L21/02639 , H01L29/0653 , H01L29/1054 , H01L29/78
摘要： A method of forming a channel region for a transistor includes forming a layer of silicon germanium (SiGe) above a substrate, forming an oxide layer above the SiGe layer wherein the oxide layer includes an aperture in a channel area and the aperture is filled with a SiGe feature, depositing a layer having a first thickness above the oxide layer and the SiGe feature, and forming source and drain regions in the layer.
摘要翻译：形成用于晶体管的沟道区的方法包括在衬底上形成硅锗层（SiGe），在SiGe层上形成氧化物层，其中氧化物层包括沟道区中的孔，并且孔填充有 SiGe特征，在氧化物层上沉积具有第一厚度的层和SiGe特征，以及在该层中形成源区和漏区。

7. 发明申请

US20090294896A1 SHALLOW TRENCH ISOLATION PROCESS UTILIZING DIFFERENTIAL LINERS 有权
标题翻译：使用差异衬线的浅层分离工艺
公开(公告)号：US20090294896A1
公开(公告)日：2009-12-03
申请号：US12538008
申请日：2009-08-07
申请人： Srinath Krishnan
发明人： Srinath Krishnan
IPC分类号： H01L29/06
CPC分类号： H01L21/823807 , H01L21/76283 , H01L21/823878 , H01L21/84 , H01L29/7846
摘要： A method of manufacturing an integrated circuit (IC) can utilize a shallow trench isolation (STI) technique. The shallow trench isolation technique can be used in an IC process. Separate liners for the trench are used for NMOS and PMOS regions. The liners can induce strain in the substrate.
摘要翻译：集成电路（IC）的制造方法可以利用浅沟槽隔离（STI）技术。浅沟槽隔离技术可用于IC工艺。用于沟槽的单独衬垫用于NMOS和PMOS区域。衬垫可以在衬底中引起应变。

8. 发明授权

US06713819B1 SOI MOSFET having amorphized source drain and method of fabrication 失效
标题翻译：具有非晶化源极漏极和制造方法的SOI MOSFET
公开(公告)号：US06713819B1
公开(公告)日：2004-03-30
申请号：US10118364
申请日：2002-04-08
申请人： William G. En , Dong-Hyuk Ju , Srinath Krishnan
发明人： William G. En , Dong-Hyuk Ju , Srinath Krishnan
IPC分类号： H01L2976
CPC分类号： H01L29/78609 , H01L21/84 , H01L27/1203 , H01L29/78612
摘要： An integrated circuit formed in semiconductor-on-insulator format. The integrated circuit includes a layer of semiconductor material disposed on an insulating layer, where the insulating layer disposed on a substrate. A first and a second MOSFET are provided such that one of a source and a drain of the first MOSFET is disposed adjacent one of a source and a drain of the second MOSFET. An amorphous region is formed in the layer of semiconductor material and extending from an upper surface of the layer of semiconductor material to the isolation layer. The amorphous region is formed between a crystalline portion of the one of the source and the drain of the first MOSFET and a crystalline portion of the one of the source and the drain of the second MOSFET.
摘要翻译：一种以绝缘体半导体形式形成的集成电路。集成电路包括设置在绝缘层上的半导体材料层，其中设置在基板上的绝缘层。提供第一和第二MOSFET，使得第一MOSFET的源极和漏极中的一个被设置为邻近第二MOSFET的源极和漏极之一。在半导体材料层中形成非晶区域并从半导体材料层的上表面延伸到隔离层。非晶区域形成在第一MOSFET的源极和漏极之一的结晶部分和第二MOSFET的源极和漏极之一的结晶部分之间。

9. 发明授权

US06589823B1 Silicon-on-insulator (SOI)electrostatic discharge (ESD) protection device with backside contact plug 失效
标题翻译：具有背面接触插头的绝缘体上硅（SOI）静电放电（ESD）保护装置
公开(公告)号：US06589823B1
公开(公告)日：2003-07-08
申请号：US09792138
申请日：2001-02-22
申请人： Stephen G. Beebe , Srinath Krishnan , Zoran Krivokapic
发明人： Stephen G. Beebe , Srinath Krishnan , Zoran Krivokapic
IPC分类号： H01L2100
CPC分类号： H01L27/0255
摘要： An electrostatic discharge (ESD) protection device for a silicon-on-insulator (SOI) integrated circuit having a silicon substrate with a buried oxide layer disposed thereon and an active layer disposed on the buried oxide layer having active regions defined by isolation trenches. The ESD protection device is formed on the SOI integrated circuit and has an anode and a cathode formed within one of the active regions and coupled respectively to a first and a second node; and a backside contact plug adjacent and in thermal contact with at least one of the anode or the cathode, the backside contact plug traversing the buried oxide layer to thermally couple the one of the active regions and the substrate.
摘要翻译：一种用于绝缘体上硅（SOI）集成电路的静电放电（ESD）保护装置，其具有设置在其上的掩埋氧化物层的硅衬底和设置在具有由隔离沟槽限定的有源区的掩埋氧化物层上的有源层。 ESD保护器件形成在SOI集成电路上，并且具有形成在有源区域之一内的阳极和阴极，并且分别耦合到第一和第二节点; 以及与所述阳极或阴极中的至少一个相邻并与其接触的背面接触插塞，所述背面接触插塞穿过所述掩埋氧化物层以热耦合所述有源区域和所述衬底之一。

10. 发明授权

US06492209B1 Selectively thin silicon film for creating fully and partially depleted SOI on same wafer 失效
标题翻译：选择性薄的硅膜，用于在同一晶圆上产生完全和部分耗尽的SOI
公开(公告)号：US06492209B1
公开(公告)日：2002-12-10
申请号：US09607629
申请日：2000-06-30
申请人： Srinath Krishnan , Matthew Buynoski , Witold Maszara
发明人： Srinath Krishnan , Matthew Buynoski , Witold Maszara
IPC分类号： H01L21302
CPC分类号： H01L27/1203 , H01L21/84
摘要： A method for providing partially depleted and fully depleted transistor devices on the same semiconductor wafer. At least one trench is etched into a bulk semiconductor wafer. The wafer is then filled with an insulating material and polished down to the surface level of the semiconductor wafer to form a generally planar surface. A handle wafer is provided having a substrate layer and an insulating layer. The planar surface of the semiconductor wafer is bonded to the insulating layer of the handle wafer. The trench filled regions of the semiconductor wafer form regions of a first thickness and the remaining regions of the semiconductor wafer form regions of a second thickness. Fully depleted transistor device can then be formed in the regions of the first thickness and partially depleted transistor devices can be formed in regions of the second thickness.
摘要翻译：一种用于在同一半导体晶片上提供部分耗尽和完全耗尽的晶体管器件的方法。至少一个沟槽被蚀刻到体半导体晶片中。然后将晶片填充绝缘材料并抛光至半导体晶片的表面水平以形成大致平坦的表面。提供具有基底层和绝缘层的处理晶片。半导体晶片的平面被接合到处理晶片的绝缘层上。半导体晶片的沟槽填充区域形成第一厚度的区域，并且半导体晶片的其余区域形成第二厚度的区域。然后可以在第一厚度的区域中形成完全耗尽的晶体管器件，并且可以在第二厚度的区域中形成部分耗尽的晶体管器件。

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