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1. 发明授权

US5843516A Liquid source formation of thin films using hexamethyl-disilazane 失效
标题翻译：使用六甲基二硅氮烷的液体源形成薄膜
公开(公告)号：US5843516A
公开(公告)日：1998-12-01
申请号：US714774
申请日：1996-09-16
申请人： Gary F. Derbenwick , Larry D. McMillan , Narayan Solayappan , Michael C. Scott , Carlos A. Paz de Araujo , Shinichiro Hayashi
发明人： Gary F. Derbenwick , Larry D. McMillan , Narayan Solayappan , Michael C. Scott , Carlos A. Paz de Araujo , Shinichiro Hayashi
IPC分类号： C23C18/12 , H01L21/314 , H01L21/316 , B05D5/12
CPC分类号： H01L21/31691 , C23C18/1216 , C23C18/1225
摘要： A precursor liquid comprising several metal 2-ethylhexanoates, such as strontium, tantalum and bismuth 2-ethylhexanoates, in a xylenes/methyl ethyl ketone solvent is prepared, a substrate is placed within a vacuum deposition chamber, a small amount of hexamethyl-disilazane is added to the precursor liquid is misted, and the mist is flowed into the deposition chamber while maintaining the chamber at ambient temperature to deposit a layer of the precursor liquid on the substrate. The liquid is dried, baked, and annealed to form a thin film of a layered superlattice material, such as strontium bismuth tantalate, on the substrate. Then an integrated circuit is completed to include at least a portion of the layered superlattice material film in a component of the integrated circuit.
摘要翻译：制备在二甲苯/甲基乙基酮溶剂中包含若干金属2-乙基己酸酯如锶，钽和铋2-乙基己酸酯的前体液体，将基材置于真空沉积室内，少量六甲基二硅氮烷加入到前体液体中，雾气流入沉积室，同时将室保持在环境温度，以将一层前体液体沉积在基底上。将液体干燥，烘烤和退火，以在基底上形成层状超晶格材料（例如钽酸锶锶）的薄膜。然后，完成集成电路以将集成电路的部件中的至少一部分分层超晶格材料膜包括在内。

2. 发明授权

US5849071A Liquid source formation of thin films using hexamethyl-disilazane 失效
标题翻译：使用六甲基二硅氮烷的液体源形成薄膜
公开(公告)号：US5849071A
公开(公告)日：1998-12-15
申请号：US876304
申请日：1997-06-16
申请人： Gary F. Derbenwick , Larry D. McMillan , Narayan Solayappan , Michael C. Scott , Carlos A. Paz de Araujo , Shinichiro Hayashi
发明人： Gary F. Derbenwick , Larry D. McMillan , Narayan Solayappan , Michael C. Scott , Carlos A. Paz de Araujo , Shinichiro Hayashi
IPC分类号： C23C18/12 , H01L21/314 , H01L21/316 , C09D7/12 , C09K15/32
CPC分类号： H01L21/31691 , C23C18/1216 , C23C18/1225
摘要： A precursor liquid comprising several metal 2-ethylhexanoates, such as strontium, tantalum and bismuth 2-ethylhexanoates, in a solvent such as xylenes/methyl ethyl ketone and a small amount of hexamethyl-disilazane. The liquid is dried, baked, and annealed to form a thin film of a layered superlattice material, such as strontium bismuth tantalate, on the substrate.
摘要翻译：在溶剂如二甲苯/甲基乙基酮和少量六甲基二硅氮烷中，包含若干金属2-乙基己酸酯如锶，钽和2-乙基己酸铋的前体液体。将液体干燥，烘烤和退火，以在基底上形成层状超晶格材料（例如钽酸锶锶）的薄膜。

3. 发明授权

US5846597A Liquid source formation of thin films using hexamethyl-disilazane 失效
公开(公告)号：US5846597A
公开(公告)日：1998-12-08
申请号：US876305
申请日：1997-06-16
申请人： Gary F. Derbenwick , Larry D. McMillan , Narayan Solayappan , Michael C. Scott , Carlos A. Paz de Araujo , Shinichiro Hayashi
发明人： Gary F. Derbenwick , Larry D. McMillan , Narayan Solayappan , Michael C. Scott , Carlos A. Paz de Araujo , Shinichiro Hayashi
IPC分类号： C23C18/12 , H01L21/314 , H01L21/316 , B05D5/12
CPC分类号： H01L21/31691 , C23C18/1216 , C23C18/1225
摘要： A precursor liquid comprising several metal 2-ethylhexanoates, such as strontium, tantalum and bismuth 2-ethylhexanoates, in a xylenes/methyl ethyl ketone solvent is prepared, a substrate is placed within a vacuum deposition chamber, a small amount of hexamethyl-disilazane is added to the precursor liquid is misted, and the mist is flowed into the deposition chamber while maintaining the chamber at ambient temperature to deposit a layer of the precursor liquid on the substrate. The liquid is dried, baked, and annealed to form a thin film of a layered superlattice material, such as strontium bismuth tantalate, on the substrate. Then an integrated circuit is completed to include at least a portion of the layered superlattice material film in a component of the integrated circuit.

4. 发明授权

US5962069A Process for fabricating layered superlattice materials and AB0.sub.3 type metal oxides without exposure to oxygen at high temperatures 失效
标题翻译：用于在高温下不暴露于氧气的层压超晶格材料和AB03型金属氧化物的制造方法
公开(公告)号：US5962069A
公开(公告)日：1999-10-05
申请号：US900270
申请日：1997-07-25
申请人： Gunther Schindler , Walter Hartner , Carlos Mazure , Narayan Solayappan , Vikram Joshi , Gary F. Derbenwick
发明人： Gunther Schindler , Walter Hartner , Carlos Mazure , Narayan Solayappan , Vikram Joshi , Gary F. Derbenwick
IPC分类号： C23C18/12 , H01L21/314 , H01L21/316 , B05D3/02 , H01L21/3205
CPC分类号： H01L21/31691 , C23C18/1216 , C23C18/1225 , C23C18/1275 , C23C18/1283 , C23C18/1295
摘要： A liquid precursor containing a metal is applied to a first electrode, dried in air at a first temperature of 160.degree. C. and then a second temperature of 260.degree. C., RTP baked at a temperature of 300.degree. C. in oxygen, RTP baked at a temperature of 650.degree. C. in nitrogen, and annealed at a temperature of 800.degree. C. in nitrogen to form a strontium bismuth tantalate layered superlattice material. A second electrode is deposited and then the device is patterned to form a capacitor, and a second anneal is performed at a temperature of 800.degree. C. in nitrogen. Alternatively, the second anneal may be performed in oxygen at a temperature of 600.degree. C. or less. In this manner, a high electronic quality thin film of a layered superlattice material is fabricated without a high-temperature oxygen anneal.
摘要翻译：将含有金属的液体前体施加到第一电极上，在空气中在160℃的第一温度下干燥，然后在260℃的第二温度下干燥，在氧气中在300℃下进行RTP烘焙，RTP 在氮气中在650℃下烘烤，并在氮气中在800℃的温度下退火，形成钽酸铋锶层状超晶格材料。沉积第二电极，然后将器件图案化以形成电容器，并且在氮气中在800℃的温度下进行第二次退火。或者，第二退火可以在600℃以下的温度下进行。以这种方式，在没有高温氧退火的情况下制造层状超晶格材料的高电子质量薄膜。

5. 发明授权

US07109934B2 Rectifier utilizing a grounded antenna 失效
公开(公告)号：US07109934B2
公开(公告)日：2006-09-19
申请号：US10879379
申请日：2004-06-29
申请人： Alan D. Devilbiss , Gary F. Derbenwick
发明人： Alan D. Devilbiss , Gary F. Derbenwick
IPC分类号： H01Q1/22 , H01Q1/38
CPC分类号： G06K19/0775 , G06K19/0701 , G06K19/0715 , G06K19/0723 , G06K19/07749
摘要： A rectifier generates a rectified output and a dc power output. The rectifier has an antenna element, a tuning capacitor, a coupling capacitor, first and second rectifying diodes, and a storage capacitor. The antenna element and the tuning capacitor are coupled in parallel and grounded at one terminal. The first rectifying diode is grounded at its anode terminal and the storage capacitor is grounded at one terminal. The coupling capacitor is coupled between the ungrounded terminal of the antenna element and the cathode terminal of the first rectifying diode. The anode terminal of the second rectifying diode is coupled to the cathode terminal of the first rectifying diode. The cathode terminal of the second rectifying diode is coupled to the ungrounded terminal of the storage capacitor. The rectified output is generated between the rectifying diodes. The dc power output is generated between the second rectifying diode and the storage capacitor.

6. 发明授权

US06658608B1 Apparatus and method for testing ferroelectric memories 失效
标题翻译：用于测试铁电存储器的装置和方法
公开(公告)号：US06658608B1
公开(公告)日：2003-12-02
申请号：US09400210
申请日：1999-09-21
申请人： David A. Kamp , Gary F. Derbenwick
发明人： David A. Kamp , Gary F. Derbenwick
IPC分类号： G11C2900
CPC分类号： G11C29/028 , G11C11/22 , G11C29/50
摘要： A ferroelectric integrated circuit memory device includes: a plurality of memory cells, each including a ferroelectric material, a plurality of conducting lines, each connected to or connectable to a selected one of the memory cells; a drive circuit for applying a predetermined voltage for a predetermined time to a selected one of the conducting lines, the predetermined voltage and time being the normal voltage and time required to perform write or read functions to the memory cell, a function selected from the group of: writing a logic state to the selected memory cell, and reading the selected memory cell; and a mode control circuit responsive to an external signal for adjusting the predetermined voltage or the predetermined time to perform an operation selected from the group consisting of: a partial read of the selected memory cell, and a partial write of the selected memory cell; and applying ferroelectric stress to the memory cell. A known logic state is written to the memory cells, the cells are heated, and then read to provide output data indicative of the likelihood of premature failure for each of the memory cells. Ferroelectric stress is applied to the cells either before or after the cells are written to by repeatedly applying a voltage to the cells corresponding to a logic state opposite that of the written logic state.
摘要翻译：铁电集成电路存储器件包括：多个存储单元，每个存储单元包括铁电材料，多个导线，每个导体线连接到或连接到选定的一个存储单元; 驱动电路，用于将预定电压预定时间施加到所选择的导线中，所述预定电压和时间是对所述存储单元执行写或读功能所需的正常电压和时间，从所述组中选择的功能将逻辑状态写入所选存储单元，并读取所选存储单元; 以及模式控制电路，其响应于外部信号用于调整所述预定电压或所述预定时间以执行从由以下组成的组中选择的操作：所选择的存储器单元的部分读取和所选存储单元的部分写入; 并向存储单元施加铁电应力。将已知的逻辑状态写入存储器单元，单元被加热，然后读取以提供指示每个存储器单元的过早故障的可能性的输出数据。通过对与逻辑状态相反的逻辑状态相对应的单元反复施加电压，在单元被写入之前或之后对电池施加铁电应力。

7. 发明授权

US07053433B1 Encapsulated ferroelectric array 失效
标题翻译：封装铁电阵列
公开(公告)号：US07053433B1
公开(公告)日：2006-05-30
申请号：US10135488
申请日：2002-04-29
申请人： Gary F. Derbenwick
发明人： Gary F. Derbenwick
IPC分类号： H01L27/108
CPC分类号： H01L27/1159 , H01L27/11502 , H01L27/11585
摘要： A ferroelectric layer within an array of ferroelectric FETs is encapsulated between a bottom barrier dielectric layer and a top barrier dielectric layer extending beyond the ferroelectric layer. The ferroelectric FETs are formed on first conductivity type silicon, each having two second conductivity type silicon regions within the first conductivity type silicon separated by some distance. The two second conductivity type silicon regions forming a source and a drain with a channel region therebetween. A silicon dioxide layer is formed on the channel region, a bottom barrier dielectric layer is formed on the silicon dioxide layer, a ferroelectric layer is formed on the bottom barrier dielectric layer, a top barrier dielectric layer is formed on the ferroelectric layer, and an electrode layer is formed on the ferroelectric layer.
摘要翻译：铁电FET阵列内的铁电层被封装在底部阻挡介电层和延伸超出铁电层的顶部阻挡介电层之间。铁电FET形成在第一导电型硅上，每个第一导电类型的硅在第一导电类型硅内部具有两个第二导电类型的硅区域，分隔一定距离。两个第二导电类型的硅区域形成在其间具有沟道区域的源极和漏极。在沟道区上形成二氧化硅层，在二氧化硅层上形成底部阻挡介电层，在底部阻挡介电层上形成铁电体层，在铁电体层上形成顶部阻挡介电层，在铁电体层上形成电极层。

8. 发明授权

US06178138B1 Asynchronously addressable clocked memory device and method of operating same 失效
标题翻译：异步寻址时钟存储器件及其操作方法
公开(公告)号：US06178138B1
公开(公告)日：2001-01-23
申请号：US09400212
申请日：1999-09-21
申请人： Gary F. Derbenwick , David A. Kamp , Michael V. Cordoba , Ryan T. Hirose
发明人： Gary F. Derbenwick , David A. Kamp , Michael V. Cordoba , Ryan T. Hirose
IPC分类号： G11C800
CPC分类号： G11C8/06 , G11C8/18
摘要： A timing circuit produces a clock signal. An address buffer circuit receives and stores a first address in a first latch and a second address in a second latch asynchronously with respect to the clock signal. A memory control circuit associated with an array of memory cells accesses a first memory cell in the array corresponding to the first address in a first clocked access cycle, and accesses a second memory cell in the array corresponding to the second address in a second clocked access cycle. If a further address is asynchronously received before said second access cycle, the further address replaces the second address in the second latch.
摘要翻译：定时电路产生时钟信号。地址缓冲电路相对于时钟信号异步地接收并存储第一锁存器中的第一地址和第二锁存器中的第二地址。与存储器单元阵列相关联的存储器控制电路在第一计时的访问周期中访问对应于第一地址的阵列中的第一存储器单元，并且以第二时钟控制存取器访问对应于第二地址的阵列中的第二存储器单元周期。如果在所述第二访问周期之前异步地接收另一地址，则另外的地址替换第二锁存器中的第二地址。

9. 发明授权

US4397077A Method of fabricating self-aligned MOS devices and independently formed gate dielectrics and insulating layers 失效
标题翻译：制造自对准MOS器件和独立形成的栅极电介质和绝缘层的方法
公开(公告)号：US4397077A
公开(公告)日：1983-08-09
申请号：US331475
申请日：1981-12-16
申请人： Gary F. Derbenwick , James R. Adams , Matthew V. Hanson , William D. Ryden
发明人： Gary F. Derbenwick , James R. Adams , Matthew V. Hanson , William D. Ryden
IPC分类号： H01L27/04 , H01L21/28 , H01L21/336 , H01L21/339 , H01L21/768 , H01L21/822 , H01L21/8242 , H01L29/78 , H01L21/76
CPC分类号： H01L27/10844 , H01L21/28273 , H01L29/66833 , H01L29/66954 , Y10S438/981
摘要： A method is described for fabricating MOS devices of the type found in very large scale integrated circuits. According to the method described herein, various gate oxides and insulating layers are fabricated independently of each other in order to independently tailor their thicknesses and thereby provide improved isolation between gate electrodes and interconnects, and independently controllable operating characteristics for multiple gate electrode structures. The fabrication of a dynamic RAM memory cell, an overlapping gate CCD device and a self-aligned MNOS transistor cell are described using the disclosed method.
摘要翻译：描述了一种用于制造在大规模集成电路中发现的类型的MOS器件的方法。根据本文描述的方法，各个栅极氧化物和绝缘层彼此独立地制造，以便独立地定制其厚度，从而提供栅电极和互连之间的改进的隔离，以及多个栅电极结构独立可控的工作特性。使用所公开的方法描述了动态RAM存储器单元，重叠栅极CCD器件和自对准MNOS晶体管单元的制造。

10. 发明授权

US06777829B2 Rectifier utilizing a grounded antenna 失效
公开(公告)号：US06777829B2
公开(公告)日：2004-08-17
申请号：US10097846
申请日：2002-03-13
申请人： Alan D. Devilbiss , Gary F. Derbenwick
发明人： Alan D. Devilbiss , Gary F. Derbenwick
IPC分类号： H02J900
CPC分类号： G06K19/0775 , G06K19/0701 , G06K19/0715 , G06K19/0723 , G06K19/07749
摘要： A rectifier generates a rectified output and a dc power output. The rectifier has an antenna element, a tuning capacitor, a coupling capacitor, first and second rectifying diodes, and a storage capacitor. The antenna element and the tuning capacitor are coupled in parallel and grounded at one terminal. The first rectifying diode is grounded at its anode terminal and the storage capacitor is grounded at one terminal. The coupling capacitor is coupled between the ungrounded terminal of the antenna element and the cathode terminal of the first rectifying diode. The anode terminal of the second rectifying diode is coupled to the cathode terminal of the first rectifying diode. The cathode terminal of the second rectifying diode is coupled to the ungrounded terminal of the storage capacitor. The rectified output is generated between the rectifying diodes. The dc power output is generated between the second rectifying diode and the storage capacitor.

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