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1. 发明授权

US06178138B1 Asynchronously addressable clocked memory device and method of operating same 失效
标题翻译：异步寻址时钟存储器件及其操作方法
公开(公告)号：US06178138B1
公开(公告)日：2001-01-23
申请号：US09400212
申请日：1999-09-21
申请人： Gary F. Derbenwick , David A. Kamp , Michael V. Cordoba , Ryan T. Hirose
发明人： Gary F. Derbenwick , David A. Kamp , Michael V. Cordoba , Ryan T. Hirose
IPC分类号： G11C800
CPC分类号： G11C8/06 , G11C8/18
摘要： A timing circuit produces a clock signal. An address buffer circuit receives and stores a first address in a first latch and a second address in a second latch asynchronously with respect to the clock signal. A memory control circuit associated with an array of memory cells accesses a first memory cell in the array corresponding to the first address in a first clocked access cycle, and accesses a second memory cell in the array corresponding to the second address in a second clocked access cycle. If a further address is asynchronously received before said second access cycle, the further address replaces the second address in the second latch.
摘要翻译：定时电路产生时钟信号。地址缓冲电路相对于时钟信号异步地接收并存储第一锁存器中的第一地址和第二锁存器中的第二地址。与存储器单元阵列相关联的存储器控制电路在第一计时的访问周期中访问对应于第一地址的阵列中的第一存储器单元，并且以第二时钟控制存取器访问对应于第二地址的阵列中的第二存储器单元周期。如果在所述第二访问周期之前异步地接收另一地址，则另外的地址替换第二锁存器中的第二地址。

2. 发明授权

US08750051B1 Systems and methods for providing high voltage to memory devices 有权
标题翻译：向存储器件提供高电压的系统和方法
公开(公告)号：US08750051B1
公开(公告)日：2014-06-10
申请号：US13340248
申请日：2011-12-29
申请人： Ryan T. Hirose , Bogdan Georgescu , Leonard Gitlan , Ashish Amonkar , Gary Moscaluk , John Tiede
发明人： Ryan T. Hirose , Bogdan Georgescu , Leonard Gitlan , Ashish Amonkar , Gary Moscaluk , John Tiede
IPC分类号： G11C16/04
CPC分类号： G11C16/14 , G11C16/30 , G11C16/3404 , H03K3/35613 , H03K19/0185
摘要： Apparatus, systems, and methods for providing high voltage to memory devices are provided. One apparatus includes a low voltage input and a two-rail level shifting. The two-rail level shifting is configured to increase the low voltage or to decrease the low voltage to an amount that is less than or equal to a ground potential based on the amount of the low voltage. A system includes a low voltage input for receiving a voltage and a two-rail level shifting coupled to the low voltage input. The two-rail level shifting is configured to increase the voltage to a positive voltage if the voltage is equal to a ground potential and decrease the voltage to a negative voltage if the voltage is greater than the ground potential. One method includes receiving a voltage, modifying the voltage to generate one of a plurality of output voltages, and providing the output voltage to a memory device.
摘要翻译：提供了用于向存储器件提供高电压的装置，系统和方法。一种装置包括低电压输入和双轨电平移位。双轨电平移位被配置为基于低电压的量来增加低电压或将低电压降低到小于或等于接地电位的量。系统包括用于接收电压的低电压输入和耦合到低电压输入的双轨电平转换。如果电压等于接地电位，则双轨电平移位被配置为将电压增加到正电压，如果电压大于接地电位，则将电压降低到负电压。一种方法包括接收电压，修改电压以产生多个输出电压中的一个，并将输出电压提供给存储器件。

3. 发明授权

US08599618B2 High voltage tolerant row driver 有权
标题翻译：高耐压行驱动器
公开(公告)号：US08599618B2
公开(公告)日：2013-12-03
申请号：US13339755
申请日：2011-12-29
申请人： Bogdan I. Georgescu , Ryan T. Hirose
发明人： Bogdan I. Georgescu , Ryan T. Hirose
IPC分类号： G11C11/34
CPC分类号： G11C8/08 , G11C16/08 , G11C16/12
摘要： A circuit is configured to supply a first gate voltage (PG1) at a first voltage bias (VP1) to a source of a first transistor providing an output (WLS), providing the first voltage bias (VP1) to a second transistor and supplying a second voltage bias (VN1) and a second gate voltage (NG1) to a third transistor, the second transistor coupled in series to the third transistor and in parallel with the first transistor, to supply a third voltage bias (VP2) and a third gate voltage (PG2) to a fourth transistor, and a fourth voltage bias (VN2) and a fourth gate voltage (NG2) to a fifth transistor, the fourth transistor coupled in series to the fifth transistor, and the fourth and fifth transistors coupled to a gate of the second transistor, and to provide a fifth voltage bias (VN3) to a line connecting the third transistor to the fifth transistor.
摘要翻译：电路被配置为将第一电压偏置（VP1）的第一栅极电压（PG1）提供给提供输出（WLS）的第一晶体管的源极，将第一电压偏置（VP1）提供给第二晶体管并提供第二电压偏置（VN1）和第二栅极电压（NG1）到第三晶体管，第二晶体管串联耦合到第三晶体管并与第一晶体管并联，以提供第三电压偏置（VP2）和第三栅极电压（PG2）到第四晶体管，以及第四电压偏置（VN2）和第四栅极电压（NG2）到第五晶体管，第四晶体管与第五晶体管串联耦合，第四和第五晶体管耦合到栅极，并且向连接第三晶体管至第五晶体管的线路提供第五电压偏置（VN3）。

4. 发明授权

US06363011B1 Semiconductor non-volatile latch device including non-volatile elements 有权
标题翻译：包括非易失性元件的半导体非易失性锁存器件
公开(公告)号：US06363011B1
公开(公告)日：2002-03-26
申请号：US09626267
申请日：2000-07-25
申请人： Ryan T. Hirose , Loren T. Lancaster
发明人： Ryan T. Hirose , Loren T. Lancaster
IPC分类号： G11C1604
CPC分类号： G11C14/00
摘要： A bistable non-volatile latch circuit adapted to store a non-volatile binary data state during a program operation, and to assume one of two stable states in response to a recall operation that correspond uniquely to the data state has first and second circuit sections. The first circuit section has a first non-volatile current path with means to set the impedance of the first current path in a non-volatile manner. A first end of the first current path is connected to provide a logic output signal, which represents a binary logic state depending on a voltage applied to the a first signal input node. The set/reset signal to the first current path varies between at least the power source voltage and a program voltage that is negative with respect to the power source voltage. A second circuit section generates an output voltage on a second output node that represents a binary logic state opposite from the output states of the first circuit section. Means are provided for connecting the first circuit section and the second circuit section into a bistable configuration.
摘要翻译：一种双稳态非易失性锁存电路，其适于在编程操作期间存储非易失性二进制数据状态，并且为了响应于唯一对应于数据状态的调用操作而采取两个稳定状态之一具有第一和第二电路部分。第一电路部分具有第一非易失性电流路径，其具有以非易失性方式设置第一电流路径的阻抗的装置。连接第一电流路径的第一端以提供逻辑输出信号，其根据施加到第一信号输入节点的电压表示二进制逻辑状态。至第一电流路径的置位/复位信号至少在电源电压和相对于电源电压为负的编程电压之间变化。第二电路部分在第二输出节点上产生表示与第一电路部分的输出状态相反的二进制逻辑状态的输出电压。提供了用于将第一电路部分和第二电路部分连接成双稳态结构的装置。

5. 发明授权

US5774400A Structure and method to prevent over erasure of nonvolatile memory transistors 失效
标题翻译：防止非易失性存储晶体管过度擦除的结构和方法
公开(公告)号：US5774400A
公开(公告)日：1998-06-30
申请号：US772970
申请日：1996-12-23
申请人： Loren T. Lancaster , Ryan T. Hirose
发明人： Loren T. Lancaster , Ryan T. Hirose
IPC分类号： G11C16/14 , G11C16/34 , G11C11/40
CPC分类号： G11C16/3477 , G11C16/14 , G11C16/3468
摘要： A method and structure for preventing over erasure in non-volatile memory cells uses simultaneous erase and program current injections which offset one another. These currents come from two separate injection points within the non-volatile memory transistor and are dominant at different points during the erase operation. The first occurring current erases the non-volatile device and the second prevents over erasure.
摘要翻译：用于防止非易失性存储单元中的擦除的方法和结构使用彼此抵消的同时擦除和编程电流注入。这些电流来自非易失性存储晶体管内的两个分离的注入点，并且在擦除操作期间在不同点处是主要的。第一次出现的电流擦除非易失性器件，第二次阻止擦除。

6. 发明授权

US08570809B2 Flash memory devices and systems 有权
标题翻译：闪存设备和系统
公开(公告)号：US08570809B2
公开(公告)日：2013-10-29
申请号：US13340091
申请日：2011-12-29
申请人： Ryan T. Hirose , Bogdan Georgescu , Ashish Amonkar , Sean Mulholland , Vijay Raghavan , Cristinel Zonte
发明人： Ryan T. Hirose , Bogdan Georgescu , Ashish Amonkar , Sean Mulholland , Vijay Raghavan , Cristinel Zonte
IPC分类号： G11C16/04
CPC分类号： G11C16/0466 , G11C16/06 , G11C16/30 , G11C16/3418 , H01L29/792
摘要： Flash memory devices and systems are provided. One flash memory device includes an n-channel metal oxide semiconductor field-effect transistor (nMOSFET), a silicon-oxide-nitride-oxide silicon (SONOS) transistor coupled to the nMOSFET, and an isolated p-well coupled to the nMOSFET and the SONOS transistor. A flash memory system includes an array of memory devices divided into a plurality of paired sectors, a global bit line (GBL) configured to provide high voltage to each respective sector during erase and program operations coupled to each of the plurality of sectors, and a plurality of sense amplifiers coupled between a respective pair of sectors. Methods for operating a flash memory are also provided. One method includes providing high voltage, via the GBL, to the paired sectors during erase and program operations and providing low voltage, via a local bit line, to each memory device during read operations.
摘要翻译：提供了闪存设备和系统。一个闪速存储器件包括n沟道金属氧化物半导体场效应晶体管（nMOSFET），耦合到nMOSFET的氧化硅 - 氧化物 - 氧化物硅（SONOS）晶体管和耦合到nMOSFET的隔离p阱，以及 SONOS晶体管。闪速存储器系统包括划分成多个成对扇区的存储器件阵列，全局位线（GBL）被配置为在擦除期间向每个相应的扇区提供高电压，并且耦合到多个扇区中的每一个扇区，以及耦合在相应的一对扇区之间的多个读出放大器。还提供了操作闪速存储器的方法。一种方法包括在擦除和编程操作期间通过GBL向配对的扇区提供高电压，并且在读取操作期间通过局部位线向每个存储器件提供低电压。

7. 发明授权

US08125835B2 Memory architecture having two independently controlled voltage pumps 有权
标题翻译：具有两个独立控制的电压泵的存储架构
公开(公告)号：US08125835B2
公开(公告)日：2012-02-28
申请号：US12343658
申请日：2008-12-24
申请人： Ryan T. Hirose , Fredrick Jenne , Vijay Raghavan , Igor G. Kouznetsov , Paul Fredrick Ruths , Cristinel Zonte , Bogdan I. Georgescu , Leonard Vasile Gitlan , James Paul Myers
发明人： Ryan T. Hirose , Fredrick Jenne , Vijay Raghavan , Igor G. Kouznetsov , Paul Fredrick Ruths , Cristinel Zonte , Bogdan I. Georgescu , Leonard Vasile Gitlan , James Paul Myers
IPC分类号： G11C16/06 , G11C5/14
CPC分类号： G11C16/14 , G11C5/145 , G11C16/06 , G11C16/12 , G11C16/28 , G11C16/32
摘要： In embodiments described herein, a memory architecture has an array of non-volatile memory cells and a pair of independently controlled voltage pumps. The pair of voltage pumps is coupled for supplying both positive and negative voltage biases to the memory array during program and erase operations, such that a sum of the magnitudes of the positive and negative voltage biases is applied across a storage node of an accessed memory cell.
摘要翻译：在这里描述的实施例中，存储器架构具有非易失性存储器单元阵列和一对独立控制的电压泵。该对电压泵被耦合以在编程和擦除操作期间将正和负电压偏压提供给存储器阵列，使得正和负电压偏置的幅度之和被施加在存取存储器单元的存储节点上。

8. 发明授权

US06654309B1 Circuit and method for reducing voltage stress in a memory decoder 有权
标题翻译：用于降低存储器解码器中的电压应力的电路和方法
公开(公告)号：US06654309B1
公开(公告)日：2003-11-25
申请号：US10029371
申请日：2001-12-20
申请人： Ryan T. Hirose
发明人： Ryan T. Hirose
IPC分类号： G11C800
CPC分类号： G11C8/08 , G11C8/10
摘要： A circuit for generating an output signal, such as a subword line signal, to one or more memory cells of a memory. In one embodiment, the circuit includes four transistors each with a separate select line. In one example, a first switch is provided and has an input coupled with a global word line input signal; a second switch has an input coupled with the output of the first switch at an output node; a third switch has an input coupled with the global word line input signal and the output of the third switch being coupled with the output of the first switch at the output node; and a fourth switch having an input coupled with the output of the third switch at the output node and the output of the fourth switch is coupled with the output of the second switch.
摘要翻译：一种用于向存储器的一个或多个存储器单元产生诸如子字线信号的输出信号的电路。在一个实施例中，电路包括四个晶体管，每个具有单独的选择线。在一个示例中，提供第一开关并具有与全局字线输入信号耦合的输入; 第二开关具有与输出节点处的第一开关的输出耦合的输入; 第三开关具有与全局字线输入信号耦合的输入，并且第三开关的输出与输出节点处的第一开关的输出耦合; 以及第四开关，其具有与输出节点处的第三开关的输出耦合的输入，并且第四开关的输出与第二开关的输出耦合。

9. 发明授权

US06590420B1 Level shifting circuit and method 有权
标题翻译：电平移位电路及方法
公开(公告)号：US06590420B1
公开(公告)日：2003-07-08
申请号：US10029370
申请日：2001-12-20
申请人： Thomas M. Mnich , Ryan T. Hirose
发明人： Thomas M. Mnich , Ryan T. Hirose
IPC分类号： H03K190175
CPC分类号： H03K17/102 , H03K3/356113 , H03K17/302
摘要： A circuit for shifting a signal from a first voltage level referenced to a first voltage reference, to a second voltage level referenced to a second voltage reference, while reducing the gate to source voltages on the output transistors. In one embodiment, the circuit includes six switches. A first switch receives the signal; a second switch receives an inverted representation of the signal; a third switch receives the output of the first switch; a fourth switch receives the output of the second switch; a fifth switch, referenced to the second voltage reference, has an input coupled with the output of the first switch and a control coupled with the output of the fourth switch; and a sixth switch, referenced to the second voltage reference, has an input coupled with the output of the second switch and has a control coupled with the output of the third switch. In one embodiment, when the third switch and the fourth switch are on, the signal is shifted to the second voltage level measured between the input of the fifth switch and the second voltage reference. The third and fourth switches act to prevent the gate to source voltage on the fifth and sixth switches from reaching a high voltage level, such as 10 volts.
摘要翻译：用于将信号从参考第一电压参考的第一电压电平移位到参考第二参考电压的第二电压电平的电路，同时减小输出晶体管上的栅极至源极电压。在一个实施例中，电路包括六个开关。第一个开关接收信号; 第二开关接收信号的反相表示; 第三开关接收第一开关的输出; 第四开关接收第二开关的输出; 参考第二参考电压的第五开关具有与第一开关的输出耦合的输入和与第四开关的输出耦合的控制; 并且参考第二参考电压的第六开关具有与第二开关的输出耦合的输入并具有与第三开关的输出耦合的控制。在一个实施例中，当第三开关和第四开关导通时，信号被转换到在第五开关的输入端和第二参考电压之间测量的第二电压电平。第三和第四开关用于防止第五和第六开关上的栅极源电压达到10伏的高电压电平。

10. 发明授权

US5013943A Single ended sense amplifier with improved data recall for variable bit line current 失效
标题翻译：单端读出放大器，具有改进的位线电流数据调用功能
公开(公告)号：US5013943A
公开(公告)日：1991-05-07
申请号：US393489
申请日：1989-08-11
申请人： Ryan T. Hirose
发明人： Ryan T. Hirose
IPC分类号： G11C17/00 , G11C7/06 , G11C16/06 , H03K5/02
CPC分类号： H03K5/023 , G11C7/067
摘要： A single ended sense amplifier senses whether or not a memory cell in an array conducts current from a bit line conductor to which the sense amplifier is connected. A first stage of the sense amplifier includes a number of separately biased transistors which establish a lower voltage level at a node when the cell conducts current than the higher voltage level at the node when the cell does not conduct current. A second stage of the sensed amplifier includes transistors connected in an inverting arrangement to receive the signal from the node and supply an output signal at an output terminal in response thereto. An equalizing transistor is selectively connected between the node and the output terminal and establishes a high gain bias point voltage at the node when conductive. The high gain bias point in intermediate the higher and lower voltages established at the node by the first stage. As soon as the equalizing transistor becomes nonconductive, the second stage is immediately driven to the correct output signal level by the voltage at the node from the first stage. A precharge transistor is conneced to the bit line to raise the voltage on it to a predetermined high level, thereafter allowing the voltage to decay before sensing the logical state of the cell. Precharging the bit line avoids the uncertainties associated with charging the bit line capacitance.
摘要翻译：单端读出放大器检测阵列中的存储单元是否从连接读出放大器的位线导体传导电流。读出放大器的第一级包括多个单独偏置的晶体管，当单元不传导电流时，当单元传导电流时，在节点处，当节点传导电流时，在节点处建立较低的电压电平。感测放大器的第二级包括以反相装置连接的晶体管，用于接收来自节点的信号，并响应于此在输出端提供输出信号。均衡晶体管选择性地连接在节点和输出端之间，并在导电时在节点处建立高增益偏置点电压。在第一级在节点处建立的较高和较低电压中间的高增益偏置点。一旦均衡晶体管变得不导通，第二级立即从第一级的节点处的电压驱动到正确的输出信号电平。将预充电晶体管连接到位线，以将其上的电压升高到预定的高电平，之后允许电压在感测电池的逻辑状态之前衰减。预充电位线避免了与位线电容充电相关的不确定性。

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