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1. 发明授权

US06658608B1 Apparatus and method for testing ferroelectric memories 失效
标题翻译：用于测试铁电存储器的装置和方法
公开(公告)号：US06658608B1
公开(公告)日：2003-12-02
申请号：US09400210
申请日：1999-09-21
申请人： David A. Kamp , Gary F. Derbenwick
发明人： David A. Kamp , Gary F. Derbenwick
IPC分类号： G11C2900
CPC分类号： G11C29/028 , G11C11/22 , G11C29/50
摘要： A ferroelectric integrated circuit memory device includes: a plurality of memory cells, each including a ferroelectric material, a plurality of conducting lines, each connected to or connectable to a selected one of the memory cells; a drive circuit for applying a predetermined voltage for a predetermined time to a selected one of the conducting lines, the predetermined voltage and time being the normal voltage and time required to perform write or read functions to the memory cell, a function selected from the group of: writing a logic state to the selected memory cell, and reading the selected memory cell; and a mode control circuit responsive to an external signal for adjusting the predetermined voltage or the predetermined time to perform an operation selected from the group consisting of: a partial read of the selected memory cell, and a partial write of the selected memory cell; and applying ferroelectric stress to the memory cell. A known logic state is written to the memory cells, the cells are heated, and then read to provide output data indicative of the likelihood of premature failure for each of the memory cells. Ferroelectric stress is applied to the cells either before or after the cells are written to by repeatedly applying a voltage to the cells corresponding to a logic state opposite that of the written logic state.
摘要翻译：铁电集成电路存储器件包括：多个存储单元，每个存储单元包括铁电材料，多个导线，每个导体线连接到或连接到选定的一个存储单元; 驱动电路，用于将预定电压预定时间施加到所选择的导线中，所述预定电压和时间是对所述存储单元执行写或读功能所需的正常电压和时间，从所述组中选择的功能将逻辑状态写入所选存储单元，并读取所选存储单元; 以及模式控制电路，其响应于外部信号用于调整所述预定电压或所述预定时间以执行从由以下组成的组中选择的操作：所选择的存储器单元的部分读取和所选存储单元的部分写入; 并向存储单元施加铁电应力。将已知的逻辑状态写入存储器单元，单元被加热，然后读取以提供指示每个存储器单元的过早故障的可能性的输出数据。通过对与逻辑状态相反的逻辑状态相对应的单元反复施加电压，在单元被写入之前或之后对电池施加铁电应力。

2. 发明授权

US06031754A Ferroelectric memory with increased switching voltage 失效
标题翻译：铁电存储器具有增加的开关电压
公开(公告)号：US06031754A
公开(公告)日：2000-02-29
申请号：US184474
申请日：1998-11-02
申请人： Gary F. Derbenwick , David A. Kamp , Michael Cordoba , George B. Coombe
发明人： Gary F. Derbenwick , David A. Kamp , Michael Cordoba , George B. Coombe
IPC分类号： G11C11/22 , G11C7/00
CPC分类号： G11C11/22
摘要： A ferroelectric integrated circuit memory includes a memory cell having a ferroelectric capacitor, one electrode of which is connected to a bit line through a transistor, and the other electrode of which is connected to a plate line. The bit line is also connected to system ground through a precharge transistor. In a read cycle, the precharge transistor remains on after the word line goes high connecting the capacitor to the bit line. At least a portion of the linear displacement current that flows to the bit line is drained off to ground via the precharge transistor, thereby increasing the switching voltage across the ferroelectric capacitor. The precharge transistor is turned off before or during the switching of the ferroelectric capacitor. The signal applied to the gate of the precharge transistor is boosted above the supply voltage of the memory to shorten the cycle time.
摘要翻译：铁电集成电路存储器包括具有铁电电容器的存储单元，其一个电极通过晶体管连接到位线，并且另一个电极连接到板线。位线也通过预充电晶体管连接到系统地。在读周期中，在字线连接电容器到位线之后，预充电晶体管保持导通。流过位线的线性位移电流的至少一部分经由预充电晶体管被排出到地，从而增加了铁电电容器两端的开关电压。预充电晶体管在铁电电容器的切换之前或期间被关断。施加到预充电晶体管的栅极的信号被提升到高于存储器的电源电压以缩短周期时间。

3. 发明授权

US06178138B1 Asynchronously addressable clocked memory device and method of operating same 失效
标题翻译：异步寻址时钟存储器件及其操作方法
公开(公告)号：US06178138B1
公开(公告)日：2001-01-23
申请号：US09400212
申请日：1999-09-21
申请人： Gary F. Derbenwick , David A. Kamp , Michael V. Cordoba , Ryan T. Hirose
发明人： Gary F. Derbenwick , David A. Kamp , Michael V. Cordoba , Ryan T. Hirose
IPC分类号： G11C800
CPC分类号： G11C8/06 , G11C8/18
摘要： A timing circuit produces a clock signal. An address buffer circuit receives and stores a first address in a first latch and a second address in a second latch asynchronously with respect to the clock signal. A memory control circuit associated with an array of memory cells accesses a first memory cell in the array corresponding to the first address in a first clocked access cycle, and accesses a second memory cell in the array corresponding to the second address in a second clocked access cycle. If a further address is asynchronously received before said second access cycle, the further address replaces the second address in the second latch.
摘要翻译：定时电路产生时钟信号。地址缓冲电路相对于时钟信号异步地接收并存储第一锁存器中的第一地址和第二锁存器中的第二地址。与存储器单元阵列相关联的存储器控制电路在第一计时的访问周期中访问对应于第一地址的阵列中的第一存储器单元，并且以第二时钟控制存取器访问对应于第二地址的阵列中的第二存储器单元周期。如果在所述第二访问周期之前异步地接收另一地址，则另外的地址替换第二锁存器中的第二地址。

4. 发明授权

US06201731B1 Electronic memory with disturb prevention function 失效
标题翻译：具有防干扰功能的电子记忆体
公开(公告)号：US06201731B1
公开(公告)日：2001-03-13
申请号：US09322490
申请日：1999-05-28
申请人： David A. Kamp , Gary F. Derbenwick , George B. Coombe , Troy A. Meester
发明人： David A. Kamp , Gary F. Derbenwick , George B. Coombe , Troy A. Meester
IPC分类号： C11C1604
CPC分类号： G11C11/22
摘要： A ferroelectric destructive read-out memory system includes a power source, a memory array including a memory cell, and a logic circuit for applying a signal to the memory array. Whenever a low power condition is detected in said power source, a disturb prevent circuit prevents unintended voltages due to the low power condition from disturbing the memory cell. The disturb prevent circuit also stops the operation of the logic circuit for a time sufficient to permit a rewrite cycle to be completed, thereby preventing loss of the data being rewritten.
摘要翻译：铁电破坏性读出存储器系统包括电源，包括存储单元的存储器阵列和用于向存储器阵列施加信号的逻辑电路。每当在所述电源中检测到低功率状况时，干扰防止电路可以防止由于低功率状况引起的非预期电压扰乱存储单元。干扰防止电路也会使逻辑电路的操作停止足以允许完成重写周期的时间，从而防止数据被重写的损失。

5. 发明授权

US08702008B2 RFID transponder chip with a programmable wake-up 有权
标题翻译： RFID应答器芯片具有可编程唤醒功能
公开(公告)号：US08702008B2
公开(公告)日：2014-04-22
申请号：US13488765
申请日：2012-06-05
申请人： James Springer , David A. Kamp
发明人： James Springer , David A. Kamp
IPC分类号： G06K19/06
CPC分类号： G06K19/0701 , G06K19/0723
摘要： An RFID transponder chip includes at least one antenna to pick-up and transmit radio-frequency signals, a rectifier to store charge on at least one capacitor at a rectified voltage from the picked-up radio-frequency signals, a power-on reset circuit to maintain a logic unit in a reset state if the rectified voltage level is less than a power-on reset or wake-up voltage of the power-on reset circuit for operating the logic unit. The RFID transponder chip further includes a non-volatile memory, in which are stored one or several trim values. Said non-volatile memory is directly connected to the power-on reset circuit to be able to provide at least one trim value to trim the power-on reset circuit at a rectified voltage level below a wake-up voltage level.
摘要翻译： RFID应答器芯片包括至少一个用于拾取和发送射频信号的天线，整流器，用于在拾取的射频信号的整流电压下在至少一个电容器上存储电荷，上电复位电路如果整流的电压电平小于用于操作逻辑单元的上电复位电路的上电复位或唤醒电压，则将逻辑单元维持在复位状态。 RFID应答器芯片还包括非易失性存储器，其中存储一个或多个修整值。所述非易失性存储器直接连接到上电复位电路，以能够提供至少一个修整值，以在低于唤醒电压电平的整流电压电平下修整上电复位电路。

6. 发明授权

US08422293B2 Self-powered event detection device 有权
标题翻译：自供电事件检测装置
公开(公告)号：US08422293B2
公开(公告)日：2013-04-16
申请号：US12945138
申请日：2010-11-12
申请人： David A. Kamp , Filippo Marinelli , Thierry Roz
发明人： David A. Kamp , Filippo Marinelli , Thierry Roz
IPC分类号： G11C16/22
CPC分类号： G08B13/06 , E05B39/00 , E05B45/06 , E05B51/023 , E05B67/22 , E05B2047/0058 , E05B2047/0062 , E05B2047/0064 , G08B29/181
摘要： The self-powered detection device comprises a non-volatile memory cell and a sensor activated by a physical or chemical action or phenomenon, this sensor forming an energy harvester transforming energy from the physical or chemical action orphenomenon into an electrical stimulus pulse, the memory cell arranged for storing, by using electrical power of the electrical stimulus pulse, at least a bit of information relative to detection by the sensor of at least a first physical or chemical action or phenomenon. The non-volatile memory cell comprises a FET transistor having a control gate, a first diffusion defining a first input and a second diffusion defining a second input. This FET transistor is set to its written logical state from its initial logical state when, in a detection mode, it receives on a set terminal a voltage stimulus signal resulting from the first physical or chemical action or phenomenon.
摘要翻译：所述自供电检测装置包括非易失性存储单元和由物理或化学作用或现象激活的传感器，所述传感器形成能量收集器，其将能量从物理或化学作用或现象转换成电刺激脉冲，所述存储器单元布置成通过使用电刺激脉冲的电力来存储与传感器相关的至少第一物理或化学作用或现象的至少一点信息。非易失性存储单元包括具有控制栅极的FET晶体管，限定第一输入的第一扩散和限定第二输入的第二扩散。当在检测模式中，它在设定端子上接收由第一物理或化学作用或现象产生的电压刺激信号时，该FET晶体管从其初始逻辑状态被设置为其写入逻辑状态。

7. 发明授权

US06256220B1 Ferroelectric memory with shunted isolated nodes 失效
标题翻译：铁电存储器，分流隔离节点
公开(公告)号：US06256220B1
公开(公告)日：2001-07-03
申请号：US09508305
申请日：2000-03-09
申请人： David A. Kamp
发明人： David A. Kamp
IPC分类号： G11C1127
CPC分类号： H01L27/11502 , G11C11/22
摘要： A ferroelectric memory includes memory cells comprising a transistor having a source/drain, a ferroelectric capacitor having a first electrode and a second electrode. A plate line is connected to each of the second electrodes. In each memory cell, the first electrode is connected to the source/drain of the transistor to create a node that is isolated when the transistor is off. A shunt system directly electrically connects the isolated nodes of a pair of memory cells at a predetermined time to essentially equalize the voltages on the nodes. The shunt may be a Schottky diode, a resistor, and a pair of back-to-back diodes, or a transistor. In the embodiment in which the shunt is a transistor, the shunt line connected to the shunt transistor gate is boosted, there is a shunt transistor connecting each isolated node in a portion of the memory to the adjacent isolated node, and every eight to thirty-two isolated nodes, another shunt transistor connects the chain of isolated nodes to the plate line.
摘要翻译：铁电存储器包括具有源极/漏极的晶体管，具有第一电极和第二电极的铁电电容器的存储单元。板线连接到每个第二电极。在每个存储单元中，第一电极连接到晶体管的源极/漏极，以产生当晶体管截止时被隔离的节点。分流系统在预定时间内直接电连接一对存储器单元的隔离节点，以基本上均衡节点上的电压。分路可以是肖特基二极管，电阻器和一对背对背二极管或晶体管。在分流器是晶体管的实施例中，连接到并联晶体管栅极的并联线被升压，存在将存储器的一部分中的每个隔离节点连接到相邻的隔离节点的并联晶体管，两个隔离节点，另一个分流晶体管将隔离节点链连接到板线。

8. 发明申请

US20120299641A1 TRANSPONDER WITH A MODULATOR 有权
标题翻译：带调制器的TRANSPONDER
公开(公告)号：US20120299641A1
公开(公告)日：2012-11-29
申请号：US13478485
申请日：2012-05-23
申请人： Nicolas Pillin , David A. Kamp
发明人： Nicolas Pillin , David A. Kamp
IPC分类号： H03K3/01
CPC分类号： G06K19/0723 , H01L29/78
摘要： A RFID transponder includes an electronic circuit and an antenna, the electronic circuit being integrated in a p-type substrate and comprising a modulator formed by a PMOS transistor whose drain, electrically connected to a pad of the antenna, and source, connected to the ground of the electronic circuit, are arranged in an n-type well provided in the p-type substrate. The PMOS transistor has a gate driven by a driving circuit which is arranged for providing at least a negative voltage, this negative voltage being low enough for turning on this PMOS transistor in response to a control signal provided by a logical unit of the electronic circuit.
摘要翻译： RFID应答器包括电子电路和天线，该电子电路集成在p型衬底中，并且包括由PMOS晶体管形成的调制器，该PMOS晶体管的漏极电连接到天线的焊盘和源，连接到地的电子电路布置在设置在p型衬底中的n型阱中。 PMOS晶体管具有由驱动电路驱动的栅极，该驱动电路被布置为提供至少一个负电压，该负电压足够低以响应由该电子电路的逻辑单元提供的控制信号而导通该PMOS晶体管。

9. 发明申请

US20080235636A1 Identifying Radiation-Induced Inversions 审中-公开
标题翻译：识别辐射诱导反转
公开(公告)号：US20080235636A1
公开(公告)日：2008-09-25
申请号：US11690607
申请日：2007-03-23
申请人： David A. Kamp
发明人： David A. Kamp
IPC分类号： G06F17/50
CPC分类号： G06F17/5081
摘要： A semiconductor layout design analyzer alerts a user of areas in a semiconductor layout design that may be candidates for radiation induced inversion. The analyzer includes means for gathering information, means for identifying, and means for alerting the user. The means for gathering gathers, from the layout design, placement information for thick oxide, low-doped p-type single crystal silicon, and n-type silicon. The means for identifying identifies, in the layout design, thick oxide overlaying low-doped p-type single crystal silicon and abutting n-type silicon. The means for alerting the user alerts the user of the identified areas of thick oxide.
摘要翻译：半导体布局设计分析仪向用户提供半导体布局设计中可能是辐射诱导反演的候选者的区域。分析器包括用于收集信息的装置，用于识别的手段和用于警告用户的装置。用于收集聚集的手段，从布局设计，厚氧化物，低掺杂p型单晶硅和n型硅的放置信息。用于识别的手段在布局设计中识别厚氧化物覆盖低掺杂p型单晶硅和邻接的n型硅。提醒用户的手段向使用者发出了确认的厚氧化物区域。

10. 发明授权

US06831116B2 Polymeric modifying agents 有权
标题翻译：聚合改性剂
公开(公告)号：US06831116B2
公开(公告)日：2004-12-14
申请号：US09733744
申请日：2000-12-08
申请人： Steven P. Bitler , Ray F. Stewart , Mark A. Wanthal , David A. Kamp , Paul A. Meyers , David D. Taft , Donald A. Schultz
发明人： Steven P. Bitler , Ray F. Stewart , Mark A. Wanthal , David A. Kamp , Paul A. Meyers , David D. Taft , Donald A. Schultz
IPC分类号： C08K910
CPC分类号： C08L101/00 , C08G59/18 , C08J3/24 , C08L63/00 , H05K3/285 , C08L2666/14 , C08L2666/02
摘要： Novel modifying agents contain a sharply-melting crystalline polymer ingredient, preferably a side chain crystalline (SCC) ingredient, and an active chemical ingredient. Such modifying agents, especially when in the form of particles, can be placed in contact with a matrix, will not modify the matrix below the crystalline melting point Tp, but will rapidly modify the matrix above Tp. The active chemical ingredient can react with the matrix, catalyze a reaction of the matrix, or inhibit a reaction of the matrix. Particularly useful compositions are polymer precursors which are storage-stable at low temperatures but which are rapidly converted to crosslinked resins when heated to temperatures above Tp, optionally in the presence of light.
摘要翻译：新型改性剂含有急剧熔化的结晶聚合物成分，优选侧链结晶（SCC）成分和活性化学成分。这种改性剂，特别是当以颗粒形式时，可以与基质接触，不会将基质改性成低于结晶熔点Tp，而是会快速修饰Tp以上的基质。活性化学成分可与基质反应，催化基质的反应或抑制基质的反应。特别有用的组合物是在低温下储存稳定但在加热至高于Tp的温度时可快速转化为交联树脂的聚合物前体，任选地在光存在下。

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