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1. 发明授权

US4993019A Line unit interface circuit 失效
标题翻译：线路单元接口电路
公开(公告)号：US4993019A
公开(公告)日：1991-02-12
申请号：US451436
申请日：1989-12-15
申请人： Gary B. Cole , Michael J. Gingell , Joseph E. Sutherland , Paul M. Matsumura
发明人： Gary B. Cole , Michael J. Gingell , Joseph E. Sutherland , Paul M. Matsumura
IPC分类号： H04Q11/04
CPC分类号： H04Q11/04
摘要： A line unit interface circuit used on line units in a line shelf of a digital loop carrier provides all of the logic necessary to access two subscriber lines to a line unit interface bus connected to common equipment within the line shelf. Information received from the common equipment includes signaling data, configuration data and provisioning data, which is reconfigured and processed by the line unit interface circuit for controlling the subscriber line channels. Configuration data from the common equipment is decoded to assign time slots on the line unit interface bus to the various channels serviced by the line shelf and to further provide for a timing offset between the transmit and receive strobes provided to each subscriber line circuit. A flywheel circuit is used to prevent erroneous time slot assignment in the event of noise or interference on the line unit interface bus.
摘要翻译：在数字环路载波的线路架中的线路单元上使用的线路单元接口电路提供了将两条用户线路连接到线路架内的公共设备的线路单元接口总线所需的所有逻辑。从公共设备接收的信息包括由线路单元接口电路重新配置和处理的用于控制用户线路信道的信令数据，配置数据和供应数据。解码来自公共设备的配置数据，以将线路单元接口总线上的时隙分配给由线路架服务的各种通道，并进一步提供提供给每个用户线电路的发射和接收选通之间的定时偏移。飞轮电路用于在线路单元接口总线上发生噪声或干扰的情况下防止错误的时隙分配。

2. 发明授权

US5185736A Synchronous optical transmission system 失效
标题翻译：同步光传输系统
公开(公告)号：US5185736A
公开(公告)日：1993-02-09
申请号：US351861
申请日：1989-05-12
申请人： Raymond E. Tyrrell , O. Lamar Bishop , William E. Powell , Dale L. Krisher , William H. Stephenson , M. Rodney Briscoe , Hal A. Thorne , Claude M. Hurlocker , V. Paul Runyon , Timothy J. Williams , Joseph E. Sutherland , William B. Weeber , Michael J. Gingell , Kenneth J. Stoia , William J. Fox , Jeffrey P. Jones , Richard M. Czerwiec , Ertugrul Baydar , Heinrich T. Sonnenberg , Richard Peters , Gus C. Sanders , Richard J. Sanders, Jr. , Francis G. Noser , Joseph L. Smith , Jak Yaemsiri , Camille A. Abu-Saba , Patrick M. Farrell , Wenkwei Rou , Victor W. Wilkerson , Mohammad S. Arani , Stephen C. Dunning , Keith Bernhardt , Dana Merrill , Michael Sutton
发明人： Raymond E. Tyrrell , O. Lamar Bishop , William E. Powell , Dale L. Krisher , William H. Stephenson , M. Rodney Briscoe , Hal A. Thorne , Claude M. Hurlocker , V. Paul Runyon , Timothy J. Williams , Joseph E. Sutherland , William B. Weeber , Michael J. Gingell , Kenneth J. Stoia , William J. Fox , Jeffrey P. Jones , Richard M. Czerwiec , Ertugrul Baydar , Heinrich T. Sonnenberg , Richard Peters , Gus C. Sanders , Richard J. Sanders, Jr. , Francis G. Noser , Joseph L. Smith , Jak Yaemsiri , Camille A. Abu-Saba , Patrick M. Farrell , Wenkwei Rou , Victor W. Wilkerson , Mohammad S. Arani , Stephen C. Dunning , Keith Bernhardt , Dana Merrill , Michael Sutton
IPC分类号： H04J3/08 , H04J3/16 , H04Q11/04
CPC分类号： H04J3/1611 , H04J3/08 , H04J2203/0048 , H04J2203/006
摘要： A synchronous optical transmission system for interfacing SONET formatted channels to lower speed channels in either a SONET format or otherwise. The transmission system incorporates a fiber transmission system, terminal multiplexers and add/drop multiplexers that in turn incorporate a plurality of features, such as parallel scrambling circuitry, frame synchronization circuitry and the like.

3. 发明授权

US5033067A Variable shift register 失效
标题翻译：可变移位寄存器
公开(公告)号：US5033067A
公开(公告)日：1991-07-16
申请号：US451415
申请日：1989-12-15
申请人： Gary B. Cole , Michael J. Gingell
发明人： Gary B. Cole , Michael J. Gingell
IPC分类号： H03K5/00 , H03K5/13 , H03K5/135
CPC分类号： H03K5/135 , H03K5/131 , H03K2005/00241
摘要： A variable length shift register is formed of a plurality of flip-flops arranged to form separate shift registers of different lengths. The shift registers are interconnected by multiplexers which connect either the input or the output of each shift register to the input of an adjacent shift register. Control signals are provided to the multiplexers to controllably select the length of the variable shift register by selectively inserting shift registers into the variable shift register and bypassing others.
摘要翻译：可变长度移位寄存器由多个触发器形成，多个触发器被布置成形成不同长度的分离的移位寄存器。移位寄存器通过将每个移位寄存器的输入或输出连接到相邻移位寄存器的输入的多路复用器互连。通过选择性地将移位寄存器插入到可变移位寄存器中并绕过其它寄存器，将控制信号提供给多路复用器以可控地选择可变移位寄存器的长度。

4. 发明授权

US5088089A Apparatus for programmably accessing and assigning time slots in a time division multiplexed communication system 失效
标题翻译：用于在时分复用通信系统中可编程地访问和分配时隙的装置
公开(公告)号：US5088089A
公开(公告)日：1992-02-11
申请号：US451419
申请日：1989-12-15
申请人： Michael J. Gingell , Joseph E. Sutherland
发明人： Michael J. Gingell , Joseph E. Sutherland
IPC分类号： H04Q11/04
CPC分类号： H04Q11/04
摘要： A three-ported apparatus is adapted to interface a serial TDM bus, a local controller and a line unit bus in a telecommunications terminal. All data passing between the TDM bus and the line unit bus is temporarily stored and is accessible to the local controller, allowing the controller to either pass said data without modification or provide modifications thereto. Signaling contained within the data may be translated to a form usable by the line unit through the use of translation tables down-loaded from inventory storage on the line units. For each line unit, the local controller programmably controls time slot assignment, provisioning and inventory information access.
摘要翻译：三端口设备适于在电信终端中连接串行TDM总线，本地控制器和线路单元总线。在TDM总线和线路单元总线之间通过的所有数据被临时存储并且可由本地控制器访问，允许控制器通过所述数据而不进行修改或对其进行修改。数据中包含的信令可以通过使用从线路单元上的库存存储中下载的转换表来转换为线路单元可用的表单。对于每个线路单元，本地控制器可编程地控制时隙分配，配置和库存信息访问。

5. 发明授权

US4288873A Analogue to digital converters 失效
标题翻译：模数转换器
公开(公告)号：US4288873A
公开(公告)日：1981-09-08
申请号：US96728
申请日：1979-11-23
申请人： Michael J. Gingell
发明人： Michael J. Gingell
IPC分类号： H04B14/04 , H04L25/06 , H03K13/01 , H04B12/02
CPC分类号： H04L25/06 , H04B14/046
摘要： A p.c.m. encoder comprises a high accuracy linear A/D converter followed by a digital high pass filter, a d.c. offset circuit and a digital compressor. The high pass filter removes any d.c. offset from the encoded signal and the offset circuit then reintroduces a controlled amount of d.c. offset. By this means the performance can be improved especially in regard to idle noise and crosstalk enhancement.
摘要翻译：一个p.c.m. 编码器包括高精度线性A / D转换器，随后是数字高通滤波器，直流偏移电路和数字压缩器。高通滤波器去除任何直流偏移编码信号和偏移电路然后重新引入受控量的直流。抵消。通过这种方式，可以提高性能，特别是在空闲噪声和串扰增强方面。

6. 发明授权

US5477529A ISDN signal transmission performance monitoring 失效
标题翻译： ISDN信号传输性能监控
公开(公告)号：US5477529A
公开(公告)日：1995-12-19
申请号：US314897
申请日：1994-09-29
申请人： Michael J. Gingell
发明人： Michael J. Gingell
IPC分类号： G06F11/34 , H04J3/14 , H04L1/00 , H04Q11/04 , G06F11/00
CPC分类号： H04L43/0847 , H04J3/14 , H04L1/0083 , H04Q11/045
摘要： During ISDN signal transmission from a network trunk line (21) to an access line (18), a word (202) provided from the network trunk line is broken into two bytes including a data byte (205) and a performance monitoring byte (206). After signal transmission through common equipment (14) and an access line shelf (10), a line card (12) verifies the composite parity of the data byte and the performance monitoring byte to determine if an ISDN signal transmission error has occurred. During ISDN signal transmission from an access line (18) to a network trunk line (21), the line card (12) forms a data byte (305) by combining pairs of data bits from the access line, and simultaneously forms a performance monitoring byte (306) by combining pairs of performance monitoring bits corresponding to the pairs of data bits. After signal transmission of the data byte and performance monitoring byte through the access line shelf and common equipment, logic (65) is provided to determine if an ISDN signal transmission error has occurred. Thereafter, a word (302) is formed on the network trunk line, the word being made up of two bytes including the data byte and a second byte having a parity bit. The parity bit is set equal to the parity of the word if it is determined that a signal transmission error has not occurred and the parity bit is set opposite of the parity of the word if it is determined that a signal transmission error has occurred.
摘要翻译：在从网络中继线（21）到接入线路（18）的ISDN信号传输期间，从网络中继线提供的字（202）被分成包括数据字节（205）和性能监视字节（206）的两个字节）。在通过通用设备（14）和接入线架（10）进行信号传输之后，线卡（12）验证数据字节和性能监视字节的复合奇偶校验，以确定是否发生了ISDN信号传输错误。在从接入线路（18）到网络中继线（21）的ISDN信号传输期间，线路卡（12）通过组合来自接入线路的数据比特组合形成数据字节（305），同时形成性能监视通过组合对对应于数据位对的性能监视位来执行字节（306）。在数据字节和性能监控字节通过接入线架和通用设备进行信号传输之后，提供逻辑（65）以确定是否发生了ISDN信号传输错误。此后，在网络中继线上形成字（302），该字由包括数据字节的两个字节和具有奇偶校验位的第二字节组成。如果确定没有发生信号传输错误，并且如果确定发生信号传输错误，则奇偶校验位被设置为等于字的奇偶校验位，并且奇偶校验位被设置为与字的奇偶校验相反。

7. 发明授权

US5267309A Telephone line unit having programmable read-only memory 失效
标题翻译：具有可编程只读存储器的电话线单元
公开(公告)号：US5267309A
公开(公告)日：1993-11-30
申请号：US616175
申请日：1990-11-20
申请人： Gus C. Sanders , Richard R. Rzonca , Richard M. Czerwiec , Claude M. Hurlocker , Benjamin M. Rice , Michael J. Gingell
发明人： Gus C. Sanders , Richard R. Rzonca , Richard M. Czerwiec , Claude M. Hurlocker , Benjamin M. Rice , Michael J. Gingell
IPC分类号： H04B3/03 , H04M3/00 , H04Q3/42 , H04Q11/04
CPC分类号： H04Q11/04 , H04M3/005
摘要： A line unit, used in a line shelf having a line shelf processor and common logic, is provided with an EEPROM device for storing information relative to the line unit. The stored information includes line unit type identification codes, auto provisioning data, gain and equalization adjustment data and signaling translation tables. The data contained within the EEPROM may be utilized by the line shelf processor to provide automatic initialization and provisioning of the line unit when first inserted into the line shelf, and automatic signaling translation so that line unit signaling becomes compatible with a transmission facility connected to the line shelf. The need for factory preset resistors installed in the line unit may be eliminated by storing within the EEPROM a required gain setting.

8. 发明授权

US5105421A System for controlling multiple line cards on a TDM bus 失效
标题翻译：用于控制TDM总线上多个线路卡的系统
公开(公告)号：US5105421A
公开(公告)日：1992-04-14
申请号：US451431
申请日：1989-12-15
申请人： Michael J. Gingell
发明人： Michael J. Gingell
IPC分类号： H04J3/06 , H04Q11/04
CPC分类号： H04Q11/04 , H04J3/0685
摘要： In a TDM telecommunications terminal, wherein multiple line cards are connected to a TDM bus, each line card location is provided with an identification code. A processor controlled circuit generates a programmable sequence of identification codes which are transmitted on a configuration bus in time slots synchronized with the time slots of the TDM bus. The configuration bus is connected to each of the line cards, which include a comparator logic circuit for comparing the identification of the line card location to the identification codes provided on the configuration bus. When a match is detected, the line card is enabled and is given access to the TDM bus. Through the programmable reassignment of time slots to line cards, concentration may be provided by the system, and a plurality of time slots may be assigned to a single line card to provide broad band service.
摘要翻译：在TDM电信终端中，其中多个线路卡连接到TDM总线，每个线路卡位置都具有识别码。处理器控制电路产生可编程序列的识别码，这些编码序列在与TDM总线的时隙同步的时隙中的配置总线上传输。配置总线连接到每个线路卡，其中包括用于将线路卡位置的识别与配置总线上提供的识别码进行比较的比较器逻辑电路。当检测到匹配时，线卡被启用，并被允许访问TDM总线。通过对线卡的时隙的可编程重新分配，可以由系统提供浓度，并且可以将多个时隙分配给单个线卡以提供宽带服务。

9. 发明授权

US5497363A Expansion shelf for access system and switch block therefor 失效
标题翻译：用于接入系统的扩展机架及其开关块
公开(公告)号：US5497363A
公开(公告)日：1996-03-05
申请号：US310934
申请日：1994-09-29
申请人： Michael J. Gingell
发明人： Michael J. Gingell
IPC分类号： H04J3/08 , H04Q11/04
CPC分类号： H04J3/08 , H04J2203/0041 , H04J2203/0089
摘要： A cross-connect for interfacing high-speed ports and having add/drop multiplexing capabilities for permitting simultaneous access to all individual subscribers may be improved by utilizing a switch block arrangement for allowing downstream subscribers to be switched among each other without the need to be switched upstream through the cross-connect or may alternatively be improved by substituting an expansion shelf in place of a line shelf so as to permit the addition of additional line shelves and hence, additional subscribers. This latter improvement is made possible by assuming that not all subscribers will need access to the cross-connect at the same time. A switch block for such arrangements can output either an input data signal previously stored in a switch memory or a daisy-chain input that is output from another switch block in the arrangement.
摘要翻译：用于接口高速端口的交叉连接和具有用于允许同时访问所有个体用户的分插复用功能的交叉连接可以通过利用交换机组装置来改进，以允许下游用户彼此之间切换而不需要被切换也可以通过用扩展架替代线路架来改进上游，以允许添加额外的线路架，并因此添加额外的用户。通过假设不是所有的订户都需要同时访问交叉连接才能实现后一种改进。用于这种布置的开关块可以输出先前存储在开关存储器中的输入数据信号或在该布置中从另一开关块输出的菊花链输入。

10. 发明授权

US5060229A Serial transport frame format method 失效
标题翻译：串行传输帧格式方法
公开(公告)号：US5060229A
公开(公告)日：1991-10-22
申请号：US351458
申请日：1989-05-12
申请人： Raymond E. Tyrrell , Stephen C. Dunning , Richard J. Sanders, Jr. , Claude M. Hurlocker , Michael J. Gingell , Jeffrey P. Jones
发明人： Raymond E. Tyrrell , Stephen C. Dunning , Richard J. Sanders, Jr. , Claude M. Hurlocker , Michael J. Gingell , Jeffrey P. Jones
IPC分类号： H04J3/12 , H04J3/16
CPC分类号： H04J3/1611 , H04J3/12
摘要： A serial transport frame format is described which transfers data between two locations. The serial transport frame format comprises a fixed number of channels per frame, each channel having a predetermined size. One channel per frame contains frame synchronization information and each channel which conveys data, contains a first portion for the transfer of data and a second portion which contains associated control information.
摘要翻译：描述了在两个位置之间传送数据的串行传输帧格式。串行传输帧格式包括每帧固定数量的信道，每个信道具有预定的大小。每帧一个通道包含帧同步信息，并且传送数据的每个通道包含用于传送数据的第一部分和包含关联控制信息的第二部分。

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