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1. 发明授权

US08018937B2 Pipelined packet switching and queuing architecture 有权
标题翻译：流水线分组交换和排队架构
公开(公告)号：US08018937B2
公开(公告)日：2011-09-13
申请号：US11263473
申请日：2005-10-31
申请人： Garry P. Epps , Michael Laor
发明人： Garry P. Epps , Michael Laor
IPC分类号： H04L12/28
CPC分类号： H04L47/527 , H04L47/10 , H04L47/21 , H04L47/326 , H04L47/50 , H04L47/6215 , H04L49/1546 , H04L49/205 , H04L49/3009 , H04L49/3018 , H04L49/3063 , H04L49/50 , H04L49/552 , H04L49/602 , H04L49/90 , H04L49/9078
摘要： A pipelined linecard architecture for receiving, modifying, switching, buffering, queuing and dequeuing packets for transmission in a communications network. The linecard has two paths: the receive path, which carries packets into the switch device from the network, and the transmit path, which carries packets from the switch to the network. In the receive path, received packets are processed and switched in an asynchronous, multi-stage pipeline utilizing programmable data structures for fast table lookup and linked list traversal. The pipelined switch operates on several packets in parallel while determining each packet's routing destination. Once that determination is made, each packet is modified to contain new routing information as well as additional header data to help speed it through the switch. Each packet is then buffered and enqueued for transmission over the switching fabric to the linecard attached to the proper destination port. The destination linecard may be the same physical linecard as that receiving the inbound packet or a different physical linecard. The transmit path consists of a buffer/queuing circuit similar to that used in the receive path. Both enqueuing and dequeuing of packets is accomplished using CoS-based decision making apparatus and congestion avoidance and dequeue management hardware. The architecture of the present invention has the advantages of high throughput and the ability to rapidly implement new features and capabilities.
摘要翻译：用于接收，修改，切换，缓冲，排队和排队数据包以在通信网络中传输的流水线线卡架构。线路卡具有两条路径：从网络将数据包传送到交换机设备的接收路径，以及将交换机传送到网络的数据包的发送路径。在接收路径中，使用可编程数据结构在快速表查找和链表遍历中，在异步多级流水线中处理和切换接收的分组。流水线交换机在确定每个数据包的路由目的地时并行操作多个数据包。一旦进行了确定，每个数据包被修改为包含新的路由信息以及额外的标题数据，以帮助通过交换机加速速度。然后每个数据包被缓冲并排入队列，以便通过交换结构传输到连接到正确目标端口的线卡。目的线路卡可能与接收入站分组或不同物理线卡一样的物理线卡。发送路径由与接收路径中使用的类似的缓冲器/排队电路组成。使用基于CoS的决策设备和拥塞避免和出队管理硬件来实现分组的入队和出队。本发明的架构具有高吞吐量和快速实现新特征和能力的能力的优点。

2. 发明授权

US07554907B1 High-speed hardware implementation of RED congestion control algorithm 有权
标题翻译：高速硬件实现RED拥塞控制算法
公开(公告)号：US07554907B1
公开(公告)日：2009-06-30
申请号：US10976299
申请日：2004-10-27
申请人： Garry P. Epps , Michael Laor
发明人： Garry P. Epps , Michael Laor
IPC分类号： H04J1/16 , H04L12/28
CPC分类号： H04L47/10 , H04L47/326 , H04L49/205 , H04L49/30 , H04L49/9078
摘要： A pipelined linecard architecture for receiving, modifying, switching, buffering, queuing and dequeuing packets for transmission in a communications network. The linecard has two paths: the receive path, which carries packets into the switch device from the network, and the transmit path, which carries packets from the switch to the network. In the receive path, received packets are processed and switched in an asynchronous, multi-stage pipeline utilizing programmable data structures for fast table lookup and linked list traversal. The pipelined switch operates on several packets in parallel while determining each packet's routing destination. Once that determination is made, each packet is modified to contain new routing information as well as additional header data to help speed it through the switch. Each packet is then buffered and enqueued for transmission over the switching fabric to the linecard attached to the proper destination port. The destination linecard may be the same physical linecard as that receiving the inbound packet or a different physical linecard. The transmit path consists of a buffer/queuing circuit similar to that used in the receive path. Both enqueuing and dequeuing of packets is accomplished using CoS-based decision making apparatus and congestion avoidance and dequeue management hardware. The architecture of the present invention has the advantages of high throughput and the ability to rapidly implement new features and capabilities.
摘要翻译：用于接收，修改，切换，缓冲，排队和排队数据包以在通信网络中传输的流水线线卡架构。线路卡具有两条路径：从网络将数据包传送到交换机设备的接收路径，以及将交换机传送到网络的数据包的发送路径。在接收路径中，使用可编程数据结构在快速表查找和链表遍历中，在异步多级流水线中处理和切换接收的分组。流水线交换机在确定每个数据包的路由目的地时并行操作多个数据包。一旦进行了确定，每个数据包被修改为包含新的路由信息以及额外的标题数据，以帮助通过交换机加速速度。然后每个数据包被缓冲并排入队列，以便通过交换结构传输到连接到正确目标端口的线卡。目的线路卡可能与接收入站分组或不同物理线卡一样的物理线卡。发送路径由与接收路径中使用的类似的缓冲器/排队电路组成。使用基于CoS的决策设备和拥塞避免和出队管理硬件来实现分组的入队和出队。本发明的架构具有高吞吐量和快速实现新特征和能力的能力的优点。

3. 发明授权

US06980552B1 Pipelined packet switching and queuing architecture 有权
标题翻译：流水线分组交换和排队架构
公开(公告)号：US06980552B1
公开(公告)日：2005-12-27
申请号：US10219460
申请日：2002-08-15
申请人： David Belz , Garry P. Epps , Michael Laor , Eyal Oren
发明人： David Belz , Garry P. Epps , Michael Laor , Eyal Oren
IPC分类号： H04L12/28 , H04L12/56
CPC分类号： H04L47/527 , H04L47/10 , H04L47/21 , H04L47/326 , H04L47/50 , H04L47/6215 , H04L49/1546 , H04L49/205 , H04L49/3009 , H04L49/3018 , H04L49/3063 , H04L49/50 , H04L49/552 , H04L49/602 , H04L49/90 , H04L49/9078
摘要： A pipelined linecard architecture for receiving, modifying, switching, buffering, queuing and dequeuing packets for transmission in a communications network. The linecard has two paths: the receive path, which carries packets into the switch device from the network, and the transmit path, which carries packets from the switch to the network. In the receive path, received packets are processed and switched in a multi-stage pipeline utilizing programmable data structures for fast table lookup and linked list traversal. The pipelined switch operates on several packets in parallel while determining each packet's routing destination. Once that determination is made, each packet is modified to contain new routing information as well as additional header data to help speed it through the switch. Using bandwidth management techniques, each packet is then buffered and enqueued for transmission over the switching fabric to the linecard attached to the proper destination port. The destination linecard may be the same physical linecard as that receiving the inbound packet or a different physical linecard. The transmit path includes a buffer/queuing circuit similar to that used in the receive path and can include another pipelined switch. Both enqueuing and dequeuing of packets is accomplished using CoS-based decision making apparatus, congestion avoidance, and bandwidth management hardware.
摘要翻译：用于接收，修改，切换，缓冲，排队和排队数据包以在通信网络中传输的流水线线卡架构。线路卡具有两条路径：从网络将数据包传送到交换机设备的接收路径，以及将交换机传送到网络的数据包的发送路径。在接收路径中，使用可编程数据结构在多级流水线中对接收到的数据包进行处理和切换，以便进行快速表查找和链表遍历。流水线交换机在确定每个数据包的路由目的地时并行操作多个数据包。一旦进行了确定，每个数据包被修改为包含新的路由信息以及额外的标题数据，以帮助通过交换机加速速度。使用带宽管理技术，每个数据包然后被缓冲并排入队列，以便通过交换结构传输到连接到适当目标端口的线卡。目的线路卡可能与接收入站分组或不同物理线卡一样的物理线卡。发送路径包括类似于在接收路径中使用的缓冲器/排队电路，并且可以包括另一流水线开关。使用基于CoS的决策设备，拥塞避免和带宽管理硬件来实现分组的入队和出队。

4. 发明授权

US06778546B1 High-speed hardware implementation of MDRR algorithm over a large number of queues 有权
标题翻译：高速硬件实现MDRR算法的大量队列
公开(公告)号：US06778546B1
公开(公告)日：2004-08-17
申请号：US09503976
申请日：2000-02-14
申请人： Garry P. Epps , Michael Laor
发明人： Garry P. Epps , Michael Laor
IPC分类号： H04L1256
CPC分类号： H04L47/6225 , H04L47/50 , H04L47/527 , H04L47/6215 , H04L49/90 , H04L49/901 , H04L49/9052
摘要： A pipelined linecard architecture for receiving, modifying, switching, buffering, queuing and dequeuing packets for transmission in a communications network. The linecard has two paths: the receive path, which carries packets into the switch device from the network, and the transmit path, which carries packets from the switch to the network. In the receive path, received packets are processed and switched in an asynchronous, multi-stage pipeline utilizing programmable data structures for fast table lookup and linked list traversal. The pipelined switch operates on several packets in parallel while determining each packet's routing destination. Once that determination is made, each packet is modified to contain new routing information as well as additional header data to help speed it through the switch. Each packet is then buffered and enqueued for transmission over the switching fabric to the linecard attached to the proper destination port. The destination linecard may be the same physical linecard as that receiving the inbound packet or a different physical linecard. The transmit path consists of a buffer/queuing circuit similar to that used in the receive path. Both enqueuing and dequeuing of packets is accomplished using CoS-based decision making apparatus and congestion avoidance and dequeue management hardware. The architecture of the present invention has the advantages of high throughput and the ability to rapidly implement new features and capabilities.
摘要翻译：用于接收，修改，切换，缓冲，排队和排队数据包以在通信网络中传输的流水线线卡架构。线路卡具有两条路径：从网络将数据包传送到交换机设备的接收路径，以及将交换机传送到网络的数据包的发送路径。在接收路径中，使用可编程数据结构在快速表查找和链表遍历中，在异步多级流水线中处理和切换接收的分组。流水线交换机在确定每个数据包的路由目的地时并行操作多个数据包。一旦进行了确定，每个数据包被修改为包含新的路由信息以及额外的标题数据，以帮助通过交换机加速速度。然后每个数据包被缓冲并排入队列，以便通过交换结构传输到连接到正确目标端口的线卡。目的线路卡可能与接收入站分组或不同物理线卡一样的物理线卡。发送路径由与接收路径中使用的类似的缓冲器/排队电路组成。使用基于CoS的决策设备和拥塞避免和出队管理硬件来实现分组的入队和出队。本发明的架构具有高吞吐量和快速实现新特征和能力的能力的优点。

5. 发明授权

US06424649B1 Synchronous pipelined switch using serial transmission 失效
标题翻译：同步流水线开关采用串行传输
公开(公告)号：US06424649B1
公开(公告)日：2002-07-23
申请号：US09001270
申请日：1997-12-31
申请人： Michael Laor , Garry P. Epps
发明人： Michael Laor , Garry P. Epps
IPC分类号： H04L1256
CPC分类号： H04L12/5601 , H04J3/0685 , H04L49/106 , H04L49/608 , H04L2012/5674
摘要： The invention provides a method and system for operating a switch, in which incoming data cells are converted from parallel to serial for synchronous input to a switch interconnect, converted from serial to parallel for parallel switching, converted from parallel to serial for synchronous output from the switch interconnect, and converted from serial to parallel for output. The switch interconnect and its input and output interfaces are controlled by a single frequency source, so that all serial data communication paths into and out of the switch interconnect are phase synchronized to within one clock cycle. A single frequency source for the switch system is coupled to the input interfaces, to output interfaces, and to the switch interconnect. The input interfaces each include a PLL which synchronizes to the single frequency source once for all serial communication to the switch interconnect. The switch interconnect includes one PLL for each input interface which synchronizes to the serial input from that input interface, and one PLL for each output interface which synchronizes to the single frequency source once for all serial communication to the output interface. Similarly, the output interfaces each include a PLL which synchronizes to the serial output from the switch interconnect. The switch interconnect is coupled to the single frequency source and operates in phase therewith.
摘要翻译：本发明提供了一种用于操作开关的方法和系统，其中输入数据单元从并行转换为串行以用于同步输入到开关互连，从串行转换为并行用于并行切换，从并行转换为串行以用于同步输出开关互连，并从串行转换为并行输出。开关互连及其输入和输出接口由单个频率源控制，使得进入和离开交换机互连的所有串行数据通信路径在一个时钟周期内被相位同步。用于交换机系统的单个频率源耦合到输入接口，输出接口和交换机互连。每个输入接口包括一个与单个频率源同步的PLL，用于与交换机互连的所有串行通信。开关互连包括每个输入接口的一个PLL，与该输入接口的串行输入同步，每个输出接口的一个PLL与单个频率源同步一次，用于输出接口的所有串行通信。类似地，输出接口各自包括与交换机互连的串行输出同步的PLL。开关互连耦合到单个频率源并与其同相运行。

6. 发明申请

US20120314707A1 Pipelined Packet Switching And Queuing Architecture 有权
标题翻译：流水线分组交换和排队架构
公开(公告)号：US20120314707A1
公开(公告)日：2012-12-13
申请号：US13230069
申请日：2011-09-12
申请人： Garry P. Epps , Michael Laor
发明人： Garry P. Epps , Michael Laor
IPC分类号： H04L12/56
CPC分类号： H04L47/527 , H04L47/10 , H04L47/21 , H04L47/326 , H04L47/50 , H04L47/6215 , H04L49/1546 , H04L49/205 , H04L49/3009 , H04L49/3018 , H04L49/3063 , H04L49/50 , H04L49/552 , H04L49/602 , H04L49/90 , H04L49/9078
摘要： A pipelined linecard architecture for receiving, modifying, switching, buffering, queuing and dequeuing packets for transmission in a communications network is disclosed. The linecard has two paths: a receive path and a transmit path. In the receive path, received packets are processed and switched in an asynchronous, multi-stage pipeline. The pipelined switch operates on several packets in parallel while determining each packet's routing destination. Once that determination is made, each packet is modified to contain new routing information. Each packet is buffered and enqueued for transmission over the switching fabric to a destination linecard. The transmit path includes a buffer/queuing circuit similar to that used in the receive path. Both enqueuing and dequeuing of packets is accomplished using a CoS-based decision making apparatus.
摘要翻译：公开了一种用于在通信网络中接收，修改，切换，缓冲，排队和排队分组以进行传输的流水线线路卡架构。线卡有两条路径：接收路径和发送路径。在接收路径中，接收的分组在异步多级流水线中进行处理和切换。流水线交换机在确定每个数据包的路由目的地时并行操作多个数据包。一旦确定，每个数据包被修改为包含新的路由信息。每个数据包被缓冲并排入队列，以便通过交换结构传输到目标线卡。发送路径包括与在接收路径中使用的类似的缓冲器/排队电路。分组的入队和出队均使用基于CoS的决策设备完成。

7. 发明授权

US07286525B1 Synchronous pipelined switch using serial transmission 有权
标题翻译：同步流水线开关采用串行传输
公开(公告)号：US07286525B1
公开(公告)日：2007-10-23
申请号：US10176819
申请日：2002-06-21
申请人： Michael Laor , Garry P. Epps
发明人： Michael Laor , Garry P. Epps
IPC分类号： H04L12/56
CPC分类号： H04L12/5601 , H04J3/0685 , H04L49/106 , H04L49/608 , H04L2012/5674
摘要： The invention provides a method and system for operating a switch, in which incoming data cells are converted from parallel to serial for synchronous input to a switch interconnect, converted from serial to parallel for parallel switching, converted from parallel to serial for synchronous output from the switch interconnect, and converted from serial to parallel for output. The switch interconnect and its input and output interfaces are controlled by a single frequency source, so that all serial data communication paths into and out of the switch interconnect are phase synchronized to within one clock cycle. A single frequency source for the switch system is coupled to the input interfaces, to output interfaces, and to the switch interconnect. The input interfaces each include a PLL which synchronizes to the single frequency source once for all serial communication to the switch interconnect. The switch interconnect includes one PLL for each input interface which synchronizes to the serial input from that input interface, and one PLL for each output interface which synchronizes to the single frequency source once for all serial communication to the output interface. Similarly, the output interfaces each include a PLL which synchronizes to the serial output from the switch interconnect. The switch interconnect is coupled to the single frequency source and operates in phase therewith.
摘要翻译：本发明提供了一种用于操作开关的方法和系统，其中输入数据单元从并行转换为串行以用于同步输入到开关互连，从串行转换为并行用于并行切换，从并行转换为串行以用于同步输出开关互连，并从串行转换为并行输出。开关互连及其输入和输出接口由单个频率源控制，使得进入和离开交换机互连的所有串行数据通信路径在一个时钟周期内被相位同步。用于交换机系统的单个频率源耦合到输入接口，输出接口和交换机互连。每个输入接口包括一个与单个频率源同步的PLL，用于与交换机互连的所有串行通信。开关互连包括每个输入接口的一个PLL，与该输入接口的串行输入同步，每个输出接口的一个PLL与单个频率源同步一次，用于输出接口的所有串行通信。类似地，输出接口各自包括与交换机互连的串行输出同步的PLL。开关互连耦合到单个频率源并与其同相操作。

8. 发明授权

US06977930B1 Pipelined packet switching and queuing architecture 有权
标题翻译：流水线分组交换和排队架构
公开(公告)号：US06977930B1
公开(公告)日：2005-12-20
申请号：US09503552
申请日：2000-02-14
申请人： Garry P. Epps , Michael Laor
发明人： Garry P. Epps , Michael Laor
IPC分类号： H04L12/28 , H04L12/56
CPC分类号： H04L47/527 , H04L47/10 , H04L47/21 , H04L47/326 , H04L47/50 , H04L47/6215 , H04L49/1546 , H04L49/205 , H04L49/3009 , H04L49/3018 , H04L49/3063 , H04L49/50 , H04L49/552 , H04L49/602 , H04L49/90 , H04L49/9078
摘要： A pipelined linecard architecture for receiving, modifying, switching, buffering, queuing and dequeuing packets for transmission in a communications network. The linecard has two paths: the receive path, which carries packets into the switch device from the network, and the transmit path, which carries packets from the switch to the network. In the receive path, received packets are processed and switched in an asynchronous, multi-stage pipeline utilizing programmable data structures for fast table lookup and linked list traversal. The pipelined switch operates on several packets in parallel while determining each packet's routing destination. Once that determination is made, each packet is modified to contain new routing information as well as additional header data to help speed it through the switch. Each packet is then buffered and enqueued for transmission over the switching fabric to the linecard attached to the proper destination port. The destination linecard may be the same physical linecard as that receiving the inbound packet or a different physical linecard. The transmit path consists of a buffer/queuing circuit similar to that used in the receive path. Both enqueuing and dequeuing of packets is accomplished using CoS-based decision making apparatus and congestion avoidance and dequeue management hardware. The architecture of the present invention has the advantages of high throughput and the ability to rapidly implement new features and capabilities.
摘要翻译：用于接收，修改，切换，缓冲，排队和排队数据包以在通信网络中传输的流水线线卡架构。线路卡具有两条路径：从网络将数据包传送到交换机设备的接收路径，以及将交换机传送到网络的数据包的发送路径。在接收路径中，使用可编程数据结构在快速表查找和链表遍历中，在异步多级流水线中处理和切换接收的分组。流水线交换机在确定每个数据包的路由目的地时并行操作多个数据包。一旦进行了确定，每个数据包被修改为包含新的路由信息以及额外的标题数据，以帮助通过交换机加速速度。然后每个数据包被缓冲并排入队列，以便通过交换结构传输到连接到正确目标端口的线卡。目的线路卡可能与接收入站分组或不同物理线卡一样的物理线卡。发送路径由与接收路径中使用的类似的缓冲器/排队电路组成。使用基于CoS的决策设备和拥塞避免和出队管理硬件来实现分组的入队和出队。本发明的架构具有高吞吐量和快速实现新特征和能力的能力的优点。

9. 发明授权

US08665875B2 Pipelined packet switching and queuing architecture 有权
标题翻译：流水线分组交换和排队架构
公开(公告)号：US08665875B2
公开(公告)日：2014-03-04
申请号：US13230069
申请日：2011-09-12
申请人： Garry P. Epps , Michael Laor
发明人： Garry P. Epps , Michael Laor
IPC分类号： H04L12/26
CPC分类号： H04L47/527 , H04L47/10 , H04L47/21 , H04L47/326 , H04L47/50 , H04L47/6215 , H04L49/1546 , H04L49/205 , H04L49/3009 , H04L49/3018 , H04L49/3063 , H04L49/50 , H04L49/552 , H04L49/602 , H04L49/90 , H04L49/9078
摘要： A pipelined linecard architecture for receiving, modifying, switching, buffering, queuing and dequeuing packets for transmission in a communications network is disclosed. The linecard has two paths: a receive path and a transmit path. In the receive path, received packets are processed and switched in an asynchronous, multi-stage pipeline. The pipelined switch operates on several packets in parallel while determining each packet's routing destination. Once that determination is made, each packet is modified to contain new routing information. Each packet is buffered and enqueued for transmission over the switching fabric to a destination linecard. The transmit path includes a buffer/queuing circuit similar to that used in the receive path. Both enqueuing and dequeuing of packets is accomplished using a CoS-based decision making apparatus.
摘要翻译：公开了一种用于在通信网络中接收，修改，切换，缓冲，排队和排队分组以进行传输的流水线线路卡架构。线卡有两条路径：接收路径和发送路径。在接收路径中，接收的分组在异步多级流水线中进行处理和切换。流水线交换机在确定每个数据包的路由目的地时并行操作多个数据包。一旦确定，每个数据包被修改为包含新的路由信息。每个数据包被缓冲并排入队列，以便通过交换结构传输到目标线卡。发送路径包括与在接收路径中使用的类似的缓冲器/排队电路。分组的入队和出队均使用基于CoS的决策设备完成。

10. 发明授权

US07643486B2 Pipelined packet switching and queuing architecture 有权
标题翻译：流水线分组交换和排队架构
公开(公告)号：US07643486B2
公开(公告)日：2010-01-05
申请号：US11242453
申请日：2005-10-03
申请人： David Belz , Garry P. Epps , Michael Laor , Eyal Oren
发明人： David Belz , Garry P. Epps , Michael Laor , Eyal Oren
IPC分类号： H04L12/28 , H04L12/56
CPC分类号： H04L47/527 , H04L47/10 , H04L47/21 , H04L47/326 , H04L47/50 , H04L47/6215 , H04L49/1546 , H04L49/205 , H04L49/3009 , H04L49/3018 , H04L49/3063 , H04L49/50 , H04L49/552 , H04L49/602 , H04L49/90 , H04L49/9078
摘要： A pipelined linecard architecture for receiving, modifying, switching, buffering, queuing and dequeuing packets for transmission in a communications network. The linecard has two paths: the receive path, which carries packets into the switch device from the network, and the transmit path, which carries packets from the switch to the network. In the receive path, received packets are processed and switched in a multi-stage pipeline utilizing programmable data structures for fast table lookup and linked list traversal. The pipelined switch operates on several packets in parallel while determining each packet's routing destination. Once that determination is made, each packet is modified to contain new routing information as well as additional header data to help speed it through the switch. Using bandwidth management techniques, each packet is then buffered and enqueued for transmission over the switching fabric to the linecard attached to the proper destination port. The destination linecard may be the same physical linecard as that receiving the inbound packet or a different physical linecard. The transmit path includes a buffer/queuing circuit similar to that used in the receive path and can include another pipelined switch. Both enqueuing and dequeuing of packets is accomplished using CoS-based decision making apparatus, congestion avoidance, and bandwidth management hardware.
摘要翻译：用于接收，修改，切换，缓冲，排队和排队数据包以在通信网络中传输的流水线线卡架构。线路卡具有两条路径：从网络将数据包传送到交换机设备的接收路径，以及将交换机传送到网络的数据包的发送路径。在接收路径中，使用可编程数据结构在多级流水线中对接收到的数据包进行处理和切换，以便进行快速表查找和链表遍历。流水线交换机在确定每个数据包的路由目的地时并行操作多个数据包。一旦进行了确定，每个数据包被修改为包含新的路由信息以及额外的标题数据，以帮助通过交换机加速速度。使用带宽管理技术，每个数据包然后被缓冲并排入队列，以便通过交换结构传输到连接到适当目标端口的线卡。目的线路卡可能与接收入站分组或不同物理线卡一样的物理线卡。发送路径包括类似于在接收路径中使用的缓冲器/排队电路，并且可以包括另一流水线开关。使用基于CoS的决策设备，拥塞避免和带宽管理硬件来实现分组的入队和出队。

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