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1. 发明申请

US20060183347A1 Method of depositing a silicon dioxide-comprising layer in the fabrication of integrated circuitry 失效
公开(公告)号：US20060183347A1
公开(公告)日：2006-08-17
申请号：US11404541
申请日：2006-04-14
申请人： Garo Derderian , Chris Hill
发明人： Garo Derderian , Chris Hill
IPC分类号： H01L21/31
CPC分类号： H01L21/02164 , C23C16/0272 , C23C16/402 , H01L21/02145 , H01L21/02214 , H01L21/02271 , H01L21/31612 , H01L21/76227
摘要： This invention includes methods of depositing a silicon dioxide comprising layer in the fabrication of integrated circuitry, and to methods of forming trench isolation in the fabrication of integrated circuitry. In one implementation, a method of depositing a silicon dioxide comprising layer in the fabrication of integrated circuitry includes flowing an aluminum containing organic precursor to a chamber containing a semiconductor substrate effective to deposit an aluminum comprising layer over the substrate. An alkoxysilanol is flowed to the substrate comprising the aluminum comprising layer within the chamber effective to deposit a silicon dioxide comprising layer over the substrate. At least one halogen is provided within the chamber during at least one of the aluminum containing organic precursor flowing and the alkoxysilanol flowing under conditions effective to reduce rate of the deposit of the silicon dioxide comprising layer over the substrate than would otherwise occur under identical conditions but for providing the halogen. Other implementations are contemplated.

2. 发明申请

US20060110936A1 Method of increasing deposition rate of silicon dioxide on a catalyst 有权
公开(公告)号：US20060110936A1
公开(公告)日：2006-05-25
申请号：US11321437
申请日：2005-12-29
申请人： Chris Hill , Garo Derderian
发明人： Chris Hill , Garo Derderian
IPC分类号： H01L21/31
CPC分类号： C23C16/45534 , C23C16/403 , C23C16/45525 , H01L21/02164 , H01L21/02178 , H01L21/022 , H01L21/02203 , H01L21/02216 , H01L21/02274 , H01L21/0228 , H01L21/316 , H01L21/31683 , H01L21/31695
摘要： Methods for forming dielectric layers, and structures and devices resulting from such methods, and systems that incorporate the devices are provided. The invention provides an aluminum oxide/silicon oxide laminate film formed by sequentially exposing a substrate to an organoaluminum catalyst to form a monolayer over the surface, remote plasmas of oxygen and nitrogen to convert the organoaluminum layer to a porous aluminum oxide layer, and a silanol precursor to form a thick layer of silicon dioxide over the porous oxide layer. The process provides an increased rate of deposition of the silicon dioxide, with each cycle producing a thick layer of silicon dioxide of about 120 Å over the layer of porous aluminum oxide.

3. 发明申请

US20060008972A1 Method of forming trench isolation in the fabrication of integrated circuitry 失效
标题翻译：在集成电路制造中形成沟槽隔离的方法
公开(公告)号：US20060008972A1
公开(公告)日：2006-01-12
申请号：US11215934
申请日：2005-08-31
申请人： Garo Derderian , Chris Hill
发明人： Garo Derderian , Chris Hill
IPC分类号： H01L21/8238
CPC分类号： H01L21/02164 , C23C16/0272 , C23C16/402 , H01L21/02145 , H01L21/02214 , H01L21/02271 , H01L21/31612 , H01L21/76227
摘要： This invention includes methods of depositing a silicon dioxide comprising layer in the fabrication of integrated circuitry, and to methods of forming trench isolation in the fabrication of integrated circuitry. In one implementation, a method of depositing a silicon dioxide comprising layer in the fabrication of integrated circuitry includes flowing an aluminum containing organic precursor to a chamber containing a semiconductor substrate effective to deposit an aluminum comprising layer over the substrate. An alkoxysilanol is flowed to the substrate comprising the aluminum comprising layer within the chamber effective to deposit a silicon dioxide comprising layer over the substrate. At least one halogen is provided within the chamber during at least one of the aluminum containing organic precursor flowing and the alkoxysilanol flowing under conditions effective to reduce rate of the deposit of the silicon dioxide comprising layer over the substrate than would otherwise occur under identical conditions but for providing the halogen. Other implementations are contemplated.
摘要翻译：本发明包括在制造集成电路中沉积含二氧化硅的层的方法以及在集成电路的制造中形成沟槽隔离的方法。在一个实施方案中，在集成电路的制造中沉积含二氧化硅的层的方法包括将含有铝的有机前体流动到含有半导体衬底的室，该半导体衬底有效地在衬底上沉积含铝层。烷氧基硅烷流到包含室内的包含铝的基材的基材中，有效地将二氧化硅包含层沉积在基材上。在含铝的有机前驱体和烷氧基硅烷中的至少一种中，至少有一个卤素在有效地降低衬底上沉积二氧化硅层的条件下流动的条件下流动，这与在相同条件下将会发生的情况相反，但是用于提供卤素。考虑其他实现。

4. 发明申请

US20060189159A1 Methods of depositing a silicon dioxide comprising layer in the fabrication of integrated circuitry, and methods of forming trench isolation in the fabrication of integrated circuitry 失效
标题翻译：在制造集成电路中沉积含二氧化硅的层的方法以及在集成电路的制造中形成沟槽隔离的方法
公开(公告)号：US20060189159A1
公开(公告)日：2006-08-24
申请号：US11404703
申请日：2006-04-14
申请人： Garo Derderian , Chris Hill
发明人： Garo Derderian , Chris Hill
IPC分类号： H01L21/31
CPC分类号： H01L21/02164 , C23C16/0272 , C23C16/402 , H01L21/02145 , H01L21/02214 , H01L21/02271 , H01L21/31612 , H01L21/76227
摘要： This invention includes methods of depositing a silicon dioxide comprising layer in the fabrication of integrated circuitry, and to methods of forming trench isolation in the fabrication of integrated circuitry. In one implementation, a method of depositing a silicon dioxide comprising layer in the fabrication of integrated circuitry includes flowing an aluminum containing organic precursor to a chamber containing a semiconductor substrate effective to deposit an aluminum comprising layer over the substrate. An alkoxysilanol is flowed to the substrate comprising the aluminum comprising layer within the chamber effective to deposit a silicon dioxide comprising layer over the substrate. At least one halogen is provided within the chamber during at least one of the aluminum containing organic precursor flowing and the alkoxysilanol flowing under conditions effective to reduce rate of the deposit of the silicon dioxide comprising layer over the substrate than would otherwise occur under identical conditions but for providing the halogen. Other implementations are contemplated.
摘要翻译：本发明包括在制造集成电路中沉积含二氧化硅的层的方法以及在集成电路的制造中形成沟槽隔离的方法。在一个实施方案中，在集成电路的制造中沉积含二氧化硅的层的方法包括将含有铝的有机前体流动到含有半导体衬底的室，该半导体衬底有效地在衬底上沉积含铝层。烷氧基硅烷流到包含室内的包含铝的基材的基材中，有效地将二氧化硅包含层沉积在基材上。在含铝的有机前驱体和烷氧基硅烷中的至少一种中，至少有一个卤素在有效地降低衬底上沉积二氧化硅层的条件下流动的条件下流动，这与在相同条件下将会发生的情况相反，但是用于提供卤素。考虑其他实现。

5. 发明申请

US20060046518A1 Method of increasing deposition rate of silicon dioxide on a catalyst 有权
公开(公告)号：US20060046518A1
公开(公告)日：2006-03-02
申请号：US10930149
申请日：2004-08-31
申请人： Chris Hill , Garo Derderian
发明人： Chris Hill , Garo Derderian
IPC分类号： H01L21/31
CPC分类号： C23C16/45534 , C23C16/403 , C23C16/45525 , H01L21/02164 , H01L21/02178 , H01L21/022 , H01L21/02203 , H01L21/02216 , H01L21/02274 , H01L21/0228 , H01L21/316 , H01L21/31683 , H01L21/31695
摘要： Methods for forming dielectric layers, and structures and devices resulting from such methods, and systems that incorporate the devices are provided. The invention provides an aluminum oxide/silicon oxide laminate film formed by sequentially exposing a substrate to an organoaluminum catalyst to form a monolayer over the surface, remote plasmas of oxygen and nitrogen to convert the organoaluminum layer to a porous aluminum oxide layer, and a silanol precursor to form a thick layer of silicon dioxide over the porous oxide layer. The process provides an increased rate of deposition of the silicon dioxide, with each cycle producing a thick layer of silicon dioxide of about 120 Å over the layer of porous aluminum oxide.

6. 发明申请

US20060189158A1 Method of depositing a silicon dioxide-comprising layer in the fabrication of integrated circuitry 失效
标题翻译：在制造集成电路中沉积含二氧化硅的层的方法
公开(公告)号：US20060189158A1
公开(公告)日：2006-08-24
申请号：US11404542
申请日：2006-04-14
申请人： Garo Derderian , Chris Hill
发明人： Garo Derderian , Chris Hill
IPC分类号： H01L21/31
CPC分类号： H01L21/02164 , C23C16/0272 , C23C16/402 , H01L21/02145 , H01L21/02214 , H01L21/02271 , H01L21/31612 , H01L21/76227
摘要： This invention includes methods of depositing a silicon dioxide comprising layer in the fabrication of integrated circuitry, and to methods of forming trench isolation in the fabrication of integrated circuitry. In one implementation, a method of depositing a silicon dioxide comprising layer in the fabrication of integrated circuitry includes flowing an aluminum containing organic precursor to a chamber containing a semiconductor substrate effective to deposit an aluminum comprising layer over the substrate. An alkoxysilanol is flowed to the substrate comprising the aluminum comprising layer within the chamber effective to deposit a silicon dioxide comprising layer over the substrate. At least one halogen is provided within the chamber during at least one of the aluminum containing organic precursor flowing and the alkoxysilanol flowing under conditions effective to reduce rate of the deposit of the silicon dioxide comprising layer over the substrate than would otherwise occur under identical conditions but for providing the halogen. Other implementations are contemplated.
摘要翻译：本发明包括在制造集成电路中沉积含二氧化硅的层的方法以及在集成电路的制造中形成沟槽隔离的方法。在一个实施方案中，在集成电路的制造中沉积含二氧化硅的层的方法包括将含有铝的有机前体流动到含有半导体衬底的室，该半导体衬底有效地在衬底上沉积含铝层。烷氧基硅烷流到包含室内的包含铝的基材的基材中，有效地将二氧化硅包含层沉积在基材上。在含铝的有机前驱体和烷氧基硅烷中的至少一种中，至少有一个卤素在有效地降低衬底上沉积二氧化硅层的条件下流动的条件下流动，这与在相同条件下将会发生的情况相反，但是用于提供卤素。考虑其他实现。

7. 发明授权

US07390710B2 Protection of tunnel dielectric using epitaxial silicon 有权
标题翻译：使用外延硅保护隧道电介质
公开(公告)号：US07390710B2
公开(公告)日：2008-06-24
申请号：US10932795
申请日：2004-09-02
申请人： Garo Derderian , Nirmal Ramaswamy
发明人： Garo Derderian , Nirmal Ramaswamy
IPC分类号： H01L21/8238
CPC分类号： H01L27/11521 , H01L27/115 , H01L29/42336
摘要： Layers of epitaxial silicon are used to protect the tunnel dielectric layer of a floating-gate memory cell from excessive oxidation or removal during the formation of shallow trench isolation (STI) regions. Following trench formation, the layers of epitaxial silicon are grown from silicon-containing layers on opposing sides of the tunnel dielectric layer, thereby permitting their thickness to be limited to approximately one-half of the thickness of the tunnel dielectric layer. The epitaxial silicon may be oxidized prior to filling the trench with a dielectric material or a dielectric fill may occur prior to oxidizing at least the epitaxial silicon covering the ends of the tunnel dielectric layer.
摘要翻译：使用外延硅层来保护浮栅存储器单元的隧道介电层免于在形成浅沟槽隔离（STI）区域期间的过度氧化或去除。在沟槽形成之后，外延硅层从隧道介电层的相对侧上的含硅层生长，从而允许其厚度被限制为隧道介电层的厚度的大约二分之一。外延硅可以在用电介质材料填充沟槽之前被氧化，或者在氧化至少覆盖隧道介电层的端部的外延硅之前可能发生电介质填充。

8. 发明申请

US20070148932A9 Systems and methods for forming niobium and/or vanadium containing layers using atomic layer deposition 失效
标题翻译：使用原子层沉积形成铌和/或含钒层的系统和方法
公开(公告)号：US20070148932A9
公开(公告)日：2007-06-28
申请号：US10923315
申请日：2004-08-20
申请人： Garo Derderian , Donald Westmoreland , Stefan Uhlenbrook
发明人： Garo Derderian , Donald Westmoreland , Stefan Uhlenbrook
IPC分类号： H01L21/20
CPC分类号： H01L21/02205 , C23C16/405 , C23C16/45553 , H01L21/02175 , H01L21/0228 , H01L21/28562 , H01L21/3141 , H01L21/31604 , H01L28/90
摘要： A method of forming (and an apparatus for forming) a metal containing layer on a substrate, particularly a semiconductor substrate or substrate assembly for use in manufacturing a semiconductor or memory device structure, using one or more precursor compounds that include niobium and/or vanadium and using an atomic layer deposition process including a plurality of deposition cycles.
摘要翻译：使用一种或多种包括铌和/或钒的前体化合物在基板上，特别是用于制造半导体或存储器件结构的半导体衬底或衬底组件中形成（以及用于形成）含金属层的方法以及使用包括多个沉积循环的原子层沉积工艺。

9. 发明申请

US20070141835A1 Methods of fabricating interconnects for semiconductor components 有权
标题翻译：制造半导体元件互连的方法
公开(公告)号：US20070141835A1
公开(公告)日：2007-06-21
申请号：US11705897
申请日：2007-02-13
申请人： Kyle Kirby , Shuang Meng , Garo Derderian
发明人： Kyle Kirby , Shuang Meng , Garo Derderian
IPC分类号： H01L21/4763 , H01L21/44
CPC分类号： C23C16/34 , C23C16/45525 , C23C18/1608 , C23C18/1879 , C23C18/36 , H01L21/28562 , H01L21/288 , H01L21/76898 , H01L23/481 , H01L24/11 , H01L24/13 , H01L2224/0231 , H01L2224/02372 , H01L2224/03002 , H01L2224/0401 , H01L2224/13009 , H01L2224/13024 , H01L2224/13099 , H01L2224/13111 , H01L2924/0001 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01022 , H01L2924/01023 , H01L2924/01029 , H01L2924/01033 , H01L2924/01046 , H01L2924/01047 , H01L2924/01072 , H01L2924/01073 , H01L2924/01074 , H01L2924/01078 , H01L2924/01082 , H01L2924/014 , H01L2924/04941 , H01L2924/12042 , H01L2924/14 , H01L2924/00014 , H01L2924/00
摘要： In one aspect, the invention encompasses a method of fabricating an interconnect for a semiconductor component. A semiconductor substrate is provided, and an opening is formed which extends entirely through the substrate. A first material is deposited along sidewalls of the opening at a temperature of less than or equal to about 200° C. The deposition can comprise one or both of atomic layer deposition and chemical vapor deposition, and the first material can comprise a metal nitride. A solder-wetting material is formed over a surface of the first material. The solder-wetting material can comprise, for example, nickel. Subsequently, solder is provided within the opening and over the solder-wetting material.
摘要翻译：一方面，本发明包括制造用于半导体部件的互连的方法。提供半导体衬底，并且形成完全贯穿衬底的开口。第一种材料在小于或等于约200℃的温度下沿着开口的侧壁沉积。沉积可以包括原子层沉积和化学气相沉积中的一个或两个，并且第一材料可以包括金属氮化物。在第一材料的表面上形成焊料润湿材料。焊料润湿材料可以包括例如镍。随后，在开口内和焊料润湿材料之上提供焊料。

10. 发明申请

US20070138529A1 MIS capacitor and method of formation 有权
标题翻译： MIS电容器和形成方法
公开(公告)号：US20070138529A1
公开(公告)日：2007-06-21
申请号：US11545481
申请日：2006-10-11
申请人： Cem Basceri , Garo Derderian
发明人： Cem Basceri , Garo Derderian
IPC分类号： H01L29/94
CPC分类号： H01L28/40 , H01L21/3141 , H01L21/31604 , H01L21/31616 , H01L21/31637 , H01L21/31645 , H01L27/10852 , H01L28/55 , H01L28/84 , H01L28/91 , H01L29/94
摘要： An MIS capacitor with low leakage and high capacitance is disclosed. A layer of hemispherical grained polysilicon (HSG) is formed as a lower electrode. Prior to the dielectric formation, the hemispherical grained polysilicon layer may be optionally subjected to a nitridization or anneal process. A dielectric layer of aluminum oxide (Al2O3), or a composite stack of interleaved layers of aluminum oxide and other metal oxide dielectric materials, is fabricated over the hemispherical grained polysilicon layer and after the optional nitridization or anneal process. The dielectric layer of aluminum oxide (Al2O3) or the aluminum oxide composite stack may be optionally subjected to a post-deposition treatment to further increase the capacitance and decrease the leakage current. A metal nitride upper electrode is formed over the dielectric layer or the composite stack by a deposition technique or by atomic layer deposition.
摘要翻译：公开了具有低泄漏和高电容的MIS电容器。形成半球状晶粒多晶硅层（HSG）作为下电极。在电介质形成之前，半球状晶粒多晶硅层可以任选地进行氮化或退火工艺。在半球形颗粒上制造氧化铝（Al 2 O 3 3）的介电层或氧化铝和其它金属氧化物电介质材料的交错层的复合叠层多晶硅层和可选的氮化或退火工艺后。氧化铝（Al 2 O 3 3）的电介质层或氧化铝复合叠层可以任选地进行后沉积处理以进一步增加电容并减小漏电流。通过沉积技术或通过原子层沉积在电介质层或复合叠层上形成金属氮化物上电极。

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