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1. 发明授权

US07136306B2 Single bit nonvolatile memory cell and methods for programming and erasing thereof 失效
标题翻译：单位非易失性存储单元及其编程和擦除方法
公开(公告)号：US07136306B2
公开(公告)日：2006-11-14
申请号：US10680878
申请日：2003-10-07
申请人： Gang Xue , Jan Van Houdt
发明人： Gang Xue , Jan Van Houdt
IPC分类号： G11C16/04 , G11C5/06
CPC分类号： G11C16/0466 , G11C16/10 , G11C16/14 , G11C16/26
摘要： A method for programming a single bit nonvolatile memory cell integrated on a metal-dielectric-semiconductor technology chip. The memory cell comprises a semiconductor substrate including a source, a drain, and a channel in-between the source and the drain. The memory cell further comprises a control gate that comprises a gate electrode and a dielectric stack. The gate electrode is separated from the channel by the dielectric stack. Further, the dielectric stack comprises at least one charge storage dielectric layer. The method for programming the memory cell comprises applying electrical ground to the source, applying a first voltage having a first polarity to the drain, applying a second voltage of the first polarity to the control gate; and applying a third voltage having a second polarity opposite to the first polarity to the semiconductor substrate.
摘要翻译：一种用于编程集成在金属 - 电介质 - 半导体技术芯片上的单个位非易失性存储单元的方法。存储单元包括在源极和漏极之间包括源极，漏极和沟道的半导体衬底。该存储单元还包括一个包括栅电极和电介质叠层的控制栅极。栅极通过电介质堆叠与沟道分离。此外，电介质叠层包括至少一个电荷存储电介质层。用于对存储单元进行编程的方法包括将电接地施加到源极，向漏极施加具有第一极性的第一电压，将第一极性的第二电压施加到控制栅极; 以及将具有与所述第一极性相反的第二极性的第三电压施加到所述半导体衬底。

2. 发明授权

US06653682B1 Non-volatile electrically alterable semiconductor memory device 失效
标题翻译：非易失性电可变半导体存储器件
公开(公告)号：US06653682B1
公开(公告)日：2003-11-25
申请号：US09696616
申请日：2000-10-25
申请人： Jan Van Houdt , Gang Xue
发明人： Jan Van Houdt , Gang Xue
IPC分类号： H01L29788
CPC分类号： H01L29/66825 , G11C16/0425 , H01L21/28273 , H01L29/42324 , H01L29/7886
摘要： Apparatus for an electrically programmable and erasable memory device and methods for programming, erasing and reading the device. The device has a single transistor including a source, a drain, a control gate and a floating gate positioned between the control gate, the source and the drain, where the floating gate is capacitively coupled to the drain. At least one part of the floating gate is partly positioned between the control gate, the drain and the source, and the other part of the floating gate overlaps with the drain. Further, the single transistor of the device includes means for injecting hot electrons generated by the drain induced secondary impact ionization onto the floating gate. Additionally, the means are arranged to induce Fowler-Nordheim tunnelling of charges from the floating gate to the drain.
摘要翻译：用于电可编程和可擦除存储器件的装置以及用于编程，擦除和读取器件的方法。器件具有单个晶体管，其包括位于控制栅极，源极和漏极之间的源极，漏极，控制栅极和浮置栅极，其中浮动栅极电容耦合到漏极。浮栅的至少一部分部分地位于控制栅极，漏极和源极之间，并且浮栅的另一部分与漏极重叠。此外，器件的单个晶体管包括用于将由漏极引起的次级冲击电离产生的热电子注入到浮动栅极上的装置。另外，这些装置被设置成将Fowler-Nordheim隧道从浮动栅极引导到漏极。

3. 发明授权

US5583811A Transistor structure for erasable and programmable semiconductor memory devices 失效
标题翻译：用于可擦除和可编程半导体存储器件的晶体管结构
公开(公告)号：US5583811A
公开(公告)日：1996-12-10
申请号：US275016
申请日：1994-07-13
申请人： Jan Van Houdt , Guido Groeseneken , Herman Maes
发明人： Jan Van Houdt , Guido Groeseneken , Herman Maes
IPC分类号： G11C16/04 , H01L27/105 , H01L27/115 , H01L29/423 , H01L29/788
CPC分类号： G11C16/0425 , H01L27/11526 , H01L29/42328 , H01L29/7881 , H01L29/7883 , H01L27/105 , H01L27/115
摘要： A programmable EEPROM cell structure consisting in a split-gate structure in series with a coupling capacitor between the floating gate and an additional program gate in order to provide enhanced injection efficiency. The electron injection is controlled by a control gate at the source side. The area of the coupling capacitor is selected with a substantial coupling factor to a high voltage onto the floating gate during programming so as to produce hot-electron injection at the split point in the channel region between the control gate and the floating gate. Submicrosecond programming at a 5 V drain voltage can thereby be achieved.
摘要翻译：一个可编程EEPROM单元结构，其分立栅极结构与浮置栅极和附加程序栅极之间的耦合电容器串联，以提供增强的注入效率。电子注入由源极侧的控制栅极控制。耦合电容器的面积在编程期间以对浮栅的高电压的实质耦合因子进行选择，以便在控制栅极和浮置栅极之间的沟道区域中的分裂点处产生热电子注入。因此可以实现在5V漏极电压下的微秒编程。

4. 发明授权

US06144586A Methods of erasing a memory device and a method of programming a memory device for low-voltage and low-power applications 有权
标题翻译：擦除存储器件的方法和用于低电压和低功率应用的存储器件的编程方法
公开(公告)号：US06144586A
公开(公告)日：2000-11-07
申请号：US505234
申请日：2000-02-16
申请人： Jan Van Houdt , Dirk Wellekens
发明人： Jan Van Houdt , Dirk Wellekens
IPC分类号： G11C16/04 , G11C16/14 , H01L21/336 , H01L21/8247 , H01L27/115 , H01L29/423 , H01L29/788 , H01L29/792 , G11C16/00
CPC分类号： G11C16/14 , G11C16/0425 , H01L29/42328 , Y10S977/943
摘要： A method of erasing and a method of programming a nonvolatile memory cell in a chip is disclosed. Said cell comprises a semiconductor substrate including a source and a drain region and a channel therebetween, a floating gate extending over a portion of said channel, a control gate extending over another portion of the channel region, and a program gate capacitively coupled through a dielectric layer to said floating gate. The methods or schemes are using substantially the lowest possible voltage to erase a nonvolatile memory cell of the floating-gate type without having the SILC problem. Therefore, these schemes are expected to allow a further scaling of the minimum feature size of Flash memory products which is necessary for cost reduction and density increase.The present invention also aims to further decrease the voltages necessary to erase/program the memory device without degrading the corresponding performance.
摘要翻译：公开了一种擦除方法和芯片中的非易失性存储单元的编程方法。所述单元包括半导体衬底，其包括源区和漏区及其间的沟道，在所述沟道的一部分上延伸的浮动栅极，在沟道区的另一部分上延伸的控制栅极以及通过电介质电容耦合的程序栅极层到所述浮动门。所述方法或方案基本上使用尽可能低的电压来擦除浮栅型非易失性存储单元，而不会出现SILC问题。因此，预期这些方案可以进一步缩小成本降低和密度增加所需的闪存产品的最小特征尺寸。本发明还旨在进一步降低擦除/编程存储器件所需的电压，而不降低对应的性能。

5. 发明授权

US07232722B2 Method of making a multibit non-volatile memory 有权
标题翻译：制作多位非易失性存储器的方法
公开(公告)号：US07232722B2
公开(公告)日：2007-06-19
申请号：US11040516
申请日：2005-01-20
申请人： Jan Van Houdt , Luc Haspeslagh
发明人： Jan Van Houdt , Luc Haspeslagh
IPC分类号： H01L21/336
CPC分类号： H01L27/11502 , G11C16/0458 , H01L21/2815 , H01L21/28273 , H01L29/7887 , H01L29/7923
摘要： The present invention relates to a method of making a multibit non-volatile memory and especially to a method of making a flash memory such as a fast-programmable Flash EEPROM (Electrically Erasable Programmable Read-Only Memory) device relying on hot-electron injection for programming which is particularly suited for high density low-voltage low-power applications and employs only two polysilicon layers.
摘要翻译：本发明涉及一种制造多位非易失性存储器的方法，尤其涉及一种制造闪存的方法，例如依靠热电子注入的快速可编程闪存EEPROM（电可擦除可编程只读存储器）装置编程特别适用于高密度低压低功率应用，仅采用两个多晶硅层。

6. 发明授权

US6115285A Device and method for multi-level charge/storage and reading out 有权
标题翻译：用于多级充电/存储和读出的装置和方法
公开(公告)号：US6115285A
公开(公告)日：2000-09-05
申请号：US202481
申请日：1998-12-14
申请人： Donato Montanari , Jan Van Houdt , Guido Groeseneken , Herman Maes
发明人： Donato Montanari , Jan Van Houdt , Guido Groeseneken , Herman Maes
IPC分类号： G11C16/02 , G11C11/56 , G11C16/06 , H01L21/8247 , H01L27/115 , H01L29/788 , H01L29/792 , G11C16/04
CPC分类号： G11C11/5642 , G11C11/5621 , G11C11/5628 , G11C11/5635 , G11C2211/5631
摘要： The present invention discloses a memory device having memory cells capable of storing three or more charge leves in said memory cell. The cells can be programmed according to a method including a single pulse charge level injection mechanism in said cells. The method does not require a program verify scheme, permits increased speed during programming, and reduces the area necessary for storing one bit of information. The memory device of the present invention further includes information write or storage or programmation means, information erase means and information read-out means. Another object of the present invention is to provide a method and a circuit that implements said method for determining the charge level of a memory cell having t possible levels (t being larger than or equal to three). The circuit measures the similarity of the memory cell drain current with the drain current of each of n references, determines the one reference which is the most similar to the memory cell and thereby identifies the charge level of said memory cell.
摘要翻译： PCT No.PCT / EP97 / 00561 Sec。 371 1998年12月14日第 102（e）日期1998年12月14日PCT 1997年2月7日提交PCT公布。第WO97 / 48099号公报日期1997年12月18日本发明公开了一种具有能够在所述存储单元中存储三个或更多个充电电荷的存储单元的存储器件。可以根据包括所述单元中的单个脉冲电荷注入机制的方法对单元进行编程。该方法不需要程序验证方案，允许在编程期间增加速度，并减少存储一位信息所需的面积。本发明的存储装置还包括信息写入或存储或编程装置，信息擦除装置和信息读出装置。本发明的另一个目的是提供一种实现用于确定具有t个可能电平（t大于或等于3个）的存储单元的电荷电平的所述方法的方法和电路。电路测量存储单元漏极电流与n个参考中每一个的漏极电流的相似度，确定与存储单元最相似的一个参考，从而识别所述存储单元的电荷电平。

7. 发明授权

US6058043A Method of erasing a memory device and a method of programming a memory device for low-voltage and low-power applications 有权
标题翻译：擦除存储器件的方法和用于低电压和低功率应用的存储器件的编程方法
公开(公告)号：US6058043A
公开(公告)日：2000-05-02
申请号：US149723
申请日：1998-09-08
申请人： Jan Van Houdt , Dirk Wellekens
发明人： Jan Van Houdt , Dirk Wellekens
IPC分类号： G11C16/04 , G11C16/14 , H01L21/336 , H01L21/8247 , H01L27/115 , H01L29/423 , H01L29/788 , H01L29/792 , G11C16/00
CPC分类号： G11C16/14 , G11C16/0425 , H01L29/42328 , Y10S977/943
摘要： A method of erasing and a method of programming a nonvolatile memory cell in a chip is disclosed. Said cell comprises a semiconductor substrate including a source and a drain region and a channel therebetween, a floating gate extending over a portion of said channel, a control gate extending over another portion of the channel region, and a program gate capacitively coupled through a dielectric layer to said floating gate. The methods or schemes are using substantially the lowest possible voltage to erase a nonvolatile memory cell of the floating-gate type without having the SILC problem. Therefore, these schemes are expected to allow a further scaling of the minimum feature size of Flash memory products which is necessary for cost reduction and density increase. The present invention also aims to further decrease the voltages necessary to erase/program the memory device without degrading the corresponding performance.
摘要翻译：公开了一种擦除方法和芯片中的非易失性存储单元的编程方法。所述单元包括半导体衬底，其包括源区和漏区及其间的沟道，在所述沟道的一部分上延伸的浮置栅极，在沟道区的另一部分上延伸的控制栅极以及电容耦合通过电介质层到所述浮动门。所述方法或方案基本上使用尽可能低的电压来擦除浮栅型非易失性存储单元，而不会出现SILC问题。因此，预期这些方案可以进一步缩小成本降低和密度增加所需的闪存产品的最小特征尺寸。本发明还旨在进一步降低擦除/编程存储器件所需的电压，而不降低对应的性能。

8. 发明授权

US5583810A Method for programming a semiconductor memory device 失效
标题翻译：半导体存储器件编程方法
公开(公告)号：US5583810A
公开(公告)日：1996-12-10
申请号：US80225
申请日：1993-06-21
申请人： Jan Van Houdt , Guido Groeseneken , Herman Maes
发明人： Jan Van Houdt , Guido Groeseneken , Herman Maes
IPC分类号： G11C16/04 , H01L27/105 , H01L27/115 , H01L29/423 , H01L29/788
CPC分类号： G11C16/0425 , H01L27/11526 , H01L29/42328 , H01L29/7881 , H01L29/7883 , H01L27/105 , H01L27/115
摘要： A programmable EEPROM cell structure consisting in a split-gate structure in series with a coupling capacitor between the floating gate and an additional program gate in order to provide enhanced injection efficiency. The electron injection is controlled by a control gate at the source side. The area of the coupling capacitor is selected with a substantial coupling factor to a high voltage onto the floating gate during programming so as to produce hot-electron injection at the split point in the channel region between the control gate and the floating gate. Submicrosecond programming at a 5 V drain voltage can thereby be achieved.
摘要翻译：一个可编程EEPROM单元结构，其分立栅极结构与浮置栅极和附加程序栅极之间的耦合电容器串联，以提供增强的注入效率。电子注入由源极侧的控制栅极控制。耦合电容器的面积在编程期间以对浮栅的高电压的实质耦合因子进行选择，以便在控制栅极和浮置栅极之间的沟道区域中的分裂点处产生热电子注入。因此可以实现在5V漏极电压下的微秒编程。

9. 发明授权

US06897517B2 Multibit non-volatile memory and method 有权
标题翻译：多位非易失性存储器和方法
公开(公告)号：US06897517B2
公开(公告)日：2005-05-24
申请号：US10603426
申请日：2003-06-24
申请人： Jan Van Houdt , Luc Haspeslagh
发明人： Jan Van Houdt , Luc Haspeslagh
IPC分类号： G11C16/04 , H01L21/28 , H01L27/115 , H01L29/788 , H01L29/792
CPC分类号： H01L27/11502 , G11C16/0458 , H01L21/2815 , H01L21/28273 , H01L29/7887 , H01L29/7923
摘要： A memory is described having a semiconductor substrate of a first conductivity type, a first and a second junction region of a second conductivity type, whereby said first and said second junction region are part of respectively a first and a second bitline. A select gate is provided which is part of a wordline running perpendicular to said first and said second bitline.Read, write and erase functions for each cell make use of only two polysilicon layers which simplifies manufacture and each memory cell has at least two locations for storing a charge representing at least one bit.
摘要翻译：描述了具有第一导电类型的半导体衬底，第二导电类型的第一和第二结区的存储器，由此所述第一和第二结区分别是第一和第二位线的一部分。提供选择门，其是垂直于所述第一和所述第二位线的字线的一部分。每个单元的读，写和擦除功能仅使用两个多晶硅层，这简化了制造，每个存储单元具有至少两个用于存储表示至少一个位的电荷的位置。

10. 发明授权

US06486509B1 Non-volatile memory cell 失效
标题翻译：非易失性存储单元
公开(公告)号：US06486509B1
公开(公告)日：2002-11-26
申请号：US09530614
申请日：2000-09-11
申请人： Jan Van Houdt
发明人： Jan Van Houdt
IPC分类号： H01L2976
CPC分类号： G11C16/14 , G11C16/0425 , H01L29/42328 , Y10S977/943
摘要： The present invention is related to a non-volatile memory cell, comprising a semiconductor substrate including a source region and a drain region with a channel region there between; a floating gate of a conductive material at least partially extending over a first portion of said channel region; a control gate of a conductive material and at least partially extending over a second portion of the channel region; an additional program gate of a conductive material and at least partially overlapping said floating gate and being capacitively coupled through a dielectric layer to said floating gate.
摘要翻译：本发明涉及一种非易失性存储单元，包括一个半导体衬底，该半导体衬底包括一个源极区和一个在其间具有沟道区的漏极区; 至少部分地延伸在所述沟道区的第一部分上的导电材料的浮动栅极; 导电材料的控制栅极，并且至少部分地延伸在所述沟道区域的第二部分上; 导电材料的附加编程栅极，并且至少部分地与所述浮动栅极重叠并且通过电介质层电容耦合到所述浮动栅极。

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