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1. 发明授权

US09135185B2 Die-stacked memory device providing data translation 有权
标题翻译：提供数据转换的堆叠式存储器件
公开(公告)号：US09135185B2
公开(公告)日：2015-09-15
申请号：US13726143
申请日：2012-12-23
申请人： Gabriel H. Loh , Bradford M. Beckmann , James M. O'Connor , Michael Ignatowski , Michael J. Schulte , Lisa R. Hsu , Nuwan S. Jayasena
发明人： Gabriel H. Loh , Bradford M. Beckmann , James M. O'Connor , Michael Ignatowski , Michael J. Schulte , Lisa R. Hsu , Nuwan S. Jayasena
IPC分类号： G06F12/02 , G06F12/10
CPC分类号： G06F12/1027 , H01L25/18 , H01L2224/16225 , H01L2225/06565 , H01L2924/0002 , H01L2924/15311 , H01L2924/00
摘要： A die-stacked memory device incorporates a data translation controller at one or more logic dies of the device to provide data translation services for data to be stored at, or retrieved from, the die-stacked memory device. The data translation operations implemented by the data translation controller can include compression/decompression operations, encryption/decryption operations, format translations, wear-leveling translations, data ordering operations, and the like. Due to the tight integration of the logic dies and the memory dies, the data translation controller can perform data translation operations with higher bandwidth and lower latency and power consumption compared to operations performed by devices external to the die-stacked memory device.
摘要翻译：芯片堆叠存储器件在器件的一个或多个逻辑管芯上并入数据转换控制器，以提供数据转换服务，用于存储在芯片堆叠存储器件中或从芯片堆叠的存储器件中取出的数据。由数据转换控制器实现的数据转换操作可以包括压缩/解压缩操作，加密/解密操作，格式转换，磨损均衡转换，数据排序操作等。由于逻辑管芯和存储器管芯的紧密集成，与堆叠式存储器件外部的器件执行的操作相比，数据转换控制器可以执行具有更高带宽和更低延迟和功耗的数据转换操作。

2. 发明申请

US20130159812A1 MEMORY ARCHITECTURE FOR READ-MODIFY-WRITE OPERATIONS 审中-公开
标题翻译：用于读写操作的存储器架构
公开(公告)号：US20130159812A1
公开(公告)日：2013-06-20
申请号：US13328393
申请日：2011-12-16
申请人： Gabriel H. LOH , James M. O'Connor , Michael Ignatowski , Nuwan S. Jayasena , Bradford M. Beckmann
发明人： Gabriel H. LOH , James M. O'Connor , Michael Ignatowski , Nuwan S. Jayasena , Bradford M. Beckmann
IPC分类号： H03M13/09 , G06F11/10 , G06F12/00
CPC分类号： G11C5/02 , G06F11/1048
摘要： According to one embodiment, a memory architecture implemented method is provided, where the memory architecture includes a logic chip and one or more memory chips on a single die, and where the method comprises: reading values of data from the one or more memory chips to the logic chip, where the one or more memory chips and the logic chip are on a single die; modifying, via the logic chip on the single die, the values of data; and writing, from the logic chip to the one or more memory chips, the modified values of data.
摘要翻译：根据一个实施例，提供了一种存储器架构实现的方法，其中存储器架构包括逻辑芯片和单个管芯上的一个或多个存储器芯片，并且其中该方法包括：从一个或多个存储器芯片读取数据的值逻辑芯片，其中一个或多个存储器芯片和逻辑芯片在单个芯片上; 通过单个芯片上的逻辑芯片修改数据的值; 并从逻辑芯片向一个或多个存储器芯片写入修改的数据值。

3. 发明申请

US20140040532A1 STACKED MEMORY DEVICE WITH HELPER PROCESSOR 审中-公开
标题翻译：具有帮助处理器的堆叠存储器件
公开(公告)号：US20140040532A1
公开(公告)日：2014-02-06
申请号：US13567958
申请日：2012-08-06
申请人： Yasuko Watanabe , Gabriel H. Loh , James M. O'Connor , Michael Ignatowski , Nuwan S. Jayasena
发明人： Yasuko Watanabe , Gabriel H. Loh , James M. O'Connor , Michael Ignatowski , Nuwan S. Jayasena
IPC分类号： G06F12/00
CPC分类号： G06F13/1668 , G06F13/4234 , Y02D10/14 , Y02D10/151
摘要： A processing system comprises one or more processor devices and other system components coupled to a stacked memory device having a set of stacked memory layers and a set of one or more logic layers. The set of logic layers implements a helper processor that executes instructions to perform tasks in response to a task request from the processor devices or otherwise on behalf of the other processor devices. The set of logic layers also includes a memory interface coupled to memory cell circuitry implemented in the set of stacked memory layers and coupleable to the processor devices. The memory interface operates to perform memory accesses for the processor devices and for the helper processor. By virtue of the helper processor's tight integration with the stacked memory layers, the helper processor may perform certain memory-intensive operations more efficiently than could be performed by the external processor devices.
摘要翻译：处理系统包括一个或多个处理器设备和耦合到具有一组堆叠存储器层和一组一个或多个逻辑层的堆叠存储器件的其他系统组件。这组逻辑层实现了一个辅助处理器，其执行指令以响应于来自处理器设备的任务请求或以其他方式代表其他处理器设备执行任务。该组逻辑层还包括耦合到在该组堆叠存储器层中实现并且可耦合到处理器设备的存储器单元电路的存储器接口。存储器接口操作以对处理器设备和辅助处理器执行存储器访问。由于辅助处理器与堆叠的存储器层的紧密集成，辅助处理器可以比由外部处理器设备执行的更有效地执行某些存储器密集型操作。

4. 发明授权

US09697147B2 Stacked memory device with metadata management 有权
公开(公告)号：US09697147B2
公开(公告)日：2017-07-04
申请号：US13567945
申请日：2012-08-06
申请人： Gabriel H. Loh , James M. O'Connor , Bradford M. Beckmann , Michael Ignatowski
发明人： Gabriel H. Loh , James M. O'Connor , Bradford M. Beckmann , Michael Ignatowski
IPC分类号： H03M13/00 , G06F13/16 , G06F11/10
CPC分类号： G06F13/1668 , G06F11/1004 , Y02D10/14
摘要： A processing system comprises one or more processor devices and other system components coupled to a stacked memory device having a set of stacked memory layers and a set of one or more logic layers. The set of logic layers implements a metadata manager that offloads metadata management from the other system components. The set of logic layers also includes a memory interface coupled to memory cell circuitry implemented in the set of stacked memory layers and coupleable to the devices external to the stacked memory device. The memory interface operates to perform memory accesses for the external devices and for the metadata manager. By virtue of the metadata manager's tight integration with the stacked memory layers, the metadata manager may perform certain memory-intensive metadata management operations more efficiently than could be performed by the external devices.

5. 发明申请

US20140040698A1 STACKED MEMORY DEVICE WITH METADATA MANGEMENT 有权
标题翻译：具有元数据的堆叠存储器件
公开(公告)号：US20140040698A1
公开(公告)日：2014-02-06
申请号：US13567945
申请日：2012-08-06
申请人： Gabriel H. Loh , James M. O'Connor , Bradford M. Beckmann , Michael Ignatowski
发明人： Gabriel H. Loh , James M. O'Connor , Bradford M. Beckmann , Michael Ignatowski
IPC分类号： G06F12/00 , G06F12/10 , G06F11/08
CPC分类号： G06F13/1668 , G06F11/1004 , Y02D10/14
摘要： A processing system comprises one or more processor devices and other system components coupled to a stacked memory device having a set of stacked memory layers and a set of one or more logic layers. The set of logic layers implements a metadata manager that offloads metadata management from the other system components. The set of logic layers also includes a memory interface coupled to memory cell circuitry implemented in the set of stacked memory layers and coupleable to the devices external to the stacked memory device. The memory interface operates to perform memory accesses for the external devices and for the metadata manager. By virtue of the metadata manager's tight integration with the stacked memory layers, the metadata manager may perform certain memory-intensive metadata management operations more efficiently than could be performed by the external devices.
摘要翻译：处理系统包括一个或多个处理器设备和耦合到具有一组堆叠存储器层和一组一个或多个逻辑层的堆叠存储器件的其他系统组件。逻辑层集合实现了从其他系统组件卸载元数据管理的元数据管理器。逻辑层集合还包括耦合到存储单元电路的存储器接口，该存储器单元电路被实现在该组堆叠存储器层中，并且可耦合到堆叠存储器件外部的器件。存储器接口用于对外部设备和元数据管理器执行存储器访问。由于元数据管理器与堆叠存储器层的紧密集成，元数据管理器可以比由外部设备执行的更有效地执行某些存储器密集型元数据管理操作。

6. 发明授权

US09201777B2 Quality of service support using stacked memory device with logic die 有权
标题翻译：使用具有逻辑模块的堆叠存储器件的服务质量支持
公开(公告)号：US09201777B2
公开(公告)日：2015-12-01
申请号：US13726144
申请日：2012-12-23
申请人： Lisa R. Hsu , Gabriel H. Loh , Bradford M. Beckmann , Michael Ignatowski
发明人： Lisa R. Hsu , Gabriel H. Loh , Bradford M. Beckmann , Michael Ignatowski
IPC分类号： G06F12/00 , G06F12/02
CPC分类号： G06F12/00 , G06F12/0246 , G06F13/16 , H01L2224/16227 , H01L2924/1431 , H01L2924/1434 , H01L2924/15311
摘要： A die-stacked memory device implements an integrated QoS manager to provide centralized QoS functionality in furtherance of one or more specified QoS objectives for the sharing of the memory resources by other components of the processing system. The die-stacked memory device includes a set of one or more stacked memory dies and one or more logic dies. The logic dies implement hardware logic for a memory controller and the QoS manager. The memory controller is coupleable to one or more devices external to the set of one or more stacked memory dies and operates to service memory access requests from the one or more external devices. The QoS manager comprises logic to perform operations in furtherance of one or more QoS objectives, which may be specified by a user, by an operating system, hypervisor, job management software, or other application being executed, or specified via hardcoded logic or firmware.
摘要翻译：堆叠堆叠的存储器件实现集成的QoS管理器以提供集中的QoS功能，以促进一个或多个指定的QoS目标，以便由处理系统的其他组件共享存储器资源。芯片堆叠的存储器件包括一组一个或多个堆叠的存储器管芯和一个或多个逻辑管芯。逻辑模块为存储器控制器和QoS管理器实现硬件逻辑。存储器控制器可耦合到一个或多个堆叠的存储器管芯组的外部的一个或多个器件，并且操作以从一个或多个外部器件服务存储器访问请求。 QoS管理器包括用于执行可由操作系统，管理程序，作业管理软件或正在执行的其它应用程序或通过硬编码逻辑或固件指定的一个或多个QoS目标的操作的逻辑。

7. 发明授权

US09170948B2 Cache coherency using die-stacked memory device with logic die 有权
标题翻译：缓存一致性使用具有逻辑管芯的堆叠式存储器件
公开(公告)号：US09170948B2
公开(公告)日：2015-10-27
申请号：US13726146
申请日：2012-12-23
申请人： Gabriel H. Loh , Bradford M. Beckmann , Lisa R. Hsu , Michael Ignatowski , Michael J. Schulte
发明人： Gabriel H. Loh , Bradford M. Beckmann , Lisa R. Hsu , Michael Ignatowski , Michael J. Schulte
IPC分类号： G06F12/08 , H01L25/18 , G11C5/02 , G11C8/12 , G11C29/12 , H01L25/065
CPC分类号： G06F12/0828 , G11C5/025 , G11C8/12 , G11C29/12 , H01L25/0655 , H01L25/0657 , H01L25/18 , H01L2224/16225 , H01L2225/06541 , H01L2225/06565 , H01L2924/1461 , H01L2924/15311 , Y02D10/13 , H01L2924/00
摘要： A die-stacked memory device implements an integrated coherency manager to offload cache coherency protocol operations for the devices of a processing system. The die-stacked memory device includes a set of one or more stacked memory dies and a set of one or more logic dies. The one or more logic dies implement hardware logic providing a memory interface and the coherency manager. The memory interface operates to perform memory accesses in response to memory access requests from the coherency manager and the one or more external devices. The coherency manager comprises logic to perform coherency operations for shared data stored at the stacked memory dies. Due to the integration of the logic dies and the memory dies, the coherency manager can access shared data stored in the memory dies and perform related coherency operations with higher bandwidth and lower latency and power consumption compared to the external devices.
摘要翻译：堆叠堆叠的存储器件实现集成的一致性管理器以卸载处理系统的设备的高速缓存一致性协议操作。芯片堆叠的存储器件包括一组一个或多个堆叠的存储器管芯和一组一个或多个逻辑管芯。一个或多个逻辑模块实现提供存储器接口和一致性管理器的硬件逻辑。存储器接口操作以响应来自一致性管理器和一个或多个外部设备的存储器访问请求来执行存储器访问。相关性管理器包括对存储在堆叠存储器管芯上的共享数据执行一致性操作的逻辑。由于逻辑管芯和存储器管芯的集成，一致性管理器可以访问存储在存储器管芯中的共享数据，并且与外部器件相比具有更高带宽和更低的延迟和功耗的相关一致性操作。

8. 发明授权

US08879301B2 Method and apparatus for controlling state information retention in an apparatus 有权
标题翻译：用于控制装置中的状态信息保持的方法和装置
公开(公告)号：US08879301B2
公开(公告)日：2014-11-04
申请号：US13616142
申请日：2012-09-14
申请人： David Mayhew , Mark Hummel , Michael Ignatowski
发明人： David Mayhew , Mark Hummel , Michael Ignatowski
IPC分类号： G11C11/00 , G11C13/00 , G11C14/00 , H03K19/00 , G11C11/412 , G11C5/00
CPC分类号： G11C13/0002 , G11C5/005 , G11C11/4125 , G11C14/0045 , H03K19/0016 , H03K19/0019
摘要： A method and apparatus for controlling state information retention determines at least a state information save or restore condition for at least one processing circuit such as one or more CPU or GPU cores or pipelines, in an integrated circuit. In response to determining the state information save or restore condition, the method and apparatus controls either or both of saving or restoring of state information for different virtual machines operating on the processing circuit, into corresponding on-die persistent passive variable resistance memory. The state information save or restore condition is a virtual machine level state information save or restore condition. State information for each of differing virtual machines is saved or restored from differing on-die passive variable resistance memory cells that are assigned on a per-virtual machine basis.
摘要翻译：用于控制状态信息保持的方法和装置至少确定集成电路中至少一个处理电路（例如一个或多个CPU或GPU核心或管线）的状态信息保存或恢复条件。响应于确定状态信息保存或恢复条件，该方法和装置控制将处理电路上运行的不同虚拟机的状态信息的保存或恢复中的任一个或两者转换为相应的裸片上持续的可变电阻存储器。状态信息保存或恢复条件是虚拟机级状态信息保存或恢复条件。每个不同虚拟机的状态信息由在每个虚拟机基础上分配的不同的片上可变电阻存储器单元进行保存或恢复。

9. 发明授权

US08122216B2 Systems and methods for masking latency of memory reorganization work in a compressed memory system 失效
标题翻译：用于屏蔽存储器重组延迟的系统和方法在压缩存储器系统中工作
公开(公告)号：US08122216B2
公开(公告)日：2012-02-21
申请号：US11516207
申请日：2006-09-06
申请人： David Michael Daly , Peter Anthony Franaszek , Michael Ignatowski , Luis Alfonso Lastras-Montano , Michael Raymond Trombley
发明人： David Michael Daly , Peter Anthony Franaszek , Michael Ignatowski , Luis Alfonso Lastras-Montano , Michael Raymond Trombley
IPC分类号： G06F12/00 , G06F13/00 , G06F13/28
CPC分类号： G06F12/08 , G06F12/0804 , G06F12/1408 , G06F2212/401
摘要： Computer memory management systems and methods are provided in which data block buffering and priority scheduling protocols are utilized in compressed memory systems to mask the latency associated with memory reorganization work following access to compressed main memory. In particular, data block buffers and priority scheduling protocols are implemented to delay and prioritize memory reorganization work to allow resources to be used for serving new memory access requests and other high priority commands.
摘要翻译：提供了计算机存储器管理系统和方法，其中在压缩存储器系统中利用数据块缓冲和优先级调度协议来掩盖在访问压缩主存储器之后与存储器重组工作相关联的等待时间。特别地，实现数据块缓冲器和优先级调度协议以延迟和优先化存储器重组工作，以允许资源用于服务新的存储器访问请求和其他高优先级命令。

10. 发明授权

US07099816B2 Method, system and article of manufacture for an analytic modeling technique for handling multiple objectives 有权
公开(公告)号：US07099816B2
公开(公告)日：2006-08-29
申请号：US10174030
申请日：2002-06-17
申请人： Michael Ignatowski , Noshir Cavas Wadia , Peng Ye
发明人： Michael Ignatowski , Noshir Cavas Wadia , Peng Ye
IPC分类号： G06F9/455 , G06F13/00
CPC分类号： G06Q10/04 , G06F11/3419 , G06F11/3447
摘要： The present invention discloses a method, system and article of manufacture for performing analytic modeling on a computer system by handling a plurality of predefined system criteria directed to a modeled computer system. The present invention provides means for the user of an analytic model to specify (i.e. enable) any number of predefined system criteria that must all be simultaneously satisfied. The modeling methodology uses a variation of the well-known Mean Value Analysis technique in its calculations. Response times, resource utilizations, and resource queue lengths are initially estimated for a small user arrival rate. An iterative method is used to gradually increase the user arrival rate by a constant value. For each iteration, response times, resource utilizations, and resource queue lengths are calculated. Then for all the criteria, which have been enabled, it is checked to see if the value limits specified for those criteria have exceeded. If not, the model calculation results are saved and next iteration is started. The model iterations continue with a gradually increasing user arrival rate until one or more of the modeling criteria are exceeded. At that time the model outputs the results from the previous iteration (i.e. the saved results where all the criteria were still satisfied), and the modeling calculations are finished. The model results may be used as input for further processing.

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