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1. 发明申请

US20060237813A1 Junction barrier schottky with low forward drop and improved reverse block voltage 失效
标题翻译：具有低正向下降和改善的反向阻断电压的结型势垒肖特基
公开(公告)号：US20060237813A1
公开(公告)日：2006-10-26
申请号：US11111104
申请日：2005-04-20
申请人： Fuw-Iuan Hshieh , Brian Pratt
发明人： Fuw-Iuan Hshieh , Brian Pratt
IPC分类号： H01L29/47
CPC分类号： H01L29/417 , H01L29/402 , H01L29/66143 , H01L29/8611 , H01L29/872
摘要： This invention discloses a junction barrier Schottky device supported on a substrate that has a first conductivity type. The Schottky device includes a first diffusion region of a fist conductivity type for functioning as a forward barrier height reduction region. The Schottky device further includes a second diffusion region of a second conductivity type disposed immediately adjacent to the first diffusion region for functioning as a backward blocking enhancement region to reduce the backward leakage current.
摘要翻译：本发明公开了一种支撑在具有第一导电类型的基板上的接合势垒肖特基器件。肖特基装置包括第一导电类型的第一扩散区域，用作前势垒高度减小区域。所述肖特基元件还包括与第一扩散区紧邻设置的第二导电类型的第二扩散区，用作反向阻挡增强区以减小反向泄漏电流。

2. 发明授权

US07397102B2 Junction barrier schottky with low forward drop and improved reverse block voltage 失效
标题翻译：具有低正向下降和改善的反向阻断电压的结型势垒肖特基
公开(公告)号：US07397102B2
公开(公告)日：2008-07-08
申请号：US11111104
申请日：2005-04-20
申请人： Fuw-Iuan Hshieh , Brian Pratt
发明人： Fuw-Iuan Hshieh , Brian Pratt
IPC分类号： H01L29/47
CPC分类号： H01L29/417 , H01L29/402 , H01L29/66143 , H01L29/8611 , H01L29/872
摘要： This invention discloses a junction barrier Schottky device supported on a substrate that has a first conductivity type. The Schottky device includes a first diffusion region of a first conductivity type for functioning as a forward barrier height reduction region. The Schottky device further includes a second diffusion region of a second conductivity type disposed immediately adjacent to the first diffusion region for functioning as a backward blocking enhancement region to reduce the backward leakage current.
摘要翻译：本发明公开了一种支撑在具有第一导电类型的基板上的接合势垒肖特基器件。肖特基器件包括第一导电类型的第一扩散区域，用作前势垒高度减小区域。所述肖特基元件还包括与第一扩散区紧邻设置的第二导电类型的第二扩散区，用作反向阻挡增强区，以减小反向泄漏电流。

3. 发明申请

US20060231915A1 Process for high voltage superjunction termination 失效
公开(公告)号：US20060231915A1
公开(公告)日：2006-10-19
申请号：US11318873
申请日：2005-12-27
申请人： Fwu-Iuan Hshieh , Brian Pratt
发明人： Fwu-Iuan Hshieh , Brian Pratt
IPC分类号： H01L23/58
CPC分类号： H01L29/66712 , H01L21/26586 , H01L21/76251 , H01L29/0634 , H01L29/0653 , H01L29/0661 , H01L29/0696 , H01L29/7811 , H01L2924/0002 , H01L2924/00
摘要： A method of manufacturing a semiconductor device having an active region and a termination region includes providing a semiconductor substrate having first and second main surfaces opposite to each other. The semiconductor substrate has an active region and a termination region surrounding the active region. The first main surface is oxidized. A first plurality of trenches and a first plurality of mesas are formed in the termination region. The first plurality of trenches in the termination region are filled with a dielectric material. A second plurality of trenches in the termination region. The second plurality of trenches are with the dielectric material.

4. 发明授权

US08685822B2 Semiconductor component and method of manufacture 有权
标题翻译：半导体元件及制造方法
公开(公告)号：US08685822B2
公开(公告)日：2014-04-01
申请号：US13022628
申请日：2011-02-07
申请人： Peter A. Burke , Duane B. Barber , Brian Pratt
发明人： Peter A. Burke , Duane B. Barber , Brian Pratt
IPC分类号： H01L21/336
CPC分类号： H01L29/66727 , H01L29/407 , H01L29/41766 , H01L29/42376 , H01L29/456 , H01L29/4933 , H01L29/66734 , H01L29/7809 , H01L29/7811 , H01L29/7813
摘要： A semiconductor component that includes gate electrodes and shield electrodes and a method of manufacturing the semiconductor component. A semiconductor material has a device region, a gate contact region, a termination region, and a drain contact region. One or more device trenches is formed in the device region and one or more termination trenches is formed in the edge termination region. Shielding electrodes are formed in portions of the device trenches that are adjacent their floors. A gate dielectric material is formed on the sidewalls of the trenches in the device region and gate electrodes are formed over and electrically isolated from the shielding electrodes. The gate electrodes in the trenches in the device region are connected to the gate electrodes in the trenches in the gate contact region. The shielding electrodes in the trenches in the device region are connected to the shielding electrodes in the termination region.
摘要翻译：包括栅电极和屏蔽电极的半导体部件和制造半导体部件的方法。半导体材料具有器件区域，栅极接触区域，端接区域和漏极接触区域。在器件区域中形成一个或多个器件沟槽，并且在边缘端接区域中形成一个或多个端接沟槽。屏蔽电极形成在与它们的地板相邻的器件沟槽的部分中。在器件区域中的沟槽的侧壁上形成栅极电介质材料，并且在屏蔽电极之间形成栅电极并与屏蔽电极电绝缘。器件区域中的沟槽中的栅电极连接到栅极接触区域中的沟槽中的栅电极。器件区域的沟槽中的屏蔽电极与端接区域中的屏蔽电极相连。

5. 发明授权

US07897462B2 Method of manufacturing semiconductor component with gate and shield electrodes in trenches 有权
标题翻译：在沟槽中制造具有栅极和屏蔽电极的半导体部件的方法
公开(公告)号：US07897462B2
公开(公告)日：2011-03-01
申请号：US12271083
申请日：2008-11-14
申请人： Peter A. Burke , Duane B. Barber , Brian Pratt
发明人： Peter A. Burke , Duane B. Barber , Brian Pratt
IPC分类号： H01L21/336
CPC分类号： H01L29/66727 , H01L29/407 , H01L29/41766 , H01L29/42376 , H01L29/456 , H01L29/4933 , H01L29/66734 , H01L29/7809 , H01L29/7811 , H01L29/7813
摘要： A semiconductor component that includes gate electrodes and shield electrodes and a method of manufacturing the semiconductor component. A semiconductor material has a device region, a gate contact region, a termination region, and a drain contact region. One or more device trenches is formed in the device region and one or more termination trenches is formed in the edge termination region. Shielding electrodes are formed in portions of the device trenches that are adjacent their floors. A gate dielectric material is formed on the sidewalls of the trenches in the device region and gate electrodes are formed over and electrically isolated from the shielding electrodes. The gate electrodes in the trenches in the device region are connected to the gate electrodes in the trenches in the gate contact region. The shielding electrodes in the trenches in the device region are connected to the shielding electrodes in the termination region.
摘要翻译：包括栅电极和屏蔽电极的半导体部件和制造半导体部件的方法。半导体材料具有器件区域，栅极接触区域，端接区域和漏极接触区域。在器件区域中形成一个或多个器件沟槽，并且在边缘端接区域中形成一个或多个端接沟槽。屏蔽电极形成在与它们的地板相邻的器件沟槽的部分中。在器件区域中的沟槽的侧壁上形成栅极电介质材料，并且在屏蔽电极之间形成栅电极并与屏蔽电极电绝缘。器件区域中的沟槽中的栅电极连接到栅极接触区域中的沟槽中的栅电极。器件区域的沟槽中的屏蔽电极与端接区域中的屏蔽电极相连。

6. 发明申请

US20100123192A1 SEMICONDUCTOR COMPONENT AND METHOD OF MANUFACTURE 有权
公开(公告)号：US20100123192A1
公开(公告)日：2010-05-20
申请号：US12271083
申请日：2008-11-14
申请人： Peter A. Burke , Duane B. Barber , Brian Pratt
发明人： Peter A. Burke , Duane B. Barber , Brian Pratt
IPC分类号： H01L29/78 , H01L21/28
CPC分类号： H01L29/66727 , H01L29/407 , H01L29/41766 , H01L29/42376 , H01L29/456 , H01L29/4933 , H01L29/66734 , H01L29/7809 , H01L29/7811 , H01L29/7813
摘要： A semiconductor component that includes gate electrodes and shield electrodes and a method of manufacturing the semiconductor component. A semiconductor material has a device region, a gate contact region, a termination region, and a drain contact region. One or more device trenches is formed in the device region and one or more termination trenches is formed in the edge termination region. Shielding electrodes are formed in portions of the device trenches that are adjacent their floors. A gate dielectric material is formed on the sidewalls of the trenches in the device region and gate electrodes are formed over and electrically isolated from the shielding electrodes. The gate electrodes in the trenches in the device region are connected to the gate electrodes in the trenches in the gate contact region. The shielding electrodes in the trenches in the device region are connected to the shielding electrodes in the termination region.

7. 发明申请

US20100123193A1 SEMICONDUCTOR COMPONENT AND METHOD OF MANUFACTURE 审中-公开
标题翻译：半导体元件及其制造方法
公开(公告)号：US20100123193A1
公开(公告)日：2010-05-20
申请号：US12271092
申请日：2008-11-14
申请人： Peter A. Burke , Duane B. Barber , Brian Pratt
发明人： Peter A. Burke , Duane B. Barber , Brian Pratt
IPC分类号： H01L27/088 , H01L21/28
CPC分类号： H01L27/088 , H01L21/823487
摘要： A semiconductor component that includes gate electrodes and shield electrodes and a method of manufacturing the semiconductor component. A semiconductor material has a device region, a gate contact region, a termination region, and a drain contact region. One or more device trenches is formed in the device region and one or more termination trenches is formed in the edge termination region. Shielding electrodes are formed in portions of the device trenches that are adjacent their floors. A gate dielectric material is formed on the sidewalls of the trenches in the device region and gate electrodes are formed over and electrically isolated from the shielding electrodes. The gate electrodes in the trenches in the device region are connected to the gate electrodes in the trenches in the gate contact region. The shielding electrodes in the trenches in the device region are connected to the shielding electrodes in the termination region.
摘要翻译：包括栅电极和屏蔽电极的半导体部件和制造半导体部件的方法。半导体材料具有器件区域，栅极接触区域，端接区域和漏极接触区域。在器件区域中形成一个或多个器件沟槽，并且在边缘端接区域中形成一个或多个端接沟槽。屏蔽电极形成在与它们的地板相邻的器件沟槽的部分中。在器件区域的沟槽的侧壁上形成栅极电介质材料，并且在屏蔽电极之间形成栅电极并与屏蔽电极电绝缘。器件区域中的沟槽中的栅电极连接到栅极接触区域中的沟槽中的栅电极。器件区域的沟槽中的屏蔽电极与端接区域中的屏蔽电极相连。

8. 发明申请

US20070005254A1 Methods and apparatuses for processing biological data 审中-公开
标题翻译：用于处理生物数据的方法和装置
公开(公告)号：US20070005254A1
公开(公告)日：2007-01-04
申请号：US10574382
申请日：2005-04-02
申请人： Erik Nilsson , Brian Pratt
发明人： Erik Nilsson , Brian Pratt
IPC分类号： G06F19/00
CPC分类号： G01N30/8651 , G01N30/463
摘要： Methods and apparatuses are described to process an n-dimensional data set acquired from a measurement on a biological sample. A method includes dividing an n-dimensional data set into n-dimensional sub-regions, wherein a size of a dimension of an n-dimensional sub-region is less than a size of the dimension of the n-dimensional data set. The n-dimensional sub-regions are stored on a computer readable medium and the computer readable medium is accessible to a data processing system. The n-dimensional data set can exceed an addressable memory limit of the data processing system and mathematical operations are performed on the n-dimensional data set.
摘要翻译：描述了用于处理从生物样品上的测量获取的n维数据集的方法和装置。一种方法包括将n维数据集划分为n维子区域，其中n维子区域的维度的大小小于n维数据集的维度的大小。 n维子区域存储在计算机可读介质上，并且计算机可读介质可被数据处理系统访问。 n维数据集可以超过数据处理系统的可寻址存储器限制，并且对n维数据集执行数学运算。

9. 发明申请

US20060205174A1 Method for Manufacturing a Superjunction Device With Wide Mesas 失效
标题翻译：制造具有宽台面的超级连接装置的方法
公开(公告)号：US20060205174A1
公开(公告)日：2006-09-14
申请号：US11420490
申请日：2006-05-26
申请人： Fwu-Iuan Hshieh , Koon So , Brian Pratt
发明人： Fwu-Iuan Hshieh , Koon So , Brian Pratt
IPC分类号： H01L21/76
CPC分类号： H01L29/7802 , H01L21/26586 , H01L29/0634 , H01L29/0653 , H01L29/66143 , H01L29/66712 , H01L29/66734 , H01L29/7811 , H01L29/7813 , H01L29/872 , H01L2924/0002 , H01L2924/00
摘要： A method of manufacturing a semiconductor device includes providing semiconductor substrate having trenches and mesas. At least one mesa has first and second sidewalls. The method includes angularly implanting a dopant of a second conductivity into the first sidewall, and angularly implanting a dopant of a second conductivity into the second sidewall. The at least one mesa is converted to a pillar by diffusing the dopants into the at least one mesa. The pillar is then converted to a column by angularly implanting a dopant of the first conductivity into a first sidewall of the pillar, and by angularly implanting the dopant of the first conductivity type into a second sidewall of the pillar. The dopants are then diffused into the pillar to provide a P-N junction of the first and second doped regions located along the depth direction of the adjoining trench. Finally, the trenches are filled with an insulating material.
摘要翻译：制造半导体器件的方法包括提供具有沟槽和台面的半导体衬底。至少一个台面具有第一和第二侧壁。该方法包括将第二导电性的掺杂剂角度地注入到第一侧壁中，并将第二导电性的掺杂剂角度地注入第二侧壁。通过将掺杂剂扩散到至少一个台面中，将至少一个台面转变成柱。然后通过将第一导电性的掺杂剂角度地注入到柱的第一侧壁中，并且将第一导电类型的掺杂剂角度地注入到柱的第二侧壁中，将柱转换成列。然后将掺杂剂扩散到柱中以提供沿相邻沟槽的深度方向定位的第一和第二掺杂区的P-N结。最后，沟槽填充绝缘材料。

10. 发明申请

US20110127603A1 SEMICONDUCTOR COMPONENT AND METHOD OF MANUFACTURE 有权
标题翻译：半导体元件及其制造方法
公开(公告)号：US20110127603A1
公开(公告)日：2011-06-02
申请号：US13022628
申请日：2011-02-07
申请人： Peter A. Burke , Duane B. Barber , Brian Pratt
发明人： Peter A. Burke , Duane B. Barber , Brian Pratt
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/66727 , H01L29/407 , H01L29/41766 , H01L29/42376 , H01L29/456 , H01L29/4933 , H01L29/66734 , H01L29/7809 , H01L29/7811 , H01L29/7813
摘要： A semiconductor component that includes gate electrodes and shield electrodes and a method of manufacturing the semiconductor component. A semiconductor material has a device region, a gate contact region, a termination region, and a drain contact region. One or more device trenches is formed in the device region and one or more termination trenches is formed in the edge termination region. Shielding electrodes are formed in portions of the device trenches that are adjacent their floors. A gate dielectric material is formed on the sidewalls of the trenches in the device region and gate electrodes are formed over and electrically isolated from the shielding electrodes. The gate electrodes in the trenches in the device region are connected to the gate electrodes in the trenches in the gate contact region. The shielding electrodes in the trenches in the device region are connected to the shielding electrodes in the termination region.
摘要翻译：包括栅电极和屏蔽电极的半导体部件和制造半导体部件的方法。半导体材料具有器件区域，栅极接触区域，端接区域和漏极接触区域。在器件区域中形成一个或多个器件沟槽，并且在边缘端接区域中形成一个或多个端接沟槽。屏蔽电极形成在与它们的地板相邻的器件沟槽的部分中。在器件区域中的沟槽的侧壁上形成栅极电介质材料，并且在屏蔽电极之间形成栅电极并与屏蔽电极电绝缘。器件区域中的沟槽中的栅电极连接到栅极接触区域中的沟槽中的栅电极。器件区域的沟槽中的屏蔽电极与端接区域中的屏蔽电极相连。

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