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1. 发明申请

US20050012134A1 Nonvolatile memory device driving method, semiconductor storage device, and liquid crystal display device including the semiconductor storage device 有权
标题翻译：非易失性存储器件驱动方法，半导体存储器件和包括半导体存储器件的液晶显示器件
公开(公告)号：US20050012134A1
公开(公告)日：2005-01-20
申请号：US10888693
申请日：2004-07-08
申请人： Fujio Masuoka , Hiroshi Sakuraba , Fumiyoshi Matsuoka , Syounosuke Ueno , Ryusuke Matsuyama , Shinji Horii
发明人： Fujio Masuoka , Hiroshi Sakuraba , Fumiyoshi Matsuoka , Syounosuke Ueno , Ryusuke Matsuyama , Shinji Horii
IPC分类号： G02F1/1343 , G02F1/133 , G09G3/36 , G11C16/02 , G11C16/04 , G11C16/06 , G11C16/12 , G11C16/14 , G11C16/30 , H01L21/8247 , H01L27/10 , H01L27/115 , H01L29/788 , H01L29/792 , H01L21/336 , H01L27/108 , H01L29/76 , H01L29/94 , H01L31/119
CPC分类号： H01L27/11556 , G09G3/3611 , G09G2320/0285 , G11C16/0433 , G11C16/14 , H01L27/115 , H01L29/7881 , H01L29/7887
摘要： A method for driving a nonvolatile memory device including a semiconductor substrate, an island semiconductor layer on the substrate, a memory cell having a control gate and a charge storage layer surrounding a peripheral surface of the island semiconductor layer, a first selection transistor provided between the memory cell and the substrate and having a first selection gate, a source diffusion layer between the substrate and the island semiconductor layer, a drain diffusion layer provided in an opposing end of the island semiconductor layer from the source diffusion layer, and a second selection transistor provided between the memory cell and the drain diffusion layer and having a second selection gate, the method comprising the steps of: applying a negative first voltage to the drain and the first selection gate, applying a positive second voltage to the second selection gate, and applying 0V or a positive third voltage to the source; and applying a positive fourth voltage higher than the second voltage to the control gate of the memory cell for injecting electric charges into the charge storage layer.
摘要翻译：一种用于驱动包括半导体衬底，在衬底上的岛状半导体层，具有控制栅极的存储单元和围绕岛状半导体层的外围表面的电荷存储层的非易失性存储器件的方法，存储单元和基板，并且具有第一选择栅极，在基板和岛状半导体层之间的源极扩散层，设置在岛状半导体层与源极扩散层相对的端部的漏极扩散层，以及第二选择晶体管设置在所述存储单元和所述漏极扩散层之间并具有第二选择栅极，所述方法包括以下步骤：向所述漏极和所述第一选择栅极施加负的第一电压，向所述第二选择栅极施加正的第二电压，以及向源施加0V或正的第三电压; 以及将高于第二电压的正的第四电压施加到用于向电荷存储层注入电荷的存储单元的控制栅极。

2. 发明授权

US07088617B2 Nonvolatile semiconductor storage device, and liquid crystal display device including the same 有权
标题翻译：非易失性半导体存储装置以及包含该非易失性半导体存储装置的液晶显示装置
公开(公告)号：US07088617B2
公开(公告)日：2006-08-08
申请号：US10919777
申请日：2004-08-16
申请人： Fujio Masuoka , Hiroshi Sakuraba , Fumiyoshi Matsuoka , Syounosuke Ueno , Ryusuke Matsuyama , Shinji Horii
发明人： Fujio Masuoka , Hiroshi Sakuraba , Fumiyoshi Matsuoka , Syounosuke Ueno , Ryusuke Matsuyama , Shinji Horii
IPC分类号： G11C16/04
CPC分类号： G11C16/0483
摘要： A nonvolatile semiconductor storage device including: a plurality of memory cell unit groups each comprising one or more NAND nonvolatile memory cell units each comprising at least one memory cell having a control gate, a first selection transistor having a first selection gate, and a second selection transistor having a second selection gate, the memory cell unit groups each further comprising a control gate line connected to the control gate, a first selection gate line connected to the first selection gate, and a second selection gate line connected to the second selection gate; a common control gate line connected commonly to the control gate lines of different ones of the memory cell unit groups; a first common selection gate line connected commonly to the first selection gate lines of different ones of the memory cell unit groups; and a second common selection gate line connected commonly to the second selection gate lines of different ones of the memory cell unit groups; wherein the memory cells in the respective memory cell unit groups are each uniquely selected on the basis of a combination of the common control gate line and the first and second common selection gate lines.
摘要翻译：一种非易失性半导体存储装置，包括：多个存储单元单元组，每个存储单元单元组包括一个或多个NAND非易失性存储单元单元，每个非易失性存储单元单元包括至少一个具有控制栅极的存储单元，晶体管具有第二选择栅极，所述存储单元单元组还包括连接到所述控制栅极的控制栅极线，连接到所述第一选择栅极的第一选择栅极线和连接到所述第二选择栅极的第二选择栅极线; 公共控制栅极线，共同地连接到不同的存储单元单元组的控制栅极线; 第一公共选择栅极线，共同连接到不同的存储单元单元组的第一选择栅极线; 以及第二公共选择栅极线，共同连接到不同的存储单元单元组的第二选择栅极线; 其中各个存储单元单元组中的存储单元是基于公共控制栅极线和第一和第二公共选择栅极线的组合而被唯一地选择的。

3. 发明申请

US20050047209A1 Nonvolatile semiconductor storage device, and liquid crystal display device including the same 有权
标题翻译：非易失性半导体存储装置以及包含该非易失性半导体存储装置的液晶显示装置
公开(公告)号：US20050047209A1
公开(公告)日：2005-03-03
申请号：US10919777
申请日：2004-08-16
申请人： Fujio Masuoka , Hiroshi Sakuraba , Fumiyoshi Matsuoka , Syounosuke Ueno , Ryusuke Matsuyama , Shinji Horii
发明人： Fujio Masuoka , Hiroshi Sakuraba , Fumiyoshi Matsuoka , Syounosuke Ueno , Ryusuke Matsuyama , Shinji Horii
IPC分类号： G02F1/133 , G09G3/20 , G09G3/36 , G11C16/02 , G11C16/04 , G11C16/06 , G11C16/08 , G11C11/34
CPC分类号： G11C16/0483
摘要： A nonvolatile semiconductor storage device including: a plurality of memory cell unit groups each comprising one or more NAND nonvolatile memory cell units each comprising at least one memory cell having a control gate, a first selection transistor having a first selection gate, and a second selection transistor having a second selection gate, the memory cell unit groups each further comprising a control gate line connected to the control gate, a first selection gate line connected to the first selection gate, and a second selection gate line connected to the second selection gate; a common control gate line connected commonly to the control gate lines of different ones of the memory cell unit groups; a first common selection gate line connected commonly to the first selection gate lines of different ones of the memory cell unit groups; and a second common selection gate line connected commonly to the second selection gate lines of different ones of the memory cell unit groups; wherein the memory cells in the respective memory cell unit groups are each uniquely selected on the basis of a combination of the common control gate line and the first and second common selection gate lines.
摘要翻译：一种非易失性半导体存储装置，包括：多个存储单元单元组，每个存储单元单元组包括一个或多个NAND非易失性存储单元单元，每个非易失性存储单元单元包括至少一个具有控制栅极的存储单元，晶体管具有第二选择栅极，所述存储单元单元组还包括连接到所述控制栅极的控制栅极线，连接到所述第一选择栅极的第一选择栅极线和连接到所述第二选择栅极的第二选择栅极线; 公共控制栅极线，共同地连接到不同的存储单元单元组的控制栅极线; 第一公共选择栅极线，共同连接到不同的存储单元单元组的第一选择栅极线; 以及第二公共选择栅极线，共同连接到不同的存储单元单元组的第二选择栅极线; 其中各个存储单元单元组中的存储单元是基于公共控制栅极线和第一和第二公共选择栅极线的组合而被唯一地选择的。

4. 发明授权

US07387935B2 Memory cell unit, nonvolatile semiconductor storage device including memory cell unit, and memory cell array driving method 有权
标题翻译：存储单元单元，包括存储单元单元的非易失性半导体存储器件和存储单元阵列驱动方法
公开(公告)号：US07387935B2
公开(公告)日：2008-06-17
申请号：US10941505
申请日：2004-09-14
申请人： Fujio Masuoka , Hiroshi Sakuraba , Fumiyoshi Matsuoka , Syounosuke Ueno , Ryusuke Matsuyama , Shinji Horii , Takuji Tanigami
发明人： Fujio Masuoka , Hiroshi Sakuraba , Fumiyoshi Matsuoka , Syounosuke Ueno , Ryusuke Matsuyama , Shinji Horii , Takuji Tanigami
IPC分类号： H01L21/336 , G11C16/04
CPC分类号： H01L29/7926 , G11C16/0483 , H01L27/115 , H01L27/11556 , H01L29/7881 , H01L29/792
摘要： A memory cell unit including: a semiconductor substrate having a source diffusion layer in at least a part of a surface thereof; a column-shaped semiconductor layer provided on the semiconductor substrate, and having a drain diffusion layer provided in an uppermost portion thereof and a first low concentration impurity diffusion layer provided in an entire bottom portion thereof; a memory cell arrangement which includes a plurality of memory cells provided in a peripheral wall of the column-shaped semiconductor layer and connected in series perpendicularly to the substrate, the memory cells each having a charge storage layer and a control gate; a second impurity diffusion layer provided at a lower end of the memory cell arrangement; and a selection transistor having a gate electrode provided around the peripheral wall of the column-shaped semiconductor layer and connecting the second impurity diffusion layer and the first impurity diffusion layer; wherein the first impurity diffusion layer extends into a part of a channel region provided in the peripheral wall of the column-shaped semiconductor layer in opposed relation to the gate electrode of the selection transistor.
摘要翻译：一种存储单元，包括：在其表面的至少一部分中具有源极扩散层的半导体衬底; 设置在半导体基板上的柱状半导体层，在其最上部设置有漏极扩散层，在底部设置有第一低浓度杂质扩散层; 存储单元布置，其包括设置在所述列状半导体层的周壁中并且与所述基板垂直串联连接的多个存储单元，所述存储单元各自具有电荷存储层和控制栅极; 设置在所述存储单元布置的下端的第二杂质扩散层; 以及选择晶体管，其具有设置在所述柱状半导体层的周壁周围的栅电极，并且连接所述第二杂质扩散层和所述第一杂质扩散层; 其中所述第一杂质扩散层延伸到与所述选择晶体管的栅电极相对的所述柱状半导体层的周壁中设置的沟道区的一部分。

5. 发明申请

US20050051806A1 Memory cell unit, nonvolatile semiconductor device, and liquid crystal display device including the nonvolatile semiconductor device 审中-公开
标题翻译：存储单元单元，非易失性半导体器件和包括非易失性半导体器件的液晶显示器件
公开(公告)号：US20050051806A1
公开(公告)日：2005-03-10
申请号：US10930229
申请日：2004-08-30
申请人： Fujio Masuoka , Hiroshi Sakuraba , Fumiyoshi Matsuoka , Syounosuke Ueno
发明人： Fujio Masuoka , Hiroshi Sakuraba , Fumiyoshi Matsuoka , Syounosuke Ueno
IPC分类号： G02F1/133 , H01L21/8247 , H01L27/115 , H01L29/768 , H01L29/786 , H01L29/788 , H01L29/792
CPC分类号： H01L27/11556 , H01L27/115
摘要： A memory cell unit including: a semiconductor substrate having a source diffusion layer provided in a surface thereof; a column-shaped semiconductor layer provided on the source diffusion layer and having a drain diffusion layer provided in an uppermost portion thereof; a memory cell arrangement which includes a plurality of memory cells arranged in series with the intervention of a first impurity diffusion layer; a first selection transistor connected to one end of the memory cell arrangement with the intervention of a second impurity diffusion layer and connected to the drain diffusion layer; and a second selection transistor connected to the other end of the memory cell arrangement with the intervention of a third impurity diffusion layer and connected to the source diffusion layer; wherein a distance between the third impurity diffusion layer and the source diffusion layer is greater than a distance between impurity diffusion layers disposed on opposite sides of each of the memory cells, whereby punch-through of the second selection transistor is prevented when a writing prevention voltage is applied between the source diffusion layer and the first impurity diffusion layer.
摘要翻译：一种存储单元，包括：具有设置在其表面中的源极扩散层的半导体衬底; 设置在源极扩散层上并具有设置在其最上部的漏极扩散层的柱状半导体层; 存储单元布置，其包括与第一杂质扩散层的介入串联布置的多个存储单元; 连接到所述存储单元布置的一端的第一选择晶体管，其具有第二杂质扩散层并连接到所述漏极扩散层; 以及第二选择晶体管，其连接到所述存储单元布置的另一端，并具有第三杂质扩散层并连接到所述源极扩散层; 其中所述第三杂质扩散层和所述源极扩散层之间的距离大于设置在每个所述存储单元的相对侧上的杂质扩散层之间的距离，从而当写入防止电压施加在源极扩散层和第一杂质扩散层之间。

6. 发明授权

US07009888B2 Low voltage, island-layer-based nonvolatile semiconductor storage device with floating biased memory cell channel 有权
标题翻译：具有浮置偏置存储单元通道的低电压，基于岛的非易失性半导体存储器件
公开(公告)号：US07009888B2
公开(公告)日：2006-03-07
申请号：US10888693
申请日：2004-07-08
申请人： Fujio Masuoka , Hiroshi Sakuraba , Fumiyoshi Matsuoka , Syounosuke Ueno , Ryusuke Matsuyama , Shinji Horii
发明人： Fujio Masuoka , Hiroshi Sakuraba , Fumiyoshi Matsuoka , Syounosuke Ueno , Ryusuke Matsuyama , Shinji Horii
IPC分类号： G11C16/12
CPC分类号： H01L27/11556 , G09G3/3611 , G09G2320/0285 , G11C16/0433 , G11C16/14 , H01L27/115 , H01L29/7881 , H01L29/7887
摘要： A method for driving a nonvolatile memory device including a semiconductor substrate, an island semiconductor layer on the substrate, a memory cell having a control gate and a charge storage layer surrounding a peripheral surface of the island semiconductor layer, a first selection transistor provided between the memory cell and the substrate and having a first selection gate, a source diffusion layer between the substrate and the island semiconductor layer, a drain diffusion layer provided in an opposing end of the island semiconductor layer from the source diffusion layer, and a second selection transistor provided between the memory cell and the drain diffusion layer and having a second selection gate, the method comprising the steps of: applying a negative first voltage to the drain and the first selection gate, applying a positive second voltage to the second selection gate, and applying 0V or a positive third voltage to the source; and applying a positive fourth voltage higher than the second voltage to the control gate of the memory cell for injecting electric charges into the charge storage layer.
摘要翻译：一种用于驱动包括半导体衬底，在衬底上的岛状半导体层，具有控制栅极的存储单元和围绕岛状半导体层的外围表面的电荷存储层的非易失性存储器件的方法，存储单元和基板，并且具有第一选择栅极，在基板和岛状半导体层之间的源极扩散层，设置在岛状半导体层与源极扩散层相对的端部的漏极扩散层，以及第二选择晶体管设置在所述存储单元和所述漏极扩散层之间并具有第二选择栅极，所述方法包括以下步骤：向所述漏极和所述第一选择栅极施加负的第一电压，向所述第二选择栅极施加正的第二电压，以及向源施加0V或正的第三电压; 以及将高于第二电压的正的第四电压施加到用于向电荷存储层注入电荷的存储单元的控制栅极。

7. 发明申请

US20050063237A1 Memory cell unit, nonvolatile semiconductor storage device including memory cell unit, and memory cell array driving method 有权
标题翻译：存储单元单元，包括存储单元单元的非易失性半导体存储器件和存储单元阵列驱动方法
公开(公告)号：US20050063237A1
公开(公告)日：2005-03-24
申请号：US10941505
申请日：2004-09-14
申请人： Fujio Masuoka , Hiroshi Sakuraba , Fumiyoshi Matsuoka , Syounosuke Ueno , Ryusuke Matsuyama , Shinji Horii , Takuji Tanigami
发明人： Fujio Masuoka , Hiroshi Sakuraba , Fumiyoshi Matsuoka , Syounosuke Ueno , Ryusuke Matsuyama , Shinji Horii , Takuji Tanigami
IPC分类号： G11C16/02 , G11C7/00 , G11C16/04 , H01L21/8247 , H01L27/115 , H01L29/788 , H01L29/792
CPC分类号： H01L29/7926 , G11C16/0483 , H01L27/115 , H01L27/11556 , H01L29/7881 , H01L29/792
摘要： A memory cell unit including: a semiconductor substrate having a source diffusion layer in at least a part of a surface thereof; a column-shaped semiconductor layer provided on the semiconductor substrate, and having a drain diffusion layer provided in an uppermost portion thereof and a first low concentration impurity diffusion layer provided in an entire bottom portion thereof; a memory cell arrangement which includes a plurality of memory cells provided in a peripheral wall of the column-shaped semiconductor layer and connected in series perpendicularly to the substrate, the memory cells each having a charge storage layer and a control gate; a second impurity diffusion layer provided at a lower end of the memory cell arrangement; and a selection transistor having a gate electrode provided around the peripheral wall of the column-shaped semiconductor layer and connecting the second impurity diffusion layer and the first impurity diffusion layer; wherein the first impurity diffusion layer extends into a part of a channel region provided in the peripheral wall of the column-shaped semiconductor layer in opposed relation to the gate electrode of the selection transistor.
摘要翻译：一种存储单元，包括：在其表面的至少一部分中具有源极扩散层的半导体衬底; 设置在半导体基板上的柱状半导体层，在其最上部设置有漏极扩散层，在底部设置有第一低浓度杂质扩散层; 存储单元布置，其包括设置在所述列状半导体层的周壁中且与所述基板垂直串联连接的多个存储单元，所述存储单元各自具有电荷存储层和控制栅极; 设置在所述存储单元布置的下端的第二杂质扩散层; 以及选择晶体管，其具有设置在所述柱状半导体层的周壁周围的栅电极，并且连接所述第二杂质扩散层和所述第一杂质扩散层; 其中所述第一杂质扩散层延伸到与所述选择晶体管的栅电极相对的所述柱状半导体层的周壁中设置的沟道区的一部分。

8. 发明授权

US08901640B2 Semiconductor element and semiconductor device 有权
标题翻译：半导体元件和半导体器件
公开(公告)号：US08901640B2
公开(公告)日：2014-12-02
申请号：US12944310
申请日：2010-11-11
申请人： Fujio Masuoka , Tomohiko Kudo
发明人： Fujio Masuoka , Tomohiko Kudo
IPC分类号： H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113 , H01L31/119 , H01L29/78 , H01L21/8234 , H01L29/06 , H01L29/423 , H01L29/66 , H01L29/786
CPC分类号： H01L29/7827 , H01L21/823431 , H01L29/0657 , H01L29/42356 , H01L29/42364 , H01L29/42372 , H01L29/42392 , H01L29/66666 , H01L29/78642
摘要： The object of the invention is to provide a semiconductor device realizing high-speed operation of surrounding gate transistors (SGTs), which are three-dimensional semiconductors, by increasing the ON current of the SGTs. This object is achieved by a semiconductor element being provided in which a source, a drain and a gate are positioned in layers on a substrate, the semiconductor element being provided with: a silicon column; an insulating body surrounding the side surface of the silicon column; a gate surrounding the insulating body; a source region positioned above or below the silicon column; and a drain region positioned below or above the silicon column; wherein the contact surface of the silicon column with the source region is smaller than the contact surface of the silicon column with the drain region.
摘要翻译：本发明的目的是通过增加SGT的导通电流来提供实现作为三维半导体的周围栅极晶体管（SGT）的高速操作的半导体器件。该目的通过提供一种半导体元件来实现，其中源极，漏极和栅极分层地定位在衬底上，半导体元件设置有硅柱; 围绕所述硅柱的侧表面的绝缘体; 围绕绝缘体的门; 位于硅柱上方或下方的源区; 以及位于硅柱下方或上方的漏极区域; 其中所述硅柱与所述源极区域的接触表面小于所述硅柱与所述漏极区的接触表面。

9. 发明授权

US08772881B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US08772881B2
公开(公告)日：2014-07-08
申请号：US12794088
申请日：2010-06-04
申请人： Fujio Masuoka , Hiroki Nakamura
发明人： Fujio Masuoka , Hiroki Nakamura
IPC分类号： H01L27/11 , H01L27/088
CPC分类号： H01L27/1104 , H01L27/0207 , H01L27/11
摘要： The object to provide a highly-integrated SGT-based SRAM is achieved by forming an SRAM using an inverter which comprises a first island-shaped semiconductor layer, a first gate dielectric film in contact with a periphery of the first island-shaped semiconductor layer, a first gate electrode having one surface in contact with the first gate dielectric film, a second gate dielectric film in contact with another surface of the first gate electrode, a first arc-shaped semiconductor layer in contact with the second gate dielectric film, a first first-conductive-type high-concentration semiconductor layer arranged on a top of the first island-shaped semiconductor layer, a second first-conductive-type high-concentration semiconductor layer arranged underneath the first island-shaped semiconductor layer, a first second-conductive-type high-concentration semiconductor layer arranged on a top of the first arc-shaped semiconductor layer, and a second second-conductive-type high-concentration semiconductor layer arranged underneath the first arc-shaped semiconductor layer.
摘要翻译：提供高度集成的基于SGT的SRAM的目的是通过使用逆变器形成SRAM来实现，该逆变器包括第一岛状半导体层，与第一岛状半导体层的周边接触的第一栅极电介质膜，具有与第一栅极电介质膜接触的一个表面的第一栅极电极，与第一栅电极的另一表面接触的第二栅极电介质膜，与第二栅极电介质膜接触的第一弧形半导体层，第一栅极电极布置在第一岛状半导体层的顶部上的第一导电型高浓度半导体层，布置在第一岛状半导体层下方的第二第一导电型高浓度半导体层，第一导电型高浓度半导体层，第一导电型高浓度半导体层，布置在第一弧形半导体层的顶部上的高浓度半导体层和第二第二导电型高浓度半导体层所述半导体层布置在所述第一弧形半导体层下方。

10. 发明授权

US08564034B2 Solid-state imaging device 有权
标题翻译：固态成像装置
公开(公告)号：US08564034B2
公开(公告)日：2013-10-22
申请号：US13606823
申请日：2012-09-07
申请人： Fujio Masuoka , Nozomu Harada
发明人： Fujio Masuoka , Nozomu Harada
IPC分类号： H01L31/062
CPC分类号： H01L27/14616 , H01L27/14614
摘要： In a solid-state imaging device, a pixel has a first island-shaped semiconductor (P11) formed on a substrate (1) and a drive output circuit has second island-shaped semiconductors (4a to 4c) formed on the substrate at the same height as that of the first island-shaped semiconductor (P11). The first island-shaped semiconductor (P11) has a first gate insulating layer (6b) formed on an outer periphery thereof and a first gate conductor layer (105a) surrounding the first gate insulating layer (6b). The second island-shaped semiconductors (4a to 4c) have a second gate insulating layer (6a) formed on an outer periphery thereof and a second gate conductor layer (7a) surrounding the second gate insulating layer (6a). The first gate conductor layer (105a) and the second gate conductor layer (7a) have bottom portions located on the same plane.
摘要翻译：在固态成像装置中，像素具有形成在基板（1）上的第一岛状半导体（P11），驱动输出电路具有形成在基板上的第二岛状半导体（4a〜4c）高度为第一岛状半导体（P11）的高度。第一岛状半导体（P11）具有形成在其外周上的第一栅极绝缘层（6b）和围绕第一栅极绝缘层（6b）的第一栅极导体层（105a）。第二岛状半导体（4a〜4c）具有在其外周形成的第二栅极绝缘层（6a）和围绕第二栅极绝缘层（6a）的第二栅极导体层（7a）。第一栅极导体层（105a）和第二栅极导体层（7a）具有位于同一平面上的底部。

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