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    • 3. 发明授权
    • Musical scale generating circuit
    • 音阶发生电路
    • US4699518A
    • 1987-10-13
    • US906758
    • 1986-09-11
    • Tohru Tanabe
    • Tohru Tanabe
    • G04G13/02G10H1/26G10H5/06G04B21/02G10H1/00
    • G10H5/06G04G13/021G10H1/26G10H2230/351
    • A musical scale generating circuit comprises an oscillator, a programmable frequency divider for frequency-dividing an output signal from the oscillator, a tone generating circuit for generating a tone, and a frequency dividing ratio data output circuit for successively outputting frequency dividing ratio data determinative of a plurality of frequency dividing ratios of the programmable frequency divider. A frequency dividing ratio discriminating circuit detects whether a frequency dividing ratio necessary for outputting a desired scale frequency is an odd or even number. A frequency dividing ratio correcting circuit is operative to add one to or substract one from frequency dividing ratio data, when a frequency dividing ratio is detected to be an odd numbered frequency dividing ratio and applies corrected frequency dividing ratio to the programmable frequency divider. A one-half frequency divider further divides a signal from the programmable frequency divider by two.
    • 一种音阶发生电路,包括振荡器,用于对来自振荡器的输出信号进行分频的可编程分频器,用于产生音调的乐音产生电路,以及用于连续地输出分频比数据的分频比数据输出电路, 可编程分频器的多个分频比。 分频比判别电路检测输出期望的比例频率所需的分频比是奇数还是偶数。 当分频比被检测为奇数分频比并且将校正的分频比应用于可编程分频器时,分频比校正电路用于从分频比数据中加1或减1。 一个1/2分频器进一步将来自可编程分频器的信号分为两个。
    • 4. 发明授权
    • Electronic timepiece
    • 电子钟表
    • US4712926A
    • 1987-12-15
    • US878411
    • 1986-06-25
    • Tohru Tanabe
    • Tohru Tanabe
    • G04C3/00G04G13/00G04G13/02G04C21/16
    • G04G13/021G04C3/005G04G13/00
    • An electronic timepiece which produces a time tone based on a time code signal from a time code disk, comprising a control circuit for generating read-in signals in response to a start signal produced on the hour, memory circuit means for storing a time code signal from said time code disk in response to said read-in signals, wherein a stored code signal of said memory circuit means is supplied to a clock strike count control circuit as a signal for limiting the number of time tone strikes. Further, first and second memory circuit means are provided for storing the time code successively, and an AM/PM discriminating circuit is also provided for discriminating AM and PM by receiving said stored time codes of said first and second memory circuit means.
    • 一种电子表,其基于来自时间码盘的时间码信号产生时间色调,包括响应于在该小时产生的开始信号产生读入信号的控制电路,存储电路装置,用于存储时间码信号 响应于所述读入信号从所述时间码盘中提取所述存储电路装置的存储码信号作为用于限制时间戳打击次数的信号提供给时钟打击计数控制电路。 此外,提供第一和第二存储器电路装置用于连续地存储时间码,并且还提供AM / PM鉴别电路,用于通过接收所述第一和第二存储器电路装置的所存储的时间码来识别AM和PM。