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1. 发明申请

US20110047425A1 On-Chip Logic To Log Failures During Production Testing And Enable Debugging For Failure Diagnosis 有权
标题翻译：片上逻辑在生产测试期间记录故障并启用故障诊断调试
公开(公告)号：US20110047425A1
公开(公告)日：2011-02-24
申请号：US12629036
申请日：2009-12-01
申请人： Friedrich Hapke , Juergen Schloeffel , Michael Wittke , Rene Krenz-Baath
发明人： Friedrich Hapke , Juergen Schloeffel , Michael Wittke , Rene Krenz-Baath
IPC分类号： G01R31/3177 , G06F11/25
CPC分类号： G01R31/318335
摘要： On-chip logic includes a shadow register cross-coupled with a multiple input shift/signature register (MISR). The shadow register facilitates debugging by shifting out a test signature while resetting the MISR with a fault-free signature. The on-chip logic may further include comparator circuitry to produce an output signal by comparing the test signature with the fault-free signature or by first compressing the test signature and then comparing the compressed test signature with the compressed fault-free signature.
摘要翻译：片上逻辑包括与多输入移位/签名寄存器（MISR）交叉耦合的影子寄存器。影子寄存器通过移除测试签名便于调试，同时以无故障签名重置MISR。片上逻辑还可以包括比较器电路，用于通过将测试签名与无故障签名进行比较来产生输出信号，或者通过首先压缩测试签名，然后将压缩的测试签名与压缩的无故障签名进行比较。

2. 发明授权

US08423845B2 On-chip logic to log failures during production testing and enable debugging for failure diagnosis 有权
标题翻译：在生产测试期间记录故障的片上逻辑，并启用故障诊断调试
公开(公告)号：US08423845B2
公开(公告)日：2013-04-16
申请号：US12629036
申请日：2009-12-01
申请人： Friedrich Hapke , Juergen Schloeffel , Michael Wittke , Rene Krenz-Baath
发明人： Friedrich Hapke , Juergen Schloeffel , Michael Wittke , Rene Krenz-Baath
IPC分类号： G01R31/28
CPC分类号： G01R31/318335
摘要： On-chip logic includes a shadow register cross-coupled with a multiple input shift/signature register (MISR). The shadow register facilitates debugging by shifting out a test signature while resetting the MISR with a fault-free signature. The on-chip logic may further include comparator circuitry to produce an output signal by comparing the test signature with the fault-free signature or by first compressing the test signature and then comparing the compressed test signature with the compressed fault-free signature.
摘要翻译：片上逻辑包括与多输入移位/签名寄存器（MISR）交叉耦合的影子寄存器。影子寄存器通过移除测试签名便于调试，同时以无故障签名重置MISR。片上逻辑还可以包括比较器电路，用于通过将测试签名与无故障签名进行比较来产生输出信号，或者通过首先压缩测试签名，然后将压缩的测试签名与压缩的无故障签名进行比较。

3. 发明申请

US20100229061A1 Cell-Aware Fault Model Creation And Pattern Generation 审中-公开
标题翻译：细胞感知故障模型创建和模式生成
公开(公告)号：US20100229061A1
公开(公告)日：2010-09-09
申请号：US12718799
申请日：2010-03-05
申请人： Friedrich HAPKE , Rene Krenz-Baath , Andreas Glowatz , Juergen Schloeffel , Peter Weseloh , Michael Wittke , Mark A. Kassab , Christopher W. Schuermyer
发明人： Friedrich HAPKE , Rene Krenz-Baath , Andreas Glowatz , Juergen Schloeffel , Peter Weseloh , Michael Wittke , Mark A. Kassab , Christopher W. Schuermyer
IPC分类号： G01R31/3177 , G06F11/25
CPC分类号： G01R31/318342
摘要： Cell-aware fault models directly address layout-based intra-cell defects. They are created by performing analog simulations on the transistor-level netlist of a library cell and then by library view synthesis. The cell-aware fault models may be used to generate cell-aware test patterns, which usually have higher defect coverage than those generated by conventional ATPG techniques. The cell-aware fault models may also be used to improve defect coverage of a set of test patterns generated by conventional ATPG techniques.
摘要翻译：单元感知故障模型直接针对基于布局的小区内缺陷。它们是通过对库单元的晶体管级网表执行模拟仿真，然后通过库视图合成来创建的。细胞感知故障模型可用于产生细胞感知测试模式，其通常具有比常规ATPG技术产生的缺陷覆盖更高的缺陷覆盖。细胞感知故障模型还可以用于改进由常规ATPG技术产生的一组测试模式的缺陷覆盖。

4. 发明授权

US08250420B2 Testable integrated circuit and test data generation method 有权
标题翻译：可测试的集成电路和测试数据生成方法
公开(公告)号：US08250420B2
公开(公告)日：2012-08-21
申请号：US12594594
申请日：2008-04-03
申请人： Friedrich Hapke , Michael Wittke , Juergen Schloeffel
发明人： Friedrich Hapke , Michael Wittke , Juergen Schloeffel
IPC分类号： G01R31/28
CPC分类号： G01R31/31919
摘要： An integrated circuit (IC) is disclosed that comprises a circuit portion (100) having a plurality of inputs (102) and a plurality of outputs (106), the plurality of inputs being arranged to receive a test pattern in a test mode of the integrated circuit, the test pattern comprising a plurality of test vectors for feeding to the plurality of inputs in successive clock cycles. The IC also comprises a test arrangement for testing the circuit portion (100), comprising a test pattern generator (110) for generating the test pattern, masking logic (150) for masking selected outputs of the plurality of outputs (106) and a signal generator (130) coupled to the masking logic (150) for generating a masking signal triggering the masking of all of said circuit portion outputs during selected cycles of the successive clock cycles, the signal generator (130) being responsive to clock cycle selection data (s1-st). This way, selected clock cycles or individual flip-flops can be masked out without requiring external control signals. The IC may also comprise a mask storage arrangement (115) for storing masks to mask a plurality of scan chains for all cycles within a pattern.
摘要翻译：公开了一种集成电路（IC），其包括具有多个输入（102）和多个输出（106）的电路部分（100），所述多个输入被布置成在测试模式中接收测试图案集成电路，测试图案包括用于在连续时钟周期内馈送到多个输入的多个测试向量。 IC还包括用于测试电路部分（100）的测试装置，包括用于产生测试图案的测试图案发生器（110），用于屏蔽多个输出（106）的选定输出的屏蔽逻辑（150）发生器（130），其耦合到所述屏蔽逻辑（150），用于在所述连续时钟周期的选定周期期间产生触发所有所述电路部分输出的屏蔽的屏蔽信号，所述信号发生器（130）响应于时钟周期选择数据 s1-st）。这样，选择的时钟周期或单个触发器可以被屏蔽，而不需要外部控制信号。 IC还可以包括掩模存储装置（115），用于存储掩模以掩模图案内的所有周期的多个扫描链。

5. 发明申请

US20100117658A1 TESTABLE INTEGRATED CIRCUIT AND TEST DATA GENERATION METHOD 有权
标题翻译：可测试的集成电路和测试数据生成方法
公开(公告)号：US20100117658A1
公开(公告)日：2010-05-13
申请号：US12594594
申请日：2008-04-03
申请人： Friedrich Hapke , Michael Wittke , Juergen Schloeffel
发明人： Friedrich Hapke , Michael Wittke , Juergen Schloeffel
IPC分类号： G01R31/02
CPC分类号： G01R31/31919
摘要： An integrated circuit (IC) is disclosed that comprises a circuit portion (100) having a plurality of inputs (102) and a plurality of outputs (106), the plurality of inputs being arranged to receive a test pattern in a test mode of the integrated circuit, the test pattern comprising a plurality of test vectors for feeding to the plurality of inputs in successive clock cycles. The IC also comprises a test arrangement for testing the circuit portion (100), comprising a test pattern generator (110) for generating the test pattern, masking logic (150) for masking selected outputs of the plurality of outputs (106) and a signal generator (130) coupled to the masking logic (150) for generating a masking signal triggering the masking of all of said circuit portion outputs during selected cycles of the successive clock cycles, the signal generator (130) being responsive to clock cycle selection data (s1-st). This way, selected clock cycles or individual flip-flops can be masked out without requiring external control signals. The IC may also comprise a mask storage arrangement (115) for storing masks to mask a plurality of scan chains for all cycles within a pattern.
摘要翻译：公开了一种集成电路（IC），其包括具有多个输入（102）和多个输出（106）的电路部分（100），所述多个输入被布置成在测试模式中接收测试图案集成电路，测试图案包括用于在连续时钟周期内馈送到多个输入的多个测试向量。 IC还包括用于测试电路部分（100）的测试装置，包括用于产生测试图案的测试图案发生器（110），用于屏蔽多个输出（106）的选定输出的屏蔽逻辑（150）发生器（130），其耦合到所述屏蔽逻辑（150），用于在所述连续时钟周期的选定周期期间产生触发所有所述电路部分输出的屏蔽的屏蔽信号，所述信号发生器（130）响应于时钟周期选择数据 s1-st）。这样，选择的时钟周期或单个触发器可以被屏蔽，而不需要外部控制信号。 IC还可以包括掩模存储装置（115），用于存储掩模以掩模图案内的所有周期的多个扫描链。

6. 发明授权

US08448008B2 High speed clock control 有权
标题翻译：高速时钟控制
公开(公告)号：US08448008B2
公开(公告)日：2013-05-21
申请号：US12749093
申请日：2010-03-29
申请人： Friedrich Hapke , Michael Wittke , Sascha Ochsenknecht , Thomas H. Rinderknecht
发明人： Friedrich Hapke , Michael Wittke , Sascha Ochsenknecht , Thomas H. Rinderknecht
IPC分类号： G06F1/00 , G06F1/04 , G01D3/00
CPC分类号： G01R31/318552
摘要： On-chip high speed clock control techniques for testing circuits with multiple clock systems are disclosed. The techniques allow certain (e.g. compatible) high speed clocks to be activated with predefined waveforms during a capture period of a logic test, based on a clock control signal. The clock control signal may be supplied via a JTAG control port or via a scan chain load port. The clock control signal may also be generated by a BIST controller. The techniques may ensure glitch-free transitions from slow speed clocks during a shift period to fast speed clocks during a capture period.
摘要翻译：公开了用于具有多个时钟系统的测试电路的片上高速时钟控制技术。这些技术允许基于时钟控制信号在逻辑测试的捕获周期期间用预定波形激活某些（例如，兼容的）高速时钟。时钟控制信号可以经由JTAG控制端口或经由扫描链装载端口提供。时钟控制信号也可以由BIST控制器产生。这些技术可以确保在转换周期期间从慢速时钟到捕获周期期间快速转换时钟的无故障转换。

7. 发明授权

US08103925B2 On-chip logic to support compressed X-masking for BIST 失效
标题翻译：片上逻辑支持BIST的压缩X-masking
公开(公告)号：US08103925B2
公开(公告)日：2012-01-24
申请号：US12625487
申请日：2009-11-24
申请人： Friedrich Hapke , Michael Wittke , Reinhard Meier
发明人： Friedrich Hapke , Michael Wittke , Reinhard Meier
IPC分类号： G01R31/28
CPC分类号： G01R31/318547 , G06F11/27 , G11C2029/3202
摘要： Techniques are provided for X-masking using at least some masking information provided by on-chip logic, in lieu of masking information provided from off of the integrated circuit being tested. The masking information is provided by a masking information source on the integrated circuit being tested, such as, for example, a read-only memory (ROM) circuit, that feeds the masking information to the X-masking logic. With these implementations of the invention, it is possible to perform X-masking independent from any external data, thus enabling X-masking for a logic built-in self-test without requiring an external testing device.
摘要翻译：使用由片上逻辑提供的至少一些掩蔽信息来提供用于X掩蔽的技术，以代替从正被测试的集成电路提供的屏蔽信息。屏蔽信息由正在测试的集成电路上的掩蔽信息源（例如，将只有读取存储器（ROM）电路）提供给X掩蔽逻辑的掩蔽信息提供。利用本发明的这些实施方式，可以独立于任何外部数据进行X-掩蔽，从而可以在不需要外部测试装置的情况下实现逻辑内置自检的X掩蔽。

8. 发明申请

US20080195907A1 Circuit Arrangement and Method of Testing an Application Circuit Provided in Said Circuit Arrangement 有权
标题翻译：电路布置和测试在所述电路布置中提供的应用电路的方法
公开(公告)号：US20080195907A1
公开(公告)日：2008-08-14
申请号：US11631402
申请日：2005-06-27
申请人： Michael Wittke , Friedrich Hapke
发明人： Michael Wittke , Friedrich Hapke
IPC分类号： G01R31/3177 , G06F11/25
CPC分类号： G01R31/3187
摘要： The object being to develop an integrated circuit arrangement (100) with at least one application circuit (40) to be tested, and with at least one self-test circuit (10, 20, 32, 34, 36, 50) provided for testing the application circuit (40) and generating at least one pseudo-random test sample, wherein said pseudo-random test sample can be converted into at least one test vector that is programmable and/or deterministic and that can be supplied to the application circuit (40) for testing purposes via at least one logic gate (32, 34, 36) and by means of at least one signal that can be applied to said logic gate (32, 34, 36), and wherein the output signal arising in dependence on the deterministic test vector can be evaluated by the application circuit (40) by means of at least one signature register (50), as well as a method of testing the application circuit (40) present in the integrated circuit arrangement (100) by means of the self-test circuit (10, 20, 32, 34, 36, 50) further such that the B[uild-]I[n]S[elf-]T[est] hardware connected to the additional deterministic logic can be reduced, it is suggested that the signal to be supplied to the logic gate (32, 34, 36) can be made available by a B[it]F[lipping]F[unction] logic circuit (10) based on at least one
摘要翻译：目的是开发具有待测试的至少一个应用电路（40）的集成电路装置（100），以及提供用于测试的至少一个自测电路（10,20,32,34,36,50）所述应用电路（40）并且生成至少一个伪随机测试样本，其中所述伪随机测试样本可以被转换成至少一个可编程和/或确定性的测试向量，并且可被提供给应用电路 40），用于通过至少一个逻辑门（32,34,36）进行测试，并借助于可施加到所述逻辑门（32,34,36）的至少一个信号，并且其中依赖于所述逻辑门可以通过至少一个签名寄存器（50）由应用电路（40）对确定性测试向量进行评估，以及通过以下方式测试集成电路装置（100）中存在的应用电路（40）的方法：自检电路的装置（10,20,32,34,3 6，50），使得连接到附加确定性逻辑的B [uild-] I [n] S [elf-] T [est]硬件可以被减少，建议提供给逻辑门的信号（32,34,36）可以由B [it] F [lipping] F [逻辑]逻辑电路（10）基于至少一个

9. 发明授权

US08112686B2 Deterministic logic built-in self-test stimuli generation 失效
标题翻译：确定性逻辑内置自检刺激生成
公开(公告)号：US08112686B2
公开(公告)日：2012-02-07
申请号：US12629038
申请日：2009-12-01
申请人： Friedrich Hapke , Michael Wittke , Reinhard Meier
发明人： Friedrich Hapke , Michael Wittke , Reinhard Meier
IPC分类号： G01R31/28
CPC分类号： G01R31/318558 , G01R31/318597
摘要： Techniques for storing and using compressed restrict values for selected scan chains and flip-flops, such that the states that need to be applied to those flip flops need not be solved by a linear equation system solver, such as a linear equation system solver provided by an automatic test pattern generation (ATPG) tool. Selected restrict values can then be injected into test patterns for those flip-flop combinations that need to be set in a certain shift cycle or those flip-flops that need to be initialized one after another (e.g., for serial settings in one scan chain).
摘要翻译：用于存储和使用所选择的扫描链和触发器的压缩限制值的技术，使得需要应用于这些触发器的状态不需要通过线性方程系统求解器来解决，例如由自动测试模式生成（ATPG）工具。然后，可以将选定的限制值注入到需要在特定移位周期中设置的那些触发器组合的测试模式中，或者需要一个接一个地初始化的触发器（例如，用于一个扫描链中的串行设置）。

10. 发明授权

US07870453B2 Circuit arrangement and method of testing an application circuit provided in said circuit arrangement 有权
标题翻译：电路装置和测试在所述电路装置中提供的应用电路的方法
公开(公告)号：US07870453B2
公开(公告)日：2011-01-11
申请号：US11631402
申请日：2005-06-27
申请人： Michael Wittke , Friedrich Hapke
发明人： Michael Wittke , Friedrich Hapke
IPC分类号： G01R31/28
CPC分类号： G01R31/3187
摘要： According to an example embodiment, there is an integrated circuit arrangement with at least one application circuit to be tested, and with at least one self-test circuit for testing the application circuit and generating at least one pseudo-random test sample. wherein said The pseudo-random test sample is converted into at least one test vector that is programmable and/or deterministic and is supplied to the application circuit for testing purposes via at least one logic gate and at least one signal that is applied to said logic gate. The output signal arising in dependence on the deterministic test vector is evaluated by the application circuit by at least one signature register. Furthermore, there is a method of testing the application circuit such that Built In Self Test (BIST) hardware connected to the additional deterministic logic is reduced; it is suggested that the signal supplied to the logic gate is made available by a Bit Flipping Function (BFF) logic circuit based on at least one self-test circuit.
摘要翻译：根据示例性实施例，存在具有要测试的至少一个应用电路的集成电路布置，并且具有用于测试应用电路并生成至少一个伪随机测试样本的至少一个自检电路。其中所述伪随机测试样本被转换成至少一个可编程和/或确定的测试向量，并经由至少一个逻辑门和施加到所述逻辑的至少一个信号被提供给应用电路以用于测试目的门。根据确定性测试向量产生的输出信号由应用电路由至少一个签名寄存器进行评估。此外，存在测试应用电路的方法，使得连接到附加确定性逻辑的内置自测（BIST）硬件被减少; 建议基于至少一个自检电路的提供给逻辑门的信号由位翻转功能（BFF）逻辑电路提供。

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