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1. 发明申请

US20100229061A1 Cell-Aware Fault Model Creation And Pattern Generation 审中-公开
标题翻译：细胞感知故障模型创建和模式生成
公开(公告)号：US20100229061A1
公开(公告)日：2010-09-09
申请号：US12718799
申请日：2010-03-05
申请人： Friedrich HAPKE , Rene Krenz-Baath , Andreas Glowatz , Juergen Schloeffel , Peter Weseloh , Michael Wittke , Mark A. Kassab , Christopher W. Schuermyer
发明人： Friedrich HAPKE , Rene Krenz-Baath , Andreas Glowatz , Juergen Schloeffel , Peter Weseloh , Michael Wittke , Mark A. Kassab , Christopher W. Schuermyer
IPC分类号： G01R31/3177 , G06F11/25
CPC分类号： G01R31/318342
摘要： Cell-aware fault models directly address layout-based intra-cell defects. They are created by performing analog simulations on the transistor-level netlist of a library cell and then by library view synthesis. The cell-aware fault models may be used to generate cell-aware test patterns, which usually have higher defect coverage than those generated by conventional ATPG techniques. The cell-aware fault models may also be used to improve defect coverage of a set of test patterns generated by conventional ATPG techniques.
摘要翻译：单元感知故障模型直接针对基于布局的小区内缺陷。它们是通过对库单元的晶体管级网表执行模拟仿真，然后通过库视图合成来创建的。细胞感知故障模型可用于产生细胞感知测试模式，其通常具有比常规ATPG技术产生的缺陷覆盖更高的缺陷覆盖。细胞感知故障模型还可以用于改进由常规ATPG技术产生的一组测试模式的缺陷覆盖。

2. 发明申请

US20110047425A1 On-Chip Logic To Log Failures During Production Testing And Enable Debugging For Failure Diagnosis 有权
标题翻译：片上逻辑在生产测试期间记录故障并启用故障诊断调试
公开(公告)号：US20110047425A1
公开(公告)日：2011-02-24
申请号：US12629036
申请日：2009-12-01
申请人： Friedrich Hapke , Juergen Schloeffel , Michael Wittke , Rene Krenz-Baath
发明人： Friedrich Hapke , Juergen Schloeffel , Michael Wittke , Rene Krenz-Baath
IPC分类号： G01R31/3177 , G06F11/25
CPC分类号： G01R31/318335
摘要： On-chip logic includes a shadow register cross-coupled with a multiple input shift/signature register (MISR). The shadow register facilitates debugging by shifting out a test signature while resetting the MISR with a fault-free signature. The on-chip logic may further include comparator circuitry to produce an output signal by comparing the test signature with the fault-free signature or by first compressing the test signature and then comparing the compressed test signature with the compressed fault-free signature.
摘要翻译：片上逻辑包括与多输入移位/签名寄存器（MISR）交叉耦合的影子寄存器。影子寄存器通过移除测试签名便于调试，同时以无故障签名重置MISR。片上逻辑还可以包括比较器电路，用于通过将测试签名与无故障签名进行比较来产生输出信号，或者通过首先压缩测试签名，然后将压缩的测试签名与压缩的无故障签名进行比较。

3. 发明授权

US08423845B2 On-chip logic to log failures during production testing and enable debugging for failure diagnosis 有权
标题翻译：在生产测试期间记录故障的片上逻辑，并启用故障诊断调试
公开(公告)号：US08423845B2
公开(公告)日：2013-04-16
申请号：US12629036
申请日：2009-12-01
申请人： Friedrich Hapke , Juergen Schloeffel , Michael Wittke , Rene Krenz-Baath
发明人： Friedrich Hapke , Juergen Schloeffel , Michael Wittke , Rene Krenz-Baath
IPC分类号： G01R31/28
CPC分类号： G01R31/318335
摘要： On-chip logic includes a shadow register cross-coupled with a multiple input shift/signature register (MISR). The shadow register facilitates debugging by shifting out a test signature while resetting the MISR with a fault-free signature. The on-chip logic may further include comparator circuitry to produce an output signal by comparing the test signature with the fault-free signature or by first compressing the test signature and then comparing the compressed test signature with the compressed fault-free signature.
摘要翻译：片上逻辑包括与多输入移位/签名寄存器（MISR）交叉耦合的影子寄存器。影子寄存器通过移除测试签名便于调试，同时以无故障签名重置MISR。片上逻辑还可以包括比较器电路，用于通过将测试签名与无故障签名进行比较来产生输出信号，或者通过首先压缩测试签名，然后将压缩的测试签名与压缩的无故障签名进行比较。

4. 发明申请

US20130054161A1 Cell-Aware Fault Model Generation For Delay Faults 有权
标题翻译：用于延迟故障的小区故障模型生成
公开(公告)号：US20130054161A1
公开(公告)日：2013-02-28
申请号：US13219564
申请日：2011-08-26
申请人： Friedrich Hapke , Wilfried Redemund , Juergen Schloeffel , Andreas Glowatz
发明人： Friedrich Hapke , Wilfried Redemund , Juergen Schloeffel , Andreas Glowatz
IPC分类号： G06F19/00 , G01R31/3163
CPC分类号： G01R31/31835 , G06F17/5036
摘要： Cell-aware fault models for delay faults are created for library cells. Analog one-clock-cycle fault simulations are first performed on a transistor-level netlist of a cell to identify type one detectable defects and type two detectable defects in defects of interest. The type one detectable defects are detectable by one-clock-cycle testing and their fault models may be created based on results of the analog one-clock-cycle fault simulations. The type two detectable defects are defects for which two-cycle detection conditions may be calculated from corresponding results of the analog one-cycle fault simulations. Analog two-clock-cycle fault simulations are then performed for the rest defects in the defects of interest to determine type three detectable defects and their detection conditions. The created cell-aware fault models may be used to generate cell-aware test patterns.
摘要翻译：为库单元创建延迟故障的单元感知故障模型。模拟一时钟周期故障模拟首先在单元的晶体管级网表上执行，以识别一个可检测的缺陷并在感兴趣的缺陷中键入两个可检测的缺陷。通过一时钟周期测试可以检测到一种可检测的缺陷，并且可以基于模拟一时钟周期故障模拟的结果创建它们的故障模型。类型2可检测缺陷是可以从模拟一周期故障模拟的相应结果计算出两周期检测条件的缺陷。然后对感兴趣的缺陷中的其余缺陷进行模拟二时钟周期故障模拟，以确定三种可检测的缺陷及其检测条件。创建的小区感知故障模型可用于生成小区感知测试模式。

5. 发明授权

US08990760B2 Cell-aware fault model generation for delay faults 有权
标题翻译：延迟故障的单元感知故障模型生成
公开(公告)号：US08990760B2
公开(公告)日：2015-03-24
申请号：US13219564
申请日：2011-08-26
申请人： Friedrich Hapke , Wilfried Redemund , Juergen Schloeffel , Andreas Glowatz
发明人： Friedrich Hapke , Wilfried Redemund , Juergen Schloeffel , Andreas Glowatz
IPC分类号： G06F17/50 , G01R31/3183
CPC分类号： G01R31/31835 , G06F17/5036
摘要： Cell-aware fault models for delay faults are created for library cells. Analog one-clock-cycle fault simulations are first performed on a transistor-level netlist of a cell to identify type one detectable defects and type two detectable defects in defects of interest. The type one detectable defects are detectable by one-clock-cycle testing and their fault models may be created based on results of the analog one-clock-cycle fault simulations. The type two detectable defects are defects for which two-cycle detection conditions may be calculated from corresponding results of the analog one-cycle fault simulations. Analog two-clock-cycle fault simulations are then performed for the rest defects in the defects of interest to determine type three detectable defects and their detection conditions. The created cell-aware fault models may be used to generate cell-aware test patterns.
摘要翻译：为库单元创建延迟故障的单元感知故障模型。模拟一时钟周期故障模拟首先在单元的晶体管级网表上执行，以识别一个可检测的缺陷并在感兴趣的缺陷中键入两个可检测的缺陷。通过一时钟周期测试可以检测到一种可检测的缺陷，并且可以基于模拟一时钟周期故障模拟的结果创建它们的故障模型。类型2可检测缺陷是可以从模拟一周期故障模拟的相应结果计算出两周期检测条件的缺陷。然后对感兴趣的缺陷中的其余缺陷进行模拟二时钟周期故障模拟，以确定三种可检测的缺陷及其检测条件。创建的小区感知故障模型可用于生成小区感知测试模式。

6. 发明授权

US08250420B2 Testable integrated circuit and test data generation method 有权
标题翻译：可测试的集成电路和测试数据生成方法
公开(公告)号：US08250420B2
公开(公告)日：2012-08-21
申请号：US12594594
申请日：2008-04-03
申请人： Friedrich Hapke , Michael Wittke , Juergen Schloeffel
发明人： Friedrich Hapke , Michael Wittke , Juergen Schloeffel
IPC分类号： G01R31/28
CPC分类号： G01R31/31919
摘要： An integrated circuit (IC) is disclosed that comprises a circuit portion (100) having a plurality of inputs (102) and a plurality of outputs (106), the plurality of inputs being arranged to receive a test pattern in a test mode of the integrated circuit, the test pattern comprising a plurality of test vectors for feeding to the plurality of inputs in successive clock cycles. The IC also comprises a test arrangement for testing the circuit portion (100), comprising a test pattern generator (110) for generating the test pattern, masking logic (150) for masking selected outputs of the plurality of outputs (106) and a signal generator (130) coupled to the masking logic (150) for generating a masking signal triggering the masking of all of said circuit portion outputs during selected cycles of the successive clock cycles, the signal generator (130) being responsive to clock cycle selection data (s1-st). This way, selected clock cycles or individual flip-flops can be masked out without requiring external control signals. The IC may also comprise a mask storage arrangement (115) for storing masks to mask a plurality of scan chains for all cycles within a pattern.
摘要翻译：公开了一种集成电路（IC），其包括具有多个输入（102）和多个输出（106）的电路部分（100），所述多个输入被布置成在测试模式中接收测试图案集成电路，测试图案包括用于在连续时钟周期内馈送到多个输入的多个测试向量。 IC还包括用于测试电路部分（100）的测试装置，包括用于产生测试图案的测试图案发生器（110），用于屏蔽多个输出（106）的选定输出的屏蔽逻辑（150）发生器（130），其耦合到所述屏蔽逻辑（150），用于在所述连续时钟周期的选定周期期间产生触发所有所述电路部分输出的屏蔽的屏蔽信号，所述信号发生器（130）响应于时钟周期选择数据 s1-st）。这样，选择的时钟周期或单个触发器可以被屏蔽，而不需要外部控制信号。 IC还可以包括掩模存储装置（115），用于存储掩模以掩模图案内的所有周期的多个扫描链。

7. 发明申请

US20100117658A1 TESTABLE INTEGRATED CIRCUIT AND TEST DATA GENERATION METHOD 有权
标题翻译：可测试的集成电路和测试数据生成方法
公开(公告)号：US20100117658A1
公开(公告)日：2010-05-13
申请号：US12594594
申请日：2008-04-03
申请人： Friedrich Hapke , Michael Wittke , Juergen Schloeffel
发明人： Friedrich Hapke , Michael Wittke , Juergen Schloeffel
IPC分类号： G01R31/02
CPC分类号： G01R31/31919
摘要： An integrated circuit (IC) is disclosed that comprises a circuit portion (100) having a plurality of inputs (102) and a plurality of outputs (106), the plurality of inputs being arranged to receive a test pattern in a test mode of the integrated circuit, the test pattern comprising a plurality of test vectors for feeding to the plurality of inputs in successive clock cycles. The IC also comprises a test arrangement for testing the circuit portion (100), comprising a test pattern generator (110) for generating the test pattern, masking logic (150) for masking selected outputs of the plurality of outputs (106) and a signal generator (130) coupled to the masking logic (150) for generating a masking signal triggering the masking of all of said circuit portion outputs during selected cycles of the successive clock cycles, the signal generator (130) being responsive to clock cycle selection data (s1-st). This way, selected clock cycles or individual flip-flops can be masked out without requiring external control signals. The IC may also comprise a mask storage arrangement (115) for storing masks to mask a plurality of scan chains for all cycles within a pattern.
摘要翻译：公开了一种集成电路（IC），其包括具有多个输入（102）和多个输出（106）的电路部分（100），所述多个输入被布置成在测试模式中接收测试图案集成电路，测试图案包括用于在连续时钟周期内馈送到多个输入的多个测试向量。 IC还包括用于测试电路部分（100）的测试装置，包括用于产生测试图案的测试图案发生器（110），用于屏蔽多个输出（106）的选定输出的屏蔽逻辑（150）发生器（130），其耦合到所述屏蔽逻辑（150），用于在所述连续时钟周期的选定周期期间产生触发所有所述电路部分输出的屏蔽的屏蔽信号，所述信号发生器（130）响应于时钟周期选择数据 s1-st）。这样，选择的时钟周期或单个触发器可以被屏蔽，而不需要外部控制信号。 IC还可以包括掩模存储装置（115），用于存储掩模以掩模图案内的所有周期的多个扫描链。

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