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1. 发明授权

US08321761B1 ECC bits used as additional register file storage 有权
公开(公告)号：US08321761B1
公开(公告)日：2012-11-27
申请号：US12568552
申请日：2009-09-28
申请人： Fred Gruner , Xiaogang Qiu , Yan Yan Tang
发明人： Fred Gruner , Xiaogang Qiu , Yan Yan Tang
IPC分类号： G11C29/00
CPC分类号： G09G5/363 , G06F11/10 , G09G2330/12 , G09G2360/121 , G09G2360/125 , G11C2029/0411
摘要： A memory module includes a plurality of register files. Each register file is associated with a set of error-correcting code (ECC) bits and ECC check/correct logic that can provide error-correcting functionality, if required. When error-correcting functionality is not required, ECC bits are grouped together to form additional register files, thereby providing additional storage space.

2. 发明授权

US08533435B2 Reordering operands assigned to each one of read request ports concurrently accessing multibank register file to avoid bank conflict 有权
标题翻译：对分配给每个读取请求端口的操作数重新排序并发访问多银行寄存器文件以避免银行冲突
公开(公告)号：US08533435B2
公开(公告)日：2013-09-10
申请号：US12875843
申请日：2010-09-03
申请人： Xiaogang Qiu , Ming Y. Siu , Yan Yan Tang , John Erik Lindholm , Michael C. Shebanow , Stuart F. Oberman
发明人： Xiaogang Qiu , Ming Y. Siu , Yan Yan Tang , John Erik Lindholm , Michael C. Shebanow , Stuart F. Oberman
IPC分类号： G06F9/34
CPC分类号： G06F9/3012 , G06F9/30098 , G06F9/3824 , G06F9/3851 , G06F9/3885 , G06F9/3887 , G06F9/3889
摘要： One embodiment of the present invention sets forth a technique for collecting operands specified by an instruction. As a sequence of instructions is received the operands specified by the instructions are assigned to ports, so that each one of the operands specified by a single instruction is assigned to a different port. Reading of the operands from a multi-bank register file is scheduled by selecting an operand from each one of the different ports to produce an operand read request and ensuring that two or more of the selected operands are not stored in the same bank of the multi-bank register file. The operands specified by the operand read request are read from the multi-bank register file in a single clock cycle. Each instruction is then executed as the operands specified by the instruction are read from the multi-bank register file and collected over one or more clock cycles.
摘要翻译：本发明的一个实施例提出了一种用于收集由指令指定的操作数的技术。由于接收到指令序列，指令指定的操作数被分配给端口，以便将由单个指令指定的每个操作数分配给不同的端口。通过从不同端口中的每一个选择一个操作数来调度来自多存储器寄存器文件的操作数，以产生操作数读取请求，并确保所选择的操作数中的两个或更多个不存储在多个存储区的同一个存储区中银行寄存器文件。由操作数读取请求指定的操作数在单个时钟周期内从多存储体寄存器文件读取。然后由指令指定的操作数从多存储寄存器文件中读取并在一个或多个时钟周期内采集，执行每条指令。

3. 发明申请

US20110072243A1 Unified Collector Structure for Multi-Bank Register File 有权
标题翻译：多银行登记册统一采集器结构
公开(公告)号：US20110072243A1
公开(公告)日：2011-03-24
申请号：US12875843
申请日：2010-09-03
申请人： Xiaogang Qiu , Ming Y. Siu , Yan Yan Tang , John Erik Lindholm , Michael C. Shebanow , Stuart F. Oberman
发明人： Xiaogang Qiu , Ming Y. Siu , Yan Yan Tang , John Erik Lindholm , Michael C. Shebanow , Stuart F. Oberman
IPC分类号： G06F9/30
CPC分类号： G06F9/3012 , G06F9/30098 , G06F9/3824 , G06F9/3851 , G06F9/3885 , G06F9/3887 , G06F9/3889
摘要： One embodiment of the present invention sets forth a technique for collecting operands specified by an instruction. As a sequence of instructions is received the operands specified by the instructions are assigned to ports, so that each one of the operands specified by a single instruction is assigned to a different port. Reading of the operands from a multi-bank register file is scheduled by selecting an operand from each one of the different ports to produce an operand read request and ensuring that two or more of the selected operands are not stored in the same bank of the multi-bank register file. The operands specified by the operand read request are read from the multi-bank register file in a single clock cycle. Each instruction is then executed as the operands specified by the instruction are read from the multi-bank register file and collected over one or more clock cycles.
摘要翻译：本发明的一个实施例提出了一种用于收集由指令指定的操作数的技术。由于接收到指令序列，指令指定的操作数被分配给端口，以便将由单个指令指定的每个操作数分配给不同的端口。通过从不同端口中的每一个选择一个操作数来调度来自多存储器寄存器文件的操作数，以产生操作数读取请求，并确保所选择的操作数中的两个或更多个不存储在多个存储区的同一个存储区中银行寄存器文件。由操作数读取请求指定的操作数在单个时钟周期内从多存储体寄存器文件读取。然后由指令指定的操作数从多存储寄存器文件中读取并在一个或多个时钟周期内采集，执行每条指令。

4. 发明授权

US08134570B1 System and method for graphics attribute packing for pixel shader usage 有权
标题翻译：用于像素着色器使用的图形属性打包的系统和方法
公开(公告)号：US08134570B1
公开(公告)日：2012-03-13
申请号：US11532779
申请日：2006-09-18
申请人： Jerome F. Duluk, Jr. , Andrew J. Tao , Roger L. Allen , Svetoslav D. Tzvetkov , Yan Yan Tang , Elena M. Ing
发明人： Jerome F. Duluk, Jr. , Andrew J. Tao , Roger L. Allen , Svetoslav D. Tzvetkov , Yan Yan Tang , Elena M. Ing
IPC分类号： G09G5/00
CPC分类号： G06T15/005
摘要： A system, method and computer program product are provided for packing graphics attributes. In use, a plurality of graphics attributes is identified. Such graphics attributes are packed, such that the packed graphics attributes are capable of being processed utilizing a pixel shader.
摘要翻译：提供了用于打包图形属性的系统，方法和计算机程序产品。在使用中，识别出多个图形属性。打包这样的图形属性，使得打包的图形属性能够利用像素着色器进行处理。

5. 发明申请

US20110078689A1 Address Mapping for a Parallel Thread Processor 有权
标题翻译：并行线程处理器的地址映射
公开(公告)号：US20110078689A1
公开(公告)日：2011-03-31
申请号：US12890518
申请日：2010-09-24
申请人： Michael C. SHEBANOW , Yan Yan Tang , John R. Nickolls
发明人： Michael C. SHEBANOW , Yan Yan Tang , John R. Nickolls
IPC分类号： G06F9/46
CPC分类号： G06F12/0284 , G06F9/3851 , G06F12/0607
摘要： A method for thread address mapping in a parallel thread processor. The method includes receiving a thread address associated with a first thread in a thread group; computing an effective address based on a location of the thread address within a local window of a thread address space; computing a thread group address in an address space associated with the thread group based on the effective address and a thread identifier associated with a first thread; and computing a virtual address associated with the first thread based on the thread group address and a thread group identifier, where the virtual address is used to access a location in a memory associated with the thread address to load or store data.
摘要翻译：一种并行线程处理器中线程地址映射的方法。该方法包括接收与线程组中的第一线程相关联的线程地址; 基于线程地址在线程地址空间的本地窗口内的位置来计算有效地址; 基于有效地址和与第一线程相关联的线程标识符计算与线程组相关联的地址空间中的线程组地址; 以及基于所述线程组地址和线程组标识符计算与所述第一线程相关联的虚拟地址，其中所述虚拟地址用于访问与所述线程地址相关联的存储器中的位置以加载或存储数据。

6. 发明授权

US06831653B2 Graphics pixel packing for improved fill rate performance 有权
标题翻译：图形像素包装，提高填充率性能
公开(公告)号：US06831653B2
公开(公告)日：2004-12-14
申请号：US09919551
申请日：2001-07-31
申请人： David Kehlet , Nandini Ramani , Yan Yan Tang , Roger W. Swanson
发明人： David Kehlet , Nandini Ramani , Yan Yan Tang , Roger W. Swanson
IPC分类号： G09G536
CPC分类号： G06T1/60
摘要： A system and method for packing pixels together to provide a increased fill rate in a frame buffer hardware in the graphics system. The graphics system may be configured to receive and rasterize graphics data at a faster cycle rate than the system's frame buffer memory fill rate. The output from the rasterization hardware may be stored in a FIFO memory that is configured to selectively shift pixels in order to improve fill rate performance. The FIFO memory may be configured to ensure that the pixels meet certain criteria in order to prevent page faults and interleave conflicts that could reduce the fill rate. The FIFO memory may also be configured to remove empty cycles that occur as a result of the pixel packing.
摘要翻译：一种用于将像素打包在一起以在图形系统中的帧缓冲器硬件中提供增加的填充率的系统和方法。图形系统可以被配置为以比系统的帧缓冲存储器填充速率更快的周期速率接收和光栅化图形数据。光栅化硬件的输出可以存储在FIFO存储器中，FIFO存储器被配置为选择性地移位像素以便提高填充率性能。 FIFO存储器可以被配置为确保像素满足特定标准，以便防止可能降低填充率的页错误和交错冲突。 FIFO存储器还可以被配置为去除由于像素打包而发生的空循环。

7. 发明授权

US06927775B2 Parallel box filtering through reuse of existing circular filter 有权
标题翻译：通过重复使用现有的圆形滤波器并行框过滤
公开(公告)号：US06927775B2
公开(公告)日：2005-08-09
申请号：US10377924
申请日：2003-03-03
申请人： Michael W. Schimpf , Yan Yan Tang
发明人： Michael W. Schimpf , Yan Yan Tang
IPC分类号： G06T15/00 , G06T15/50 , G06F15/16
CPC分类号： G06T15/503 , G06T15/005
摘要： A sample filtering system and method for concurrently filtering sample data for two or more sequential pixels (in a scan-line) are disclosed. The system may include a sample cache, a control register, a read cache controller, and a sample-to-pixel calculation unit. The read cache controller reads a first set of S samples from the sample cache, and outputs a second set of S samples to the sample-to-pixel calculation unit. The second set of samples may have one or more subsets of samples, with each subset of samples selected to cover the filter region for one of the sequential pixels. The sample-to-pixel calculation unit may process each subset separately and concurrently.
摘要翻译：公开了用于同时过滤两个或更多个顺序像素（扫描线）的采样数据的采样滤波系统和方法。系统可以包括采样高速缓存，控制寄存器，读高速缓存控制器和采样到像素计算单元。读取高速缓存控制器从采样高速缓存读取第一组S采样，并将第二组S采样输出到采样到像素的计算单元。第二组样本可以具有一个或多个样本子集，其中每个样本子集被选择以覆盖顺序像素之一的滤波器区域。样本到像素计算单元可以分别地并发地处理每个子集。

8. 发明授权

US06914609B2 Multiple scan line sample filtering 有权
标题翻译：多扫描线样本滤波
公开(公告)号：US06914609B2
公开(公告)日：2005-07-05
申请号：US10085636
申请日：2002-02-28
申请人： Yan Yan Tang , Wayne Eric Burk , Philip C. Leung
发明人： Yan Yan Tang , Wayne Eric Burk , Philip C. Leung
IPC分类号： G09G5/36
CPC分类号： G09G5/363
摘要： A system and method for generating pixels for a display device. The system may include a sample buffer for storing a plurality samples in a memory, a sample cache for caching recently accessed samples, and a sample filter unit for filtering one or more samples to generate a pixel. The generated pixels may then be stored in a frame buffer or provided to a display device. The method operates to take advantage of the common samples shared by neighboring pixels in both the x and y directions for reduced sample buffer accesses and improved performance. The method involves reading samples from the memory that correspond to pixels in a plurality of neighboring scan lines, and possibly also to multiple pixels in each of these scan lines. The samples may be stored in a cache memory and then accessed from the cache memory for filtering. The method maximizes use of the common samples shared by neighboring pixels in both the x and y directions.
摘要翻译：一种用于生成显示装置的像素的系统和方法。系统可以包括用于将多个样本存储在存储器中的样本缓冲器，用于缓存最近访问的样本的样本缓存器，以及用于对一个或多个样本进行过滤以生成像素的样本滤波器单元。所产生的像素然后可以存储在帧缓冲器中或提供给显示设备。该方法操作以利用x和y方向上的相邻像素共享的公共样本，以减少采样缓冲器访问和改进的性能。该方法涉及从存储器中读取与多个相邻扫描线中的像素相对应的样本，并且还可能读取这些扫描线中的每一个中的多个像素。样本可以存储在高速缓冲存储器中，然后从高速缓存存储器进行过滤。该方法最大限度地利用x和y方向上相邻像素共享的公共样本。

9. 发明授权

US06895458B2 Opcode to turn around a bi-directional bus 有权
标题翻译：操作代码转向双向总线
公开(公告)号：US06895458B2
公开(公告)日：2005-05-17
申请号：US10090491
申请日：2002-03-04
申请人： Ewa M. Kubalska , Lisa Grenier , Yan Yan Tang , Elena M. Ing
发明人： Ewa M. Kubalska , Lisa Grenier , Yan Yan Tang , Elena M. Ing
IPC分类号： G06F13/36 , G06T15/00 , G09G5/36 , G06F13/00
CPC分类号： G09G5/363 , G06F13/36 , G06T15/005
摘要： A system for managing the control of a bi-directional data bus between a master unit and a slave unit. The master couples to the slave through a request opcode bus, a reply opcode bus and the data bus. If the master is in a bus driving state (with respect to the data bus) and receives a read request, the master relinquishes bus control and sends a read request through the request opcode bus. The slave unit assumes bus control and sends the requested data through the data bus. If the master is in a bus sensing state and receives a write request, the master sends a last read opcode to the slave via the request opcode bus, and waits for the slave to return a special token through the reply opcode bus. Upon receiving the special token the master unit assumes bus control and performs the write transaction.
摘要翻译：一种用于管理主单元和从单元之间的双向数据总线的控制的系统。主机通过请求操作码总线，应答操作码总线和数据总线耦合到从机。如果主机处于总线驱动状态（相对于数据总线）并接收到读取请求，则主机放弃总线控制并通过请求操作码总线发送读取请求。从单元假设总线控制，并通过数据总线发送所请求的数据。如果主机处于总线感测状态并接收写请求，则主机通过请求操作码总线向从机发送最后一个读操作码，并等待从机通过应答操作码总线返回特殊令牌。在接收到特殊令牌时，主单元承担总线控制并执行写入事务。

10. 发明授权

US06812929B2 System and method for prefetching data from a frame buffer 有权
标题翻译：从帧缓冲区预取数据的系统和方法
公开(公告)号：US06812929B2
公开(公告)日：2004-11-02
申请号：US10094957
申请日：2002-03-11
申请人： Michael G. Lavelle , Ewa M. Kubalska , Yan Yan Tang
发明人： Michael G. Lavelle , Ewa M. Kubalska , Yan Yan Tang
IPC分类号： G06F1318
CPC分类号： G09G5/39 , G09G5/363 , G09G2360/121
摘要： A graphics system may include a frame buffer that includes several sets of one or more memory banks and a cache. The frame buffer may load data from one of the memory banks into the cache in response to receiving a cache fill request. Each set of memory banks is accessible independently of each other set of memory banks. A frame buffer interface coupled to the frame buffer includes a plurality of cache fill request queues. Each cache fill request queue is configured to store one or more cache fill requests targeting a corresponding one of the sets of memory banks. The frame buffer interface is configured to select a cache fill request from one of the cache fill request queues that stores cache fill requests targeting a set of memory banks that is not currently being accessed and to provide the selected cache fill request to the frame buffer.
摘要翻译：图形系统可以包括帧缓冲器，其包括若干组一个或多个存储器组和高速缓存。响应于接收到高速缓存填充请求，帧缓冲器可以将数据从一个存储体加载到高速缓存中。每组存储体可以独立于彼此的存储体组来访问。耦合到帧缓冲器的帧缓冲器接口包括多个高速缓存填充请求队列。每个高速缓存填充请求队列被配置为存储一个或多个缓存填充请求，其针对存储器组的相应组之一。帧缓冲器接口被配置为从缓存填充请求队列中的一个选择高速缓存填充请求，所述缓存填充请求队列存储针对当前未被访问的一组存储器组的高速缓存填充请求，并且向帧缓冲器提供所选择的高速缓存填充请求。

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