专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

US20070072380A1 Methods for fabrication of a stressed MOS device 有权
标题翻译：制造应力MOS器件的方法
公开(公告)号：US20070072380A1
公开(公告)日：2007-03-29
申请号：US11235791
申请日：2005-09-26
申请人： Frank Wirbeleit , Linda Black , Igor Peidous
发明人： Frank Wirbeleit , Linda Black , Igor Peidous
IPC分类号： H01L21/336 , H01L21/3205 , H01L21/4763
CPC分类号： H01L27/1203 , H01L21/823807 , H01L21/823814 , H01L21/823878 , H01L21/84 , H01L29/0649 , H01L29/1037 , H01L29/66636 , H01L29/66772 , H01L29/7848 , H01L29/7849 , H01L29/78654
摘要： Methods for fabricating a stressed MOS device is provided. One method comprises the steps of providing a monocrystalline semiconductor substrate having a surface and a channel abutting the surface. A gate electrode having a first edge and a second edge is formed overlying the monocrystalline semiconductor substrate. The substrate is anisotropically etched to form a first recess aligned with the first edge and a second recess aligned with the second edge. The substrate is further isotropically etched to form a third recess in the substrate extending beneath the channel. The third recess is filled with an expanding material to exert an upward force on the channel and the first and second recesses are filled with a contact material. Conductivity determining ions are implanted into the contact material to form a source region and a drain region aligned with the first and second edges, respectively.
摘要翻译：提供制造应力MOS器件的方法。一种方法包括提供具有表面和邻接表面的通道的单晶半导体衬底的步骤。具有第一边缘和第二边缘的栅电极形成在单晶半导体衬底上。基板被各向异性蚀刻以形成与第一边缘对准的第一凹部和与第二边缘对准的第二凹部。衬底被进一步各向同性蚀刻以在通道下延伸的衬底中形成第三凹槽。第三凹部填充有膨胀材料以在通道上施加向上的力，并且第一和第二凹部填充有接触材料。电导率确定离子被注入到接触材料中以分别形成与第一和第二边缘对准的源极区域和漏极区域。

2. 发明授权

US07410859B1 Stressed MOS device and method for its fabrication 有权
标题翻译：强调MOS器件及其制造方法
公开(公告)号：US07410859B1
公开(公告)日：2008-08-12
申请号：US11269241
申请日：2005-11-07
申请人： Igor Peidous , Linda R. Black , Frank Wirbeleit
发明人： Igor Peidous , Linda R. Black , Frank Wirbeleit
IPC分类号： H01L21/8238 , H01L21/336
CPC分类号： H01L29/66636 , H01L21/823807 , H01L21/823814 , H01L21/84 , H01L29/1054 , H01L29/165 , H01L29/6656 , H01L29/66772 , H01L29/7848 , H01L29/78654
摘要： A stressed MOS device and a method for its fabrication are provided. The MOS device comprises a substrate having a surface, the substrate comprising a monocrystalline semiconductor material having a first lattice constant. A channel region is formed of the monocrystalline silicon material adjacent the surface. A stress inducing monocrystalline semiconductor material having a second lattice constant greater than the first lattice constant is grown under the channel region to exert a horizontal tensile stress on the channel region.
摘要翻译：提供了一种强调的MOS器件及其制造方法。 MOS器件包括具有表面的衬底，该衬底包括具有第一晶格常数的单晶半导体材料。沟道区域由邻近表面的单晶硅材料形成。在沟道区域下生长具有大于第一晶格常数的第二晶格常数的应力诱导单晶半导体材料，以在沟道区域上施加水平拉伸应力。

3. 发明授权

US07326601B2 Methods for fabrication of a stressed MOS device 有权
标题翻译：制造应力MOS器件的方法
公开(公告)号：US07326601B2
公开(公告)日：2008-02-05
申请号：US11235791
申请日：2005-09-26
申请人： Frank Wirbeleit , Linda R. Black , Igor Peidous
发明人： Frank Wirbeleit , Linda R. Black , Igor Peidous
IPC分类号： H01L21/84
CPC分类号： H01L27/1203 , H01L21/823807 , H01L21/823814 , H01L21/823878 , H01L21/84 , H01L29/0649 , H01L29/1037 , H01L29/66636 , H01L29/66772 , H01L29/7848 , H01L29/7849 , H01L29/78654
摘要： Methods for fabricating a stressed MOS device is provided. One method comprises the steps of providing a monocrystalline semiconductor substrate having a surface and a channel abutting the surface. A gate electrode having a first edge and a second edge is formed overlying the monocrystalline semiconductor substrate. The substrate is anisotropically etched to form a first recess aligned with the first edge and a second recess aligned with the second edge. The substrate is further isotropically etched to form a third recess in the substrate extending beneath the channel. The third recess is filled with an expanding material to exert an upward force on the channel and the first and second recesses are filled with a contact material. Conductivity determining ions are implanted into the contact material to form a source region and a drain region aligned with the first and second edges, respectively.
摘要翻译：提供制造应力MOS器件的方法。一种方法包括提供具有表面和邻接表面的通道的单晶半导体衬底的步骤。具有第一边缘和第二边缘的栅电极形成在单晶半导体衬底上。基板被各向异性蚀刻以形成与第一边缘对准的第一凹部和与第二边缘对准的第二凹部。衬底被进一步各向同性蚀刻以在通道下延伸的衬底中形成第三凹槽。第三凹部填充有膨胀材料以在通道上施加向上的力，并且第一和第二凹部填充有接触材料。电导率确定离子被注入到接触材料中以分别形成与第一和第二边缘对准的源极区域和漏极区域。

4. 发明授权

US07696534B2 Stressed MOS device 有权
标题翻译：强调MOS器件
公开(公告)号：US07696534B2
公开(公告)日：2010-04-13
申请号：US12166166
申请日：2008-07-01
申请人： Igor Peidous , Linda R. Black , Frank Wirbeleit
发明人： Igor Peidous , Linda R. Black , Frank Wirbeleit
IPC分类号： H01L29/74
CPC分类号： H01L29/66636 , H01L21/823807 , H01L21/823814 , H01L21/84 , H01L29/1054 , H01L29/165 , H01L29/6656 , H01L29/66772 , H01L29/7848 , H01L29/78654
摘要： A stressed MOS device is provided that includes a silicon substrate, a gate electrode and an epitaxial layer of stress inducing monocrystalline semiconductor material. The silicon substrate is characterized by a monocrystalline silicon lattice constant. The gate electrode overlies a silicon channel region at the surface of the silicon substrate. The epitaxial layer of stress inducing monocrystalline semiconductor material is grown in the silicon substrate. The epitaxial layer of stress inducing monocrystalline semiconductor material has a lattice constant greater than the monocrystalline silicon lattice constant, and extends under the silicon channel region.
摘要翻译：提供了一种应力MOS器件，其包括硅衬底，栅电极和应力诱导单晶半导体材料的外延层。硅衬底的特征在于单晶硅晶格常数。栅电极覆盖在硅衬底的表面处的硅沟道区域。在硅衬底中生长应力诱导单晶半导体材料的外延层。应力诱导单晶半导体材料的外延层具有大于单晶硅晶格常数的晶格常数，并且在硅沟道区下延伸。

5. 发明授权

US07494918B2 Semiconductor structures including multiple crystallographic orientations and methods for fabrication thereof 失效
标题翻译：包括多个晶体取向的半导体结构及其制造方法
公开(公告)号：US07494918B2
公开(公告)日：2009-02-24
申请号：US11538963
申请日：2006-10-05
申请人： Byeong Y. Kim , Xiaomeng Chen , Judson R. Holt , Christopher D. Sheraw , Linda Black , Igor Peidous
发明人： Byeong Y. Kim , Xiaomeng Chen , Judson R. Holt , Christopher D. Sheraw , Linda Black , Igor Peidous
IPC分类号： H01L21/4763 , H01L29/04
CPC分类号： H01L29/045 , H01L21/823807 , H01L21/823878 , H01L21/84 , H01L27/1203
摘要： Semiconductor structures and methods for fabrication thereof are predicated upon epitaxial growth of an epitaxial surface semiconductor layer upon a semiconductor substrate having a first crystallographic orientation. The semiconductor substrate is exposed within an aperture within a semiconductor-on-insulator structure. The epitaxial surface semiconductor layer alternatively contacts or is isolated from a surface semiconductor layer having a second crystallographic orientation within the semiconductor-on-insulator structure. A recess of the semiconductor surface layer with respect to a buried dielectric layer thereunder and a hard mask layer thereover provides for inhibited second crystallographic phase growth within the epitaxial surface semiconductor layer.
摘要翻译：半导体结构及其制造方法基于外延表面半导体层在具有第一晶体取向的半导体衬底上外延生长。半导体衬底暴露在绝缘体内半导体结构内的孔内。外延表面半导体层与绝缘体半导体结构内的具有第二结晶取向的表面半导体层交替接触或隔离。半导体表面层相对于其下方的掩埋介电层的凹部和其上的硬掩模层提供了外延表面半导体层内的抑制的第二结晶相生长。

6. 发明申请

US20080083952A1 SEMICONDUCTOR STRUCTURES INCLUDING MULTIPLE CRYSTALLOGRAPHIC ORIENTATIONS AND METHODS FOR FABRICATION THEREOF 失效
标题翻译：包括多个晶体学方位的半导体结构及其制造方法
公开(公告)号：US20080083952A1
公开(公告)日：2008-04-10
申请号：US11538963
申请日：2006-10-05
申请人： Byeong Y. Kim , Xiaomeng Chen , Judson R. Holt , Christopher D. Sheraw , Linda Black , Igor Peidous
发明人： Byeong Y. Kim , Xiaomeng Chen , Judson R. Holt , Christopher D. Sheraw , Linda Black , Igor Peidous
IPC分类号： H01L27/12 , H01L21/84
CPC分类号： H01L29/045 , H01L21/823807 , H01L21/823878 , H01L21/84 , H01L27/1203
摘要： Semiconductor structures and methods for fabrication thereof are predicated upon epitaxial growth of an epitaxial surface semiconductor layer upon a semiconductor substrate having a first crystallographic orientation. The semiconductor substrate is exposed within an aperture within a semiconductor-on-insulator structure. The epitaxial surface semiconductor layer alternatively contacts or is isolated from a surface semiconductor layer having a second crystallographic orientation within the semiconductor-on-insulator structure. A recess of the semiconductor surface layer with respect to a buried dielectric layer thereunder and a hard mask layer thereover provides for inhibited second crystallographic phase growth within the epitaxial surface semiconductor layer.
摘要翻译：半导体结构及其制造方法基于外延表面半导体层在具有第一晶体取向的半导体衬底上外延生长。半导体衬底暴露在绝缘体内半导体结构内的孔内。外延表面半导体层与绝缘体半导体结构内的具有第二结晶取向的表面半导体层交替接触或隔离。半导体表面层相对于其下方的掩埋介电层的凹部和其上的硬掩模层提供了外延表面半导体层内的抑制的第二结晶相生长。

7. 发明授权

US07767540B2 Transistor having a channel with tensile strain and oriented along a crystallographic orientation with increased charge carrier mobility 有权
标题翻译：晶体管具有具有拉伸应变的通道并沿着具有增加的电荷载流子迁移率的晶体取向定向
公开(公告)号：US07767540B2
公开(公告)日：2010-08-03
申请号：US11567268
申请日：2006-12-06
申请人： Igor Peidous , Thorsten Kammler , Andy Wei
发明人： Igor Peidous , Thorsten Kammler , Andy Wei
IPC分类号： H01L21/76
CPC分类号： H01L29/7843 , H01L21/26506 , H01L29/51 , H01L29/665 , H01L29/6656 , H01L29/6659 , H01L29/7833 , H01L29/7848
摘要： By appropriately orienting the channel length direction with respect to the crystallographic characteristics of the silicon layer, the stress-inducing effects of strained silicon/carbon material may be significantly enhanced compared to conventional techniques. In one illustrative embodiment, the channel may be oriented along the direction for a (100) surface orientation, thereby providing an electron mobility increase of approximately a factor of four.
摘要翻译：通过相对于硅层的结晶特性适当地定向沟道长度方向，与常规技术相比，应变硅/碳材料的应力诱导效应可以显着提高。在一个说明性实施例中，通道可以沿着（100）表面取向沿着<100>方向取向，从而提供大约四分之一的电子迁移率增加。

8. 发明申请

US20100096698A1 STRESS ENHANCED TRANSISTOR 有权
标题翻译：应力增强晶体管
公开(公告)号：US20100096698A1
公开(公告)日：2010-04-22
申请号：US12644882
申请日：2009-12-22
申请人： Igor Peidous , Rohit Pal
发明人： Igor Peidous , Rohit Pal
IPC分类号： H01L29/78 , H01L29/06
CPC分类号： H01L29/78687 , H01L29/66553 , H01L29/66621 , H01L29/66628 , H01L29/66772 , H01L29/7848
摘要： Stress enhanced MOS transistors are provided. A semiconductor device is provided that comprises a semiconductor-on-insulator structure, a gate insulator layer, a source region, a drain region and a conductive gate overlying the gate insulator layer. The semiconductor-on-insulator structure comprises: a substrate, a semiconductor layer, and an insulating layer disposed between the substrate and the semiconductor layer. The semiconductor layer has a first surface, a second surface and a first region. The gate insulator layer overlies the first region, the conductive gate overlies the gate insulator layer, and the source region and the drain region overlie the first surface and comprise a strain-inducing epitaxial layer
摘要翻译：提供了应力增强型MOS晶体管。提供一种半导体器件，其包括绝缘体上半导体结构，栅极绝缘体层，源极区域，漏极区域和覆盖栅极绝缘体层的导电栅极。绝缘体上半导体结构包括：衬底，半导体层和设置在衬底和半导体层之间的绝缘层。半导体层具有第一表面，第二表面和第一区域。栅极绝缘体层覆盖第一区域，导电栅极覆盖栅极绝缘体层，源区域和漏极区域覆盖在第一表面上，并且包括应变诱导外延层

9. 发明授权

US07534689B2 Stress enhanced MOS transistor and methods for its fabrication 有权
标题翻译：应力增强型MOS晶体管及其制造方法
公开(公告)号：US07534689B2
公开(公告)日：2009-05-19
申请号：US11562209
申请日：2006-11-21
申请人： Rohit Pal , Igor Peidous , David Brown
发明人： Rohit Pal , Igor Peidous , David Brown
IPC分类号： H01L21/20
CPC分类号： H01L29/7848 , H01L21/02532 , H01L21/02639 , H01L21/823807 , H01L21/823814 , H01L29/045 , H01L29/165 , H01L29/66636
摘要： A stress enhanced MOS transistor and methods for its fabrication are provided. In one embodiment the method comprises forming a gate electrode overlying and defining a channel region in a monocrystalline semiconductor substrate. A trench having a side surface facing the channel region is etched into the monocrystalline semiconductor substrate adjacent the channel region. The trench is filled with a second monocrystalline semiconductor material having a first concentration of a substitutional atom and with a third monocrystalline semiconductor material having a second concentration of the substitutional atom. The second monocrystalline semiconductor material is epitaxially grown to have a wall thickness along the side surface sufficient to exert a greater stress on the channel region than the stress that would be exerted by a monocrystalline semiconductor material having the second concentration if the trench was filled by the third monocrystalline material alone.
摘要翻译：提供了一种应力增强型MOS晶体管及其制造方法。在一个实施例中，该方法包括形成覆盖并限定单晶半导体衬底中的沟道区的栅电极。具有面向通道区域的侧表面的沟槽被蚀刻到与沟道区域相邻的单晶半导体衬底中。沟槽填充有具有第一浓度的取代原子的第二单晶半导体材料和具有第二浓度取代原子的第三单晶半导体材料。第二单晶半导体材料被外延生长以具有沿着侧表面的壁厚，足以在沟道区域施加比由具有第二浓度的单晶半导体材料施加的应力更大的应力，如果沟槽由第三单晶材料。

10. 发明申请

US20080142835A1 STRESS ENHANCED TRANSISTOR AND METHODS FOR ITS FABRICATION 有权
标题翻译：应力增强晶体管及其制造方法
公开(公告)号：US20080142835A1
公开(公告)日：2008-06-19
申请号：US11611784
申请日：2006-12-15
申请人： Igor Peidous , Rohit Pal
发明人： Igor Peidous , Rohit Pal
IPC分类号： H01L29/778 , H01L21/336
CPC分类号： H01L29/78687 , H01L29/66553 , H01L29/66621 , H01L29/66628 , H01L29/66772 , H01L29/7848
摘要： A stress enhanced MOS transistor and methods for its fabrication are provided. A semiconductor-on-insulator structure is provided which includes a semiconductor layer having a first surface. A strain-inducing epitaxial layer is blanket deposited over the first surface, and can then be used to create a source region and a drain region which overlie the first surface.
摘要翻译：提供了一种应力增强型MOS晶体管及其制造方法。提供了一种绝缘体上半导体结构，其包括具有第一表面的半导体层。应变诱导外延层被覆盖地沉积在第一表面上，然后可用于产生覆盖在第一表面上的源极区域和漏极区域。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式