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1. 发明申请

US20080261408A1 METHODS FOR FABRICATING A STRESS ENHANCED SEMICONDUCTOR DEVICE HAVING NARROW PITCH AND WIDE PITCH TRANSISTORS 有权
标题翻译：用于制造具有窄波长和宽度极化晶体管的应力增强半导体器件的方法
公开(公告)号：US20080261408A1
公开(公告)日：2008-10-23
申请号：US11738828
申请日：2007-04-23
申请人： Andrew M. WAITE , Scott LUNING , Frank (Bin) Yang
发明人： Andrew M. WAITE , Scott LUNING , Frank (Bin) Yang
IPC分类号： H01L21/31
CPC分类号： H01L21/823807 , H01L21/84 , H01L27/1203 , H01L29/7843
摘要： A method is provided for fabricating a semiconductor device on a semiconductor substrate. A plurality of narrow gate pitch transistors (NPTs) and wide gate pitch transistors (WPTs) are formed on and in the semiconductor substrate. The NPTs are spaced apart by a first distance, and the WPTs are spaced apart by a second distance greater than the first distance. A first stress liner layer is deposited overlying the NPTs, the WPTs and the semiconductor layer, an etch stop layer is deposited overlying the first stress liner layer, and a second stress liner layer is deposited overlying the etch stop layer. A portion of the second stress liner layer which overlies the WPTs is covered, and an exposed portion of the second stress liner layer which overlies the NPTs is removed to expose an exposed portion of the etch stop layer. The exposed portion of the etch stop layer which overlies the NPTs is removed.
摘要翻译：提供了一种在半导体衬底上制造半导体器件的方法。在半导体衬底上形成多个窄栅极间距晶体管（NPT）和宽栅极间距晶体管（WPT）。 NPT间隔开第一距离，并且WPT间隔开大于第一距离的第二距离。沉积覆盖在NPT，WPT和半导体层上的第一应力衬垫层，沉积覆盖在第一应力衬垫层上的蚀刻停止层，并且沉积覆盖在蚀刻停止层上的第二应力衬垫层。覆盖在WPT上的第二应力衬垫层的一部分被覆盖，并且去除覆盖在NPT上的第二应力衬垫层的暴露部分以露出蚀刻停止层的暴露部分。去除覆盖在NPT上的蚀刻停止层的暴露部分。

2. 发明授权

US07521380B2 Methods for fabricating a stress enhanced semiconductor device having narrow pitch and wide pitch transistors 有权
标题翻译：制造具有窄间距和宽间距晶体管的应力增强型半导体器件的方法
公开(公告)号：US07521380B2
公开(公告)日：2009-04-21
申请号：US11738828
申请日：2007-04-23
申请人： Andrew M. Waite , Scott Luning , Frank (Bin) Yang
发明人： Andrew M. Waite , Scott Luning , Frank (Bin) Yang
IPC分类号： H01L21/31 , H01L21/469
CPC分类号： H01L21/823807 , H01L21/84 , H01L27/1203 , H01L29/7843
摘要： A method is provided for fabricating a semiconductor device on a semiconductor substrate. A plurality of narrow gate pitch transistors (NPTs) and wide gate pitch transistors (WPTs) are formed on and in the semiconductor substrate. The NPTs are spaced apart by a first distance, and the WPTs are spaced apart by a second distance greater than the first distance. A first stress liner layer is deposited overlying the NPTs, the WPTs and the semiconductor layer, an etch stop layer is deposited overlying the first stress liner layer, and a second stress liner layer is deposited overlying the etch stop layer. A portion of the second stress liner layer which overlies the WPTs is covered, and an exposed portion of the second stress liner layer which overlies the NPTs is removed to expose an exposed portion of the etch stop layer. The exposed portion of the etch stop layer which overlies the NPTs is removed.
摘要翻译：提供了一种在半导体衬底上制造半导体器件的方法。在半导体衬底上形成多个窄栅极间距晶体管（NPT）和宽栅极间距晶体管（WPT）。 NPT间隔开第一距离，并且WPT间隔开大于第一距离的第二距离。沉积覆盖在NPT，WPT和半导体层上的第一应力衬垫层，沉积覆盖在第一应力衬垫层上的蚀刻停止层，并且沉积覆盖在蚀刻停止层上的第二应力衬垫层。覆盖在WPT上的第二应力衬垫层的一部分被覆盖，并且去除覆盖在NPT上的第二应力衬垫层的暴露部分以露出蚀刻停止层的暴露部分。去除覆盖在NPT上的蚀刻停止层的暴露部分。

3. 发明申请

US20110062498A1 EMBEDDED SILICON GERMANIUM SOURCE DRAIN STRUCTURE WITH REDUCED SILICIDE ENCROACHMENT AND CONTACT RESISTANCE AND ENHANCED CHANNEL MOBILITY 有权
标题翻译：嵌入式硅锗锗排水结构，具有降低的硅胶密封性和接触电阻和增强的通道移动性
公开(公告)号：US20110062498A1
公开(公告)日：2011-03-17
申请号：US12561685
申请日：2009-09-17
申请人： Frank (Bin) Yang , Johan W. Weijtmans , Scott Luning
发明人： Frank (Bin) Yang , Johan W. Weijtmans , Scott Luning
IPC分类号： H01L29/772 , H01L21/335
CPC分类号： H01L29/665 , H01L29/165 , H01L29/6656 , H01L29/66575 , H01L29/66636 , H01L29/78 , H01L29/7848
摘要： Semiconductor devices with embedded silicon germanium source/drain regions are formed with enhanced channel mobility, reduced contact resistance, and reduced silicide encroachment. Embodiments include embedded silicon germanium source/drain regions with a first portion having a relatively high germanium concentration, e.g., about 25 to about 35 at. %, an overlying second portion having a first layer with a relatively low germanium concentration, e.g., about 10 to about 20 at. %, and a second layer having a germanium concentration greater than that of the first layer. Embodiments include forming additional layers on the second layer, each odd numbered layer having relatively low germanium concentration, at. % germanium, and each even numbered layer having a relatively high germanium concentration. Embodiments include forming the first region at a thickness of about 400 Å to 28 about 800 Å, and the first and second layers at a thickness of about 30 Å to about 70 Å.
摘要翻译：具有嵌入式硅锗源极/漏极区域的半导体器件形成具有增强的沟道迁移率，降低的接触电阻和减少的硅化物侵蚀。实施例包括具有较高锗浓度的第一部分的嵌入式硅锗源/漏区，例如约25至约35at。％，上覆的第二部分具有具有相对低的锗浓度的第一层，例如约10至约20at。％，第二层的锗浓度大于第一层的浓度。实施例包括在第二层上形成附加层，每个奇数层具有较低的锗浓度。％锗，并且每个偶数层具有较高的锗浓度。实施例包括形成厚度为约400至28约800的第一区域，第一和第二层的厚度为约至大约为70埃。

4. 发明授权

US08120120B2 Embedded silicon germanium source drain structure with reduced silicide encroachment and contact resistance and enhanced channel mobility 有权
标题翻译：嵌入式硅锗源极漏极结构，具有减少的硅化物侵蚀和接触电阻以及增强的沟道迁移率
公开(公告)号：US08120120B2
公开(公告)日：2012-02-21
申请号：US12561685
申请日：2009-09-17
申请人： Frank (Bin) Yang , Johan W. Weijtmans , Scott Luning
发明人： Frank (Bin) Yang , Johan W. Weijtmans , Scott Luning
IPC分类号： H01L29/772 , H01L21/335
CPC分类号： H01L29/665 , H01L29/165 , H01L29/6656 , H01L29/66575 , H01L29/66636 , H01L29/78 , H01L29/7848
摘要： Semiconductor devices with embedded silicon germanium source/drain regions are formed with enhanced channel mobility, reduced contact resistance, and reduced silicide encroachment. Embodiments include embedded silicon germanium source/drain regions with a first portion having a relatively high germanium concentration, e.g., about 25 to about 35 at. %, an overlying second portion having a first layer with a relatively low germanium concentration, e.g., about 10 to about 20 at. %, and a second layer having a germanium concentration greater than that of the first layer. Embodiments include forming additional layers on the second layer, each odd numbered layer having relatively low germanium concentration, at. % germanium, and each even numbered layer having a relatively high germanium concentration. Embodiments include forming the first region at a thickness of about 400 Å to 28 about 800 Å, and the first and second layers at a thickness of about 30 Å to about 70 Å.
摘要翻译：具有嵌入式硅锗源极/漏极区域的半导体器件形成具有增强的沟道迁移率，降低的接触电阻和减少的硅化物侵蚀。实施例包括具有较高锗浓度的第一部分的嵌入式硅锗源/漏区，例如约25至约35at。％，上覆的第二部分具有具有相对低的锗浓度的第一层，例如约10至约20at。％，第二层的锗浓度大于第一层的浓度。实施例包括在第二层上形成附加层，每个奇数层具有较低的锗浓度。％锗，并且每个偶数层具有较高的锗浓度。实施例包括形成厚度为约400至28约800的第一区域，第一和第二层的厚度为约至大约为70埃。

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