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1. 发明授权

US06961886B2 Diagnostic method for structural scan chain designs 失效
标题翻译：结构扫描链设计的诊断方法
公开(公告)号：US06961886B2
公开(公告)日：2005-11-01
申请号：US10249513
申请日：2003-04-16
申请人： Franco Motika , Phillip J. Nigh , Phong T. Tran
发明人： Franco Motika , Phillip J. Nigh , Phong T. Tran
IPC分类号： G01R31/3185 , G01R31/28
CPC分类号： G01R31/318566 , G01R31/318569
摘要： A method for testing and diagnosing shift register latch chains coupled to logic circuits in an integrated circuit, the method including: (a) determining which of the shift register latch chains are failing by propagating a test pattern of zeros and ones through the shift register latch chains while gating which of the shift register latch chains contents are propagated into the means for generating a test signature; and (b) for each failing shift register latch chain: (b1) propagating a test pattern through the shift register latch chains while gating a selected sequential group of latches in a failing shift register latch to propagate into the means for generating a test signature; (b2) reducing the number of latches in the sequential group of latches; and (b3) repeating steps (b1) and (b2) until all failing latches of the failing shift register latch chain have been determined.
摘要翻译：一种用于测试和诊断耦合到集成电路中的逻辑电路的移位寄存器锁存链的方法，所述方法包括：（a）通过通过移位寄存器锁存器传播零和一个测试模式来确定移位寄存器锁存链中的哪一个失败同时选通移位寄存器锁链内容中的哪一个内容被传播到用于生成测试签名的装置中; 和（b）对于每个失败的移位寄存器锁存链：（b 1）通过移位寄存器锁存链传播测试模式，同时选通故障移位寄存器锁存器中的所选顺序锁存器组，以传播到生成测试签名的装置 ; （b 2）减少锁存器序列组中的锁存器数量; 和（b 3）重复步骤（b 1）和（b 2），直到确定了故障移位寄存器锁存链的所有故障锁存器。

2. 发明授权

US07017095B2 Functional pattern logic diagnostic method 失效
标题翻译：功能模式逻辑诊断方法
公开(公告)号：US07017095B2
公开(公告)日：2006-03-21
申请号：US10064398
申请日：2002-07-10
申请人： Donato Forlenza , Franco Motika , Phillip J. Nigh
发明人： Donato Forlenza , Franco Motika , Phillip J. Nigh
IPC分类号： G01R31/28 , G06F11/00
CPC分类号： G01R31/318586 , G01R31/318544
摘要： A method of diagnosing semiconductor device functional testing failures by combining deterministic and functional testing to create a new test pattern based on the functional failure by determining the location of and type of error in the failing circuit. This is accomplished by identifying the failing vector during the functional test, observing the states of the failed device by unloading the values of the latches from the LSSD scan chain before the failing vector, generating a LOAD from the unloaded states of the latches, applying the generated LOAD as the first event of a newly created independent LSSD deterministic pattern, applying the primary inputs and Clocks that produced the failure to a correctly operating device, unloading the output of the correctly operating device to generate a deterministic LSSD pattern; and applying the generated deterministic LSSD pattern to the failing device to diagnose the failure using existing LSSD deterministic tools.
摘要翻译：通过组合确定性和功能测试，通过确定故障电路中的错误的位置和类型，基于功能故障来创建新的测试模式来诊断半导体器件功能测试故障的方法。这是通过在功能测试期间识别故障向量来实现的，通过在故障向量之前从LSSD扫描链中卸载锁存器的值来观察故障设备的状态，从锁存器的未加载状态生成LOAD，应用生成LOAD作为新创建的独立LSSD确定性模式的第一个事件，将产生故障的主输入和时钟应用于正确操作的设备，卸载正确操作设备的输出以生成确定性LSSD模式; 以及将生成的确定性LSSD模式应用于故障设备，以使用现有的LSSD确定性工具来诊断故障。

3. 发明授权

US06442723B1 Logic built-in self test selective signature generation 失效
标题翻译：逻辑内置自检选择性签名生成
公开(公告)号：US06442723B1
公开(公告)日：2002-08-27
申请号：US09310445
申请日：1999-05-12
申请人： Timothy J. Koprowski , Franco Motika , Phillip J. Nigh
发明人： Timothy J. Koprowski , Franco Motika , Phillip J. Nigh
IPC分类号： G01R313185
CPC分类号： G01R31/318371
摘要： LBIST resource parameters are used to control the data inputs for the signature generation process. These resource parameters include a LBIST pattern cycle counter, a channel input selected to input the MISR, and a channel load/unload shift counter. Properly setting one or more of these resource parameters to conditionally control those latch content values that get clocked into the MISR during the unload operation generates a three dimensional signature space.
摘要翻译： LBIST资源参数用于控制签名生成过程的数据输入。这些资源参数包括LBIST模式周期计数器，选择输入MISR的通道输入和通道加载/卸载移位计数器。适当地设置这些资源参数中的一个或多个以有条件地控制在卸载操作期间被计入MISR的锁存内容值产生三维签名空间。

4. 发明申请

US20090217116A1 DIAGNOSABLE GENERAL PURPOSE TEST REGISTERS SCAN CHAIN DESIGN 有权
标题翻译：可诊断的一般用途测试寄存器扫描链设计
公开(公告)号：US20090217116A1
公开(公告)日：2009-08-27
申请号：US12036320
申请日：2008-02-25
申请人： Franco Motika , Michael R. Ouellette , Phong T. Tran
发明人： Franco Motika , Michael R. Ouellette , Phong T. Tran
IPC分类号： G06F11/00
CPC分类号： G01R31/318541 , G01R31/318536
摘要： A structural design-for-test for diagnosing broken scan chain defects of long non-scannable register chains (GPTR) The GPTR and the system for testing and diagnosing the broken LSSD scan-only chains rapidly localize defects to the failing Shift Register Latch (SRL) pair. The GPTR modifies the latches used in the GPTR scan chain to standard LSSD L1/L2 master-slave SRL type latch pairs; connects all the system ports of the L1 latches to the Shift Register Input (SRI) and clocked by the system C1-clk while the L1 scan port is clocked by the A-clk and L2 scan port is clocked only by the B-clk. The L1 latches are connected to at least one multiplexer having a first output connected to an input of each odd SRL, and a second output connected to an input port of each even SRL. In another embodiment, the GPTR includes a plurality of multiplexers respectively coupled to the master-slave latch pairs, wherein a first set of multiplexers have their respective output attached to an input of the odd L1 latches, and a second set of the multiplexers have their respective output attached to an input port of the even L1 latches.
摘要翻译：用于诊断长不可扫描寄存器链（GPTR）的断层扫描链缺陷的结构设计 - 用于测试和诊断断裂的LSSD扫描链的系统快速将缺陷定位到故障移位寄存器锁存器（SRL））对。 GPTR将GPTR扫描链中使用的锁存器修改为标准LSSD L1 / L2主从SL型锁存器对; 将L1锁存器的所有系统端口连接到移位寄存器输入（SRI）并由系统C1-clk计时，而L1扫描端口由A-clk计时，L2扫描端口由B-clk提供时钟。 L1锁存器连接到至少一个多路复用器，其具有连接到每个奇数SRL的输入的第一输出，以及连接到每个偶数SRL的输入端口的第二输出。在另一个实施例中，GPTR包括分别耦合到主从锁存器对的多个复用器，其中第一组复用器具有附加到奇数L1锁存器的输入的相应输出，并且第二组复用器具有它们相应的输出附加到偶数L1锁存器的输入端口。

5. 发明授权

US06751765B1 Method and system for determining repeatable yield detractors of integrated circuits 失效
标题翻译：用于确定集成电路的可重复产量剔除器的方法和系统
公开(公告)号：US06751765B1
公开(公告)日：2004-06-15
申请号：US09722880
申请日：2000-11-27
申请人： Richard F. Rizzolo , Rocco E. DeStefano , Joseph E. Eckelman , Thomas G. Foote , Steven Michnowski , Franco Motika , Phillip J. Nigh , Bryan J. Robbins
发明人： Richard F. Rizzolo , Rocco E. DeStefano , Joseph E. Eckelman , Thomas G. Foote , Steven Michnowski , Franco Motika , Phillip J. Nigh , Bryan J. Robbins
IPC分类号： G01R3128
CPC分类号： G01R31/3185
摘要： An exemplary embodiment of the invention is a method for LBIST testing integrated circuit. The method includes generating a plurality of multi-bit test patterns and grouping the multi-bit test patterns by a plurality of test pattern partitions including a first test pattern partition having a first number of bits and a second test pattern partition having second number of bits greater than the first number. The first test pattern partition is applied to the integrated circuit to generate a first signature that is compared to a first reference signature to detect a failure. The second test pattern partition is applied to the integrated circuit to generate a second signature that is compared to a second reference signature to detect a failure in the integrated circuit.
摘要翻译：本发明的示例性实施例是用于LBIST测试集成电路的方法。该方法包括生成多个多位测试模式，并且通过多个测试模式分区对多位测试模式进行分组，所述多个测试模式分区包括具有第一数量位的第一测试模式分区和具有第二数量位的第二测试模式分区大于第一个数字。将第一测试模式分区应用于集成电路以生成与第一参考签名进行比较以检测故障的第一签名。将第二测试模式分区应用于集成电路以产生与第二参考签名进行比较的第二签名，以检测集成电路中的故障。

6. 发明授权

US06516432B1 AC scan diagnostic method 失效
标题翻译： AC扫描诊断方法
公开(公告)号：US06516432B1
公开(公告)日：2003-02-04
申请号：US09469699
申请日：1999-12-22
申请人： Franco Motika , Phillip J. Nigh , Peilin Song , Howard B. Druckerman
发明人： Franco Motika , Phillip J. Nigh , Peilin Song , Howard B. Druckerman
IPC分类号： G01R3128
CPC分类号： G01R31/318577
摘要： Disclosed is an alternating current (AC) scan diagnostic system in which one or a plurality of scan chains are tested by serially propagating predetermined bit patterns through the scan chain and comparing the output against an expected result. The system comprises identification phase, verifications and localization, and a characterization phases. The system is adaptable for use with on-board diagnostics and is adaptable for use with on-product clock generation systems.
摘要翻译：公开了一种交流（AC）扫描诊断系统，其中一个或多个扫描链通过通过扫描链串行传播预定位图案并将输出与预期结果进行比较来测试。该系统包括识别阶段，验证和定位以及特征化阶段。该系统适用于车载诊断，适用于产品上的时钟发生系统。

7. 发明申请

US20080172576A1 METHOD FOR ENHANCING THE DIAGNOSTIC ACCURACY OF A VLSI CHIP 失效
标题翻译：用于增强VLSI芯片诊断精度的方法
公开(公告)号：US20080172576A1
公开(公告)日：2008-07-17
申请号：US11622055
申请日：2007-01-11
申请人： Mary P. Kusko , Gary W. Maier , Franco Motika , Phong T. Tran
发明人： Mary P. Kusko , Gary W. Maier , Franco Motika , Phong T. Tran
IPC分类号： G06F11/26
CPC分类号： G06F11/261
摘要： A diagnostic process applicable to VLSI designs to address the accuracy of diagnostic resolution. Environmentally based fail data drives adaptive test methods which hone the test pattern set and fail data collection for successful diagnostic resolution. Environmentally based fail data is used in diagnostic simulation to achieve a more accurate environmentally based fault callout. When needed, additional information is included in the process to further refine and define the simulation or callout result. Similarly, as needed adaptive test pattern generation methods are employed to result in enhanced diagnostic resolution.
摘要翻译：适用于VLSI设计的诊断过程，以解决诊断解决的准确性。基于环境的故障数据驱动自适应测试方法，其中测试模式集合和数据收集失败，以便成功诊断分辨率。基于环境的故障数据用于诊断仿真，以实现更准确的基于环境的故障标注。当需要时，该过程中将包含其他信息，以进一步完善和定义模拟或标注结果。类似地，根据需要采用自适应测试模式生成方法来提高诊断分辨率。

8. 发明授权

US07908534B2 Diagnosable general purpose test registers scan chain design 有权
标题翻译：可诊断通用测试寄存器扫描链设计
公开(公告)号：US07908534B2
公开(公告)日：2011-03-15
申请号：US12036320
申请日：2008-02-25
申请人： Franco Motika , Michael R. Ouellette , Phong T. Tran
发明人： Franco Motika , Michael R. Ouellette , Phong T. Tran
IPC分类号： G01R31/28
CPC分类号： G01R31/318541 , G01R31/318536
摘要： A structural design-for-test for diagnosing broken scan chain defects of long non-scannable register chains (GPTR) The GPTR and the system for testing and diagnosing the broken LSSD scan-only chains rapidly localize defects to the failing Shift Register Latch (SRL) pair. The GPTR modifies the latches used in the GPTR scan chain to standard LSSD L1/L2 master-slave SRL type latch pairs; connects all the system ports of the L1 latches to the Shift Register Input (SRI) and clocked by the system C1-clk while the L1 scan port is clocked by the A-clk and L2 scan port is clocked only by the B-clk. The L1 latches are connected to at least one multiplexer having a first output connected to an input of each odd SRL, and a second output connected to an input port of each even SRL. In another embodiment, the GPTR includes a plurality of multiplexers respectively coupled to the master-slave latch pairs, wherein a first set of multiplexers have their respective output attached to an input of the odd L1 latches, and a second set of the multiplexers have their respective output attached to an input port of the even L1 latches.
摘要翻译：用于诊断长不可扫描寄存器链（GPTR）的断层扫描链缺陷的结构设计 - 用于测试和诊断断裂的LSSD扫描链的系统快速将缺陷定位到故障移位寄存器锁存器（SRL））对。 GPTR将GPTR扫描链中使用的锁存器修改为标准LSSD L1 / L2主从SL型锁存器对; 将L1锁存器的所有系统端口连接到移位寄存器输入（SRI）并由系统C1-clk计时，而L1扫描端口由A-clk计时，L2扫描端口由B-clk提供时钟。 L1锁存器连接到至少一个多路复用器，其具有连接到每个奇数SRL的输入的第一输出，以及连接到每个偶数SRL的输入端口的第二输出。在另一个实施例中，GPTR包括分别耦合到主从锁存器对的多个复用器，其中第一组复用器具有附加到奇数L1锁存器的输入的相应输出，并且第二组复用器具有它们相应的输出附加到偶数L1锁存器的输入端口。

9. 发明授权

US5930270A Logic built in self-test diagnostic method 失效
标题翻译：逻辑内置自检诊断方法
公开(公告)号：US5930270A
公开(公告)日：1999-07-27
申请号：US898942
申请日：1997-07-23
申请人： Donato O. Forlenza , Franco Motika , John J. Shushereba , Phillip J. Nigh
发明人： Donato O. Forlenza , Franco Motika , John J. Shushereba , Phillip J. Nigh
IPC分类号： G01R31/3177 , G01R31/3185 , G06F11/22 , G01R31/28 , G06F11/00
CPC分类号： G06F11/2268 , G01R31/3177 , G01R31/318566 , G01R31/31816
摘要： A system and method for diagnosing the faults of an electronic device by running a series of tests, identifying the tests where the electronic device failed, without having to check the results of each test, storing information generated during only the tests where the electronic device failed, and using the information to diagnose the faults in the electronic device. The test results are accumulated into a Multiple Input Shift Register (MISR) which need not be examined after each test to determine which tests the device failed. The problem of a failure during one test manifesting into the MISR during subsequent tests is handled by predicting the effect of the failure on the MISR during subsequent tests.
摘要翻译：一种用于通过运行一系列测试来识别电子设备失败的测试的电子设备的故障的系统和方法，而不必检查每个测试的结果，仅存储在电子设备失败的测试期间产生的信息，并使用该信息来诊断电子设备中的故障。测试结果累积到多输入移位寄存器（MISR）中，每次测试后不需要检查，以确定器件出现哪些测试失败。在后续测试期间在一次测试中出现故障的问题是通过在随后的测试期间预测故障对MISR的影响来处理的。

10. 发明授权

US07831863B2 Method for enhancing the diagnostic accuracy of a VLSI chip 失效
标题翻译：提高VLSI芯片诊断精度的方法
公开(公告)号：US07831863B2
公开(公告)日：2010-11-09
申请号：US11622055
申请日：2007-01-11
申请人： Mary P. Kusko , Gary W. Maier , Franco Motika , Phong T. Tran
发明人： Mary P. Kusko , Gary W. Maier , Franco Motika , Phong T. Tran
IPC分类号： G06F11/00
CPC分类号： G06F11/261
摘要： A diagnostic process applicable to VLSI designs to address the accuracy of diagnostic resolution. Environmentally based fail data drives adaptive test methods which hone the test pattern set and fail data collection for successful diagnostic resolution. Environmentally based fail data is used in diagnostic simulation to achieve a more accurate environmentally based fault callout. When needed, additional information is included in the process to further refine and define the simulation or callout result. Similarly, as needed adaptive test pattern generation methods are employed to result in enhanced diagnostic resolution.
摘要翻译：适用于VLSI设计的诊断过程，以解决诊断解决的准确性。基于环境的故障数据驱动自适应测试方法，其中测试模式集合和数据收集失败，以便成功诊断分辨率。基于环境的故障数据用于诊断仿真，以实现更准确的基于环境的故障标注。当需要时，该过程中将包含其他信息，以进一步完善和定义模拟或标注结果。类似地，根据需要采用自适应测试模式生成方法来提高诊断分辨率。

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