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1. 发明授权

US5930270A Logic built in self-test diagnostic method 失效
标题翻译：逻辑内置自检诊断方法
公开(公告)号：US5930270A
公开(公告)日：1999-07-27
申请号：US898942
申请日：1997-07-23
申请人： Donato O. Forlenza , Franco Motika , John J. Shushereba , Phillip J. Nigh
发明人： Donato O. Forlenza , Franco Motika , John J. Shushereba , Phillip J. Nigh
IPC分类号： G01R31/3177 , G01R31/3185 , G06F11/22 , G01R31/28 , G06F11/00
CPC分类号： G06F11/2268 , G01R31/3177 , G01R31/318566 , G01R31/31816
摘要： A system and method for diagnosing the faults of an electronic device by running a series of tests, identifying the tests where the electronic device failed, without having to check the results of each test, storing information generated during only the tests where the electronic device failed, and using the information to diagnose the faults in the electronic device. The test results are accumulated into a Multiple Input Shift Register (MISR) which need not be examined after each test to determine which tests the device failed. The problem of a failure during one test manifesting into the MISR during subsequent tests is handled by predicting the effect of the failure on the MISR during subsequent tests.
摘要翻译：一种用于通过运行一系列测试来识别电子设备失败的测试的电子设备的故障的系统和方法，而不必检查每个测试的结果，仅存储在电子设备失败的测试期间产生的信息，并使用该信息来诊断电子设备中的故障。测试结果累积到多输入移位寄存器（MISR）中，每次测试后不需要检查，以确定器件出现哪些测试失败。在后续测试期间在一次测试中出现故障的问题是通过在随后的测试期间预测故障对MISR的影响来处理的。

2. 发明授权

US5960114A Process for identifying and capturing text 失效
标题翻译：识别和捕获文本的过程
公开(公告)号：US5960114A
公开(公告)日：1999-09-28
申请号：US739136
申请日：1996-10-28
申请人： Norman J. Dauerer , Donato O. Forlenza , Edward E. Kelley , Franco Motika
发明人： Norman J. Dauerer , Donato O. Forlenza , Edward E. Kelley , Franco Motika
IPC分类号： G06F17/24 , G06K9/72
CPC分类号： G06F17/24
摘要： A process for identifying and capturing text comprising the steps of identifying delimiters in the text, selecting delimiters from the identified delimiters to be delimiters to the left and right of the selected text, indicating only one character of the text between the left and right delimiters, and automatically blocking and capturing the text having the indicated character. In an alternate embodiment, the process comprises the steps of identifying delimiters in the text that are to the left and to the right of a cursor and identifying the position of the delimiters relative to the cursor, specifying at least one particular delimiter position relative to the cursor, indicating only one character of the text between the cursor and the specified delimiter position, and automatically blocking and capturing the text having the indicated character.
摘要翻译：用于识别和捕获文本的过程，包括以下步骤：识别文本中的分隔符，从所标识的分隔符中选择分隔符，以将所选择的文本的左侧和右侧分隔符，仅指示左和右分隔符之间的文本的一个字符，并自动阻止并捕获具有指定字符的文本。在替代实施例中，该过程包括以下步骤：识别文本中位于光标左侧和右侧的分隔符，并且识别分隔符相对于光标的位置，指定相对于该光标至少一个特定分隔符位置光标，仅指示光标和指定的分隔符位置之间的文本的一个字符，并自动阻止并捕获具有指定字符的文本。

3. 发明授权

US07017095B2 Functional pattern logic diagnostic method 失效
标题翻译：功能模式逻辑诊断方法
公开(公告)号：US07017095B2
公开(公告)日：2006-03-21
申请号：US10064398
申请日：2002-07-10
申请人： Donato Forlenza , Franco Motika , Phillip J. Nigh
发明人： Donato Forlenza , Franco Motika , Phillip J. Nigh
IPC分类号： G01R31/28 , G06F11/00
CPC分类号： G01R31/318586 , G01R31/318544
摘要： A method of diagnosing semiconductor device functional testing failures by combining deterministic and functional testing to create a new test pattern based on the functional failure by determining the location of and type of error in the failing circuit. This is accomplished by identifying the failing vector during the functional test, observing the states of the failed device by unloading the values of the latches from the LSSD scan chain before the failing vector, generating a LOAD from the unloaded states of the latches, applying the generated LOAD as the first event of a newly created independent LSSD deterministic pattern, applying the primary inputs and Clocks that produced the failure to a correctly operating device, unloading the output of the correctly operating device to generate a deterministic LSSD pattern; and applying the generated deterministic LSSD pattern to the failing device to diagnose the failure using existing LSSD deterministic tools.
摘要翻译：通过组合确定性和功能测试，通过确定故障电路中的错误的位置和类型，基于功能故障来创建新的测试模式来诊断半导体器件功能测试故障的方法。这是通过在功能测试期间识别故障向量来实现的，通过在故障向量之前从LSSD扫描链中卸载锁存器的值来观察故障设备的状态，从锁存器的未加载状态生成LOAD，应用生成LOAD作为新创建的独立LSSD确定性模式的第一个事件，将产生故障的主输入和时钟应用于正确操作的设备，卸载正确操作设备的输出以生成确定性LSSD模式; 以及将生成的确定性LSSD模式应用于故障设备，以使用现有的LSSD确定性工具来诊断故障。

4. 发明授权

US06442723B1 Logic built-in self test selective signature generation 失效
标题翻译：逻辑内置自检选择性签名生成
公开(公告)号：US06442723B1
公开(公告)日：2002-08-27
申请号：US09310445
申请日：1999-05-12
申请人： Timothy J. Koprowski , Franco Motika , Phillip J. Nigh
发明人： Timothy J. Koprowski , Franco Motika , Phillip J. Nigh
IPC分类号： G01R313185
CPC分类号： G01R31/318371
摘要： LBIST resource parameters are used to control the data inputs for the signature generation process. These resource parameters include a LBIST pattern cycle counter, a channel input selected to input the MISR, and a channel load/unload shift counter. Properly setting one or more of these resource parameters to conditionally control those latch content values that get clocked into the MISR during the unload operation generates a three dimensional signature space.
摘要翻译： LBIST资源参数用于控制签名生成过程的数据输入。这些资源参数包括LBIST模式周期计数器，选择输入MISR的通道输入和通道加载/卸载移位计数器。适当地设置这些资源参数中的一个或多个以有条件地控制在卸载操作期间被计入MISR的锁存内容值产生三维签名空间。

5. 发明授权

US06751765B1 Method and system for determining repeatable yield detractors of integrated circuits 失效
标题翻译：用于确定集成电路的可重复产量剔除器的方法和系统
公开(公告)号：US06751765B1
公开(公告)日：2004-06-15
申请号：US09722880
申请日：2000-11-27
申请人： Richard F. Rizzolo , Rocco E. DeStefano , Joseph E. Eckelman , Thomas G. Foote , Steven Michnowski , Franco Motika , Phillip J. Nigh , Bryan J. Robbins
发明人： Richard F. Rizzolo , Rocco E. DeStefano , Joseph E. Eckelman , Thomas G. Foote , Steven Michnowski , Franco Motika , Phillip J. Nigh , Bryan J. Robbins
IPC分类号： G01R3128
CPC分类号： G01R31/3185
摘要： An exemplary embodiment of the invention is a method for LBIST testing integrated circuit. The method includes generating a plurality of multi-bit test patterns and grouping the multi-bit test patterns by a plurality of test pattern partitions including a first test pattern partition having a first number of bits and a second test pattern partition having second number of bits greater than the first number. The first test pattern partition is applied to the integrated circuit to generate a first signature that is compared to a first reference signature to detect a failure. The second test pattern partition is applied to the integrated circuit to generate a second signature that is compared to a second reference signature to detect a failure in the integrated circuit.
摘要翻译：本发明的示例性实施例是用于LBIST测试集成电路的方法。该方法包括生成多个多位测试模式，并且通过多个测试模式分区对多位测试模式进行分组，所述多个测试模式分区包括具有第一数量位的第一测试模式分区和具有第二数量位的第二测试模式分区大于第一个数字。将第一测试模式分区应用于集成电路以生成与第一参考签名进行比较以检测故障的第一签名。将第二测试模式分区应用于集成电路以产生与第二参考签名进行比较的第二签名，以检测集成电路中的故障。

6. 发明授权

US06516432B1 AC scan diagnostic method 失效
标题翻译： AC扫描诊断方法
公开(公告)号：US06516432B1
公开(公告)日：2003-02-04
申请号：US09469699
申请日：1999-12-22
申请人： Franco Motika , Phillip J. Nigh , Peilin Song , Howard B. Druckerman
发明人： Franco Motika , Phillip J. Nigh , Peilin Song , Howard B. Druckerman
IPC分类号： G01R3128
CPC分类号： G01R31/318577
摘要： Disclosed is an alternating current (AC) scan diagnostic system in which one or a plurality of scan chains are tested by serially propagating predetermined bit patterns through the scan chain and comparing the output against an expected result. The system comprises identification phase, verifications and localization, and a characterization phases. The system is adaptable for use with on-board diagnostics and is adaptable for use with on-product clock generation systems.
摘要翻译：公开了一种交流（AC）扫描诊断系统，其中一个或多个扫描链通过通过扫描链串行传播预定位图案并将输出与预期结果进行比较来测试。该系统包括识别阶段，验证和定位以及特征化阶段。该系统适用于车载诊断，适用于产品上的时钟发生系统。

7. 发明授权

US06961886B2 Diagnostic method for structural scan chain designs 失效
标题翻译：结构扫描链设计的诊断方法
公开(公告)号：US06961886B2
公开(公告)日：2005-11-01
申请号：US10249513
申请日：2003-04-16
申请人： Franco Motika , Phillip J. Nigh , Phong T. Tran
发明人： Franco Motika , Phillip J. Nigh , Phong T. Tran
IPC分类号： G01R31/3185 , G01R31/28
CPC分类号： G01R31/318566 , G01R31/318569
摘要： A method for testing and diagnosing shift register latch chains coupled to logic circuits in an integrated circuit, the method including: (a) determining which of the shift register latch chains are failing by propagating a test pattern of zeros and ones through the shift register latch chains while gating which of the shift register latch chains contents are propagated into the means for generating a test signature; and (b) for each failing shift register latch chain: (b1) propagating a test pattern through the shift register latch chains while gating a selected sequential group of latches in a failing shift register latch to propagate into the means for generating a test signature; (b2) reducing the number of latches in the sequential group of latches; and (b3) repeating steps (b1) and (b2) until all failing latches of the failing shift register latch chain have been determined.
摘要翻译：一种用于测试和诊断耦合到集成电路中的逻辑电路的移位寄存器锁存链的方法，所述方法包括：（a）通过通过移位寄存器锁存器传播零和一个测试模式来确定移位寄存器锁存链中的哪一个失败同时选通移位寄存器锁链内容中的哪一个内容被传播到用于生成测试签名的装置中; 和（b）对于每个失败的移位寄存器锁存链：（b 1）通过移位寄存器锁存链传播测试模式，同时选通故障移位寄存器锁存器中的所选顺序锁存器组，以传播到生成测试签名的装置 ; （b 2）减少锁存器序列组中的锁存器数量; 和（b 3）重复步骤（b 1）和（b 2），直到确定了故障移位寄存器锁存链的所有故障锁存器。

8. 发明授权

US08055587B2 Man in the middle computer technique 失效
标题翻译：人在中间计算机技术
公开(公告)号：US08055587B2
公开(公告)日：2011-11-08
申请号：US12132203
申请日：2008-06-03
申请人： Wayne M. Delia , Edward E. Kelley , Franco Motika
发明人： Wayne M. Delia , Edward E. Kelley , Franco Motika
IPC分类号： H04L9/32 , G06F17/60
CPC分类号： H04L63/0428 , H04L63/083 , H04L63/1466
摘要： A method for constructing a secure Internet transaction, the method includes: receiving a user identification (userid) and user password on a client device for filling out a form generated by a secure web site; concatenating the user's Internet Protocol (IP) address with a separate password that is maintained on the secure web site that the user is authenticating to; encrypting the concatenated user IP and separate password to form an Internet Protocol password (IPPW); wherein the encrypting is carried out with a client device linear feedback shift register (LFSR) with a defined cycle count; building a transaction consisting of the IPPW, defined cycle count, and userid; transmitting the transaction and form via a network towards the secure web site; wherein in response the secure website performs the following: decrypts the IPPW, and determines if the IP portion of the decrypted IPPW is equal to the user's IP address.
摘要翻译：一种用于构建安全因特网事务的方法，所述方法包括：在客户端设备上接收用户标识（用户ID）和用户密码，以填写由安全网站生成的表单; 将用户的因特网协议（IP）地址与在用户正在认证的安全网站上维护的单独的密码连接起来; 加密连接的用户IP和单独的密码以形成Internet协议密码（IPPW）; 其中所述加密是利用具有定义的周期计数的客户端设备线性反馈移位寄存器（LFSR）来执行的; 构建由IPPW，定义的循环计数和userid组成的事务; 通过网络向安全网站传送交易和表单; 其中作为响应，安全网站执行以下操作：解密IPPW，并确定解密的IPPW的IP部分是否等于用户的IP地址。

9. 发明授权

US08050484B2 Method and system for image recognition for aiding the visually impaired 失效
标题翻译：帮助视力障碍者进行图像识别的方法和系统
公开(公告)号：US08050484B2
公开(公告)日：2011-11-01
申请号：US11833547
申请日：2007-08-03
申请人： Joseph B. Frei , Edward E. Kelley , Franco Motika
发明人： Joseph B. Frei , Edward E. Kelley , Franco Motika
IPC分类号： G06K9/00
CPC分类号： G09B21/003
摘要： A method for tracking paper currency in a holder, includes: scanning paper currency deposited or removed from a holder; determining the total number of each individual denomination of paper currency contained within the holder based on the scanned paper currency deposited and removed from the holder; recording the total number of each individual denomination of paper currency; determining the total value of the paper currency within the holder; outputting the denomination of paper currency when the paper currency is scanned during depositing or removal from the holder; outputting the recorded number of each individual denomination of paper currency and the total value of the currency within the holder; and wherein the recorded number of each individual denomination of paper currency and the total value of the currency within the holder is dynamically tabulated based on the scanning of paper currency deposited or removed from the holder.
摘要翻译：用于跟踪持有人纸币的方法包括：扫描从持有人存放或移走的纸币; 根据从持有人存放和移除的扫描纸币确定持有人所包含的每种纸币种类总数; 记录每个单位面值纸币的总数; 确定持有人内纸币的总价值; 在从持有人进行存放或清除期间扫描纸币时输出纸币的面额; 输出每个单独面值纸币的记录数量和持有人内货币的总价值; 并且其中，基于从所述持有者存放或移除的纸币的扫描，将所述纸币的每个单独面值的记录数量和所述持有者内的所述货币的总价值动态地列表。

10. 发明授权

US07759960B2 Integrated circuit testing methods using well bias modification 失效
标题翻译：集成电路测试方法采用偏置修正
公开(公告)号：US07759960B2
公开(公告)日：2010-07-20
申请号：US12103906
申请日：2008-04-16
申请人： Anne E. Gattiker , David A. Grosch , Marc D. Knox , Franco Motika , Phil Nigh , Jody Van Horn , Paul S. Zuchowski
发明人： Anne E. Gattiker , David A. Grosch , Marc D. Knox , Franco Motika , Phil Nigh , Jody Van Horn , Paul S. Zuchowski
IPC分类号： G01R31/26
CPC分类号： G01R31/2879 , G01R31/275 , G01R31/2856 , G01R31/3004 , G01R31/3008
摘要： Methods for testing a semiconductor circuit (10) including testing the circuit and modifying a well bias (14, 18) of the circuit during testing. The methods improve the resolution of voltage-based and IDDQ testing and diagnosis by modifying well bias during testing. In addition, the methods provide more efficient stresses during stress testing. The methods apply to ICs where the semiconductor well (wells and/or substrates) are wired separately from the chip VDD and GND, allowing for external control (40) of the well potentials during test. In general, the methods rely on using the well bias to change transistor threshold voltages.
摘要翻译：测试半导体电路（10）的方法，包括在测试期间测试电路和修改电路的阱偏压（14,18）。该方法通过在测试过程中改善阱偏差来提高基于电压和IDDQ测试和诊断的分辨率。此外，这些方法在应力测试期间提供更有效的应力。该方法适用于半导体阱（阱和/或衬底）与芯片VDD和GND分开接线的IC，允许在测试期间外部控制（40）阱电位。通常，这些方法依靠使用阱偏置来改变晶体管阈值电压。

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