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1. 发明授权

US5930270A Logic built in self-test diagnostic method 失效
标题翻译：逻辑内置自检诊断方法
公开(公告)号：US5930270A
公开(公告)日：1999-07-27
申请号：US898942
申请日：1997-07-23
申请人： Donato O. Forlenza , Franco Motika , John J. Shushereba , Phillip J. Nigh
发明人： Donato O. Forlenza , Franco Motika , John J. Shushereba , Phillip J. Nigh
IPC分类号： G01R31/3177 , G01R31/3185 , G06F11/22 , G01R31/28 , G06F11/00
CPC分类号： G06F11/2268 , G01R31/3177 , G01R31/318566 , G01R31/31816
摘要： A system and method for diagnosing the faults of an electronic device by running a series of tests, identifying the tests where the electronic device failed, without having to check the results of each test, storing information generated during only the tests where the electronic device failed, and using the information to diagnose the faults in the electronic device. The test results are accumulated into a Multiple Input Shift Register (MISR) which need not be examined after each test to determine which tests the device failed. The problem of a failure during one test manifesting into the MISR during subsequent tests is handled by predicting the effect of the failure on the MISR during subsequent tests.
摘要翻译：一种用于通过运行一系列测试来识别电子设备失败的测试的电子设备的故障的系统和方法，而不必检查每个测试的结果，仅存储在电子设备失败的测试期间产生的信息，并使用该信息来诊断电子设备中的故障。测试结果累积到多输入移位寄存器（MISR）中，每次测试后不需要检查，以确定器件出现哪些测试失败。在后续测试期间在一次测试中出现故障的问题是通过在随后的测试期间预测故障对MISR的影响来处理的。

2. 发明授权

US4696005A Apparatus for reducing test data storage requirements for high speed VLSI circuit testing 失效
标题翻译：用于降低高速VLSI电路测试的测试数据存储要求的设备
公开(公告)号：US4696005A
公开(公告)日：1987-09-22
申请号：US740592
申请日：1985-06-03
申请人： Ernest H. Millham , John J. Moser , John J. Shushereba , Gary P. Visco
发明人： Ernest H. Millham , John J. Moser , John J. Shushereba , Gary P. Visco
IPC分类号： G06F11/22 , G01R31/319 , G01R31/28
CPC分类号： G01R31/31921 , G01R31/31908
摘要： Apparatus for applying for a plurality of test cycles data specifying a plurality of test conditions to a multiple pin electronic circuit. A random access memory includes at a plurality of higher order addresses a complete data field for a plurality of test cycles. Some of said data fields include an operational code indicating that a minority of data bits in a field are to change in a consecutive number of following test cycles. A hold register is connected to receive each addressed row of test data from the memory. The higher order addresses of a memory addressed to produce complete data fields in the hold register. An operational code will be decoded to indicate a number of subsequent consecutive test cycles where a minority of data in the hold register are to be changed. The lower order addresses of the memory are subsequently addressed for a number of consecutive test cycles indicated by the operational code. The data contained in the lower order memory addresses is inserted in the hold register without changing the contents of a majority of hold register data bits.
摘要翻译：用于将指定多个测试条件的数据应用于多个引脚电子电路的装置。随机存取存储器在多个较高地址处包括用于多个测试周期的完整数据字段。所述数据字段中的一些包括一个操作代码，指示字段中的少数数据位将在连续数量的后续测试周期中改变。连接保持寄存器以从存储器接收每个寻址的测试数据行。用于在保持寄存器中产生完整数据字段的存储器的高阶地址。操作代码将被解码以指示随后的连续测试周期的数量，其中保持寄存器中的少数数据将被改变。随后，由操作代码指示的多个连续的测试周期来寻址存储器的低阶地址。包含在低位存储器地址中的数据被插入到保持寄存器中，而不改变大多数保持寄存器数据位的内容。

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