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1. 发明授权

US6090685A Method of forming a LOCOS trench isolation structure 失效
标题翻译：形成LOCOS沟槽隔离结构的方法
公开(公告)号：US6090685A
公开(公告)日：2000-07-18
申请号：US916475
申请日：1997-08-22
申请人： Fernando Gonzales , Mike Violette , Nanseng Jeng , Aftab Ahmad , Klaus Schuegraf
发明人： Fernando Gonzales , Mike Violette , Nanseng Jeng , Aftab Ahmad , Klaus Schuegraf
IPC分类号： H01L21/762 , H01L21/76
CPC分类号： H01L21/76202 , H01L21/76221 , Y10S148/05
摘要： A semiconductor structure pad oxide layer is enlarged by local oxidation of silicon to form a field oxide. An etchback causes the thinnest portions of the field oxide to recede such that a portion of the semiconductor substrate is exposed. An etch through the exposed portion of the semiconductor substrate forms a microtrench between the field oxide and the nitride layer with a lateral dimension that is less than that currently achievable by conventional photolithography. The microtrench is then filled by oxide or nitride growth or by deposition of a dielectric material. In another embodiment, formation of the microtrench is carried out as set forth above, but the nitride layer is removed immediately following trench formation. Alternatively, the pad oxide layer is stripped and a new oxide layer is regrown that substantially covers all exposed surfaces of active areas of the semiconductor substrate. The regrown oxide layer will encroach into all exposed surfaces of active areas and will grow also in the microtrench. Alternatively, the pad oxide layer is etched substantially uniformly at regions distant from nitride layer, whereas the etchant concentrates the etch against the nitride layer such that etching is accelerated at this location. Because of accelerated etching at this location, a breach in the pad oxide layer forms before etching of the pad oxide layer has been generally penetrated. The breach has a width of sub-photolithographic limits preparatory to formation of a microtrench thereunder.
摘要翻译：通过硅的局部氧化来扩大半导体结构衬垫氧化物层以形成场氧化物。回蚀使场氧化物的最薄部分后退，使得半导体衬底的一部分露出。通过半导体衬底的暴露部分的蚀刻在场氧化物和氮化物层之间形成微切口，其横向尺寸小于通过常规光刻法目前可实现的横向尺寸。然后通过氧化物或氮化物生长或通过沉积电介质材料来填充微切口。在另一个实施例中，微沟槽的形成如上所述进行，但是在形成沟槽之后立即去除氮化物层。或者，剥除焊盘氧化物层，并重新生长新的氧化物层，其基本上覆盖半导体衬底的有源区域的所有暴露表面。再生的氧化物层将侵蚀到活性区域的所有暴露表面，并且还将在微型扳手中生长。或者，在远离氮化物层的区域处基本上均匀地蚀刻焊盘氧化物层，而蚀刻剂将蚀刻集中到氮化物层上，使得在该位置加速蚀刻。由于在该位置处的加速蚀刻，在氧化垫层的蚀刻之前形成的衬垫氧化物层中的破裂已经被普遍渗透。该破裂具有准备在其下形成微型切割器的副光刻极限的宽度。

2. 发明授权

US06809395B1 Isolation structure having trench structures formed on both side of a locos 失效
标题翻译：具有形成在位置的两侧的沟槽结构的隔离结构
公开(公告)号：US06809395B1
公开(公告)日：2004-10-26
申请号：US09369579
申请日：1999-08-06
申请人： Fernando Gonzales , Mike Violette , Nanseng Jeng , Aftab Ahmad , Klaus Schuegraf
发明人： Fernando Gonzales , Mike Violette , Nanseng Jeng , Aftab Ahmad , Klaus Schuegraf
IPC分类号： H01L2900
CPC分类号： H01L21/76202 , H01L21/76221 , Y10S148/05
摘要： A semiconductor structure pad oxide layer is enlarged by local oxidation of silicon to form a field oxide. An etchback causes the thinnest portions of the field oxide to recede such that a portion of the semiconductor substrate is exposed. An etch through the exposed portion of the semiconductor substrate forms a microtrench between the field oxide and the nitride layer with a lateral dimension that is less than that currently achievable by conventional photolithography. The microtrench is then filled by oxide or nitride growth or by deposition of a dielectric material. In another embodiment, formation of the microtrench is carried out as set forth above, but the nitride layer is removed immediately following trench formation. Alternatively, the pad oxide layer is stripped and a new oxide layer is regrown that substantially covers all exposed surfaces of active areas of the semiconductor substrate. The regrown oxide layer will encroach into all exposed surfaces of active areas and will grow also in the microtrench. Alternatively, the pad oxide layer is etched substantially uniformly at regions distant from nitride layer, whereas the etchant concentrates the etch against the nitride layer such that etching is accelerated at this location. Because of accelerated etching at this location, a breach in the pad oxide layer forms before etching of the pad oxide layer has been generally penetrated. The breach has a width of sub-photolithographic limits preparatory to formation of a microtrench thereunder.
摘要翻译：通过硅的局部氧化来扩大半导体结构衬垫氧化物层以形成场氧化物。回蚀使场氧化物的最薄部分后退，使得半导体衬底的一部分露出。通过半导体衬底的暴露部分的蚀刻在场氧化物和氮化物层之间形成微切口，其横向尺寸小于通过常规光刻法目前可实现的横向尺寸。然后通过氧化物或氮化物生长或通过沉积电介质材料来填充微切口。在另一个实施例中，微沟槽的形成如上所述进行，但是在形成沟槽之后立即去除氮化物层。或者，剥除焊盘氧化物层，并重新生长新的氧化物层，其基本上覆盖半导体衬底的有源区域的所有暴露表面。再生的氧化物层将侵蚀到活性区域的所有暴露表面，并且还将在微型扳手中生长。或者，在远离氮化物层的区域处基本上均匀地蚀刻焊盘氧化物层，而蚀刻剂将蚀刻集中到氮化物层上，使得在该位置加速蚀刻。由于在该位置处的加速蚀刻，在氧化垫层的蚀刻之前形成的衬垫氧化物层中的破裂已经被普遍渗透。该破裂具有准备在其下形成微型切割器的副光刻极限的宽度。

3. 发明申请

US20050012158A1 Locos trench isolation structure 审中-公开
标题翻译： Locos沟槽隔离结构
公开(公告)号：US20050012158A1
公开(公告)日：2005-01-20
申请号：US10899609
申请日：2004-07-27
申请人： Fernando Gonzalez , Mike Violette , Nanseng Jeng , Aftab Ahmad , Klaus Schuegraf
发明人： Fernando Gonzalez , Mike Violette , Nanseng Jeng , Aftab Ahmad , Klaus Schuegraf
IPC分类号： H01L21/762 , H01L29/76
CPC分类号： H01L21/76202 , H01L21/76221 , Y10S148/05
摘要： A semiconductor structure pad oxide layer is enlarged by local oxidation of silicon to form a field oxide. An etchback causes the thinnest portions of the field oxide to recede such that a portion of the semiconductor substrate is exposed. An etch through the exposed portion of the semiconductor substrate forms a microtrench between the field oxide and the nitride layer with a lateral dimension that is less than that currently achievable by conventional photolithography. The microtrench is then filled by oxide or nitride growth or by deposition of a dielectric material. In another embodiment, formation of the microtrench is carried out as set forth above, but the nitride layer is removed immediately following trench formation. Alternatively, the pad oxide layer is stripped and a new oxide layer is regrown that substantially covers all exposed surfaces of active areas of the semiconductor substrate. The regrown oxide layer will encroach into all exposed surfaces of active areas and will grow also in the microtrench. Alternatively, the pad oxide layer is etched substantially uniformly at regions distant from nitride layer, whereas the etchant concentrates the etch against the nitride layer such that etching is accelerated at this location. Because of accelerated etching at this location, a breach in the pad oxide layer forms before etching of the pad oxide layer has been generally penetrated. The breach has a width of sub-photolithographic limits preparatory to formation of a microtrench thereunder.
摘要翻译：通过硅的局部氧化来扩大半导体结构衬垫氧化物层以形成场氧化物。回蚀使场氧化物的最薄部分后退，使得半导体衬底的一部分露出。通过半导体衬底的暴露部分的蚀刻在场氧化物和氮化物层之间形成微切口，其横向尺寸小于通过常规光刻法目前可实现的横向尺寸。然后通过氧化物或氮化物生长或通过沉积电介质材料来填充微切口。在另一个实施例中，微沟槽的形成如上所述进行，但是在形成沟槽之后立即去除氮化物层。或者，剥除焊盘氧化物层，并重新生长新的氧化物层，其基本上覆盖半导体衬底的有源区域的所有暴露表面。再生的氧化物层将侵蚀到活性区域的所有暴露表面，并且还将在微型扳手中生长。或者，在远离氮化物层的区域处基本上均匀地蚀刻焊盘氧化物层，而蚀刻剂将蚀刻集中到氮化物层上，使得在该位置加速蚀刻。由于在该位置处的加速蚀刻，在氧化垫层的蚀刻之前形成的衬垫氧化物层中的破裂已经被普遍渗透。该破裂具有准备在其下形成微型切割器的副光刻极限的宽度。

4. 发明申请

US20060231902A1 LOCOS trench isolation structures 审中-公开
标题翻译： LOCOS沟槽隔离结构
公开(公告)号：US20060231902A1
公开(公告)日：2006-10-19
申请号：US11452574
申请日：2006-06-14
申请人： Fernando Gonzalez , Mike Violette , Nanseng Jeng , Aftab Ahmad , Klaus Schuegraf
发明人： Fernando Gonzalez , Mike Violette , Nanseng Jeng , Aftab Ahmad , Klaus Schuegraf
IPC分类号： H01L29/76
CPC分类号： H01L21/76202 , H01L21/76221 , Y10S148/05
摘要： Isolation structures having trenches formed on both sides of a LOCOS structure are disclosed. A semiconductor structure pad oxide layer is enlarged by local oxidation of silicon to form a field oxide. An etchback causes the thinnest portions of the field oxide to recede, such that a portion of the semiconductor substrate is exposed. An etch, through the exposed portion of the semiconductor substrate, forms a microtrench between the field oxide and the nitride layer with a lateral dimension that is less than that currently achievable by conventional photolithography. In another embodiment, formation of the microtrench is carried out as set forth above, but the nitride layer is immediately removed following trench formation. Alternatively, the pad oxide layer is stripped and a new oxide layer is regrown that substantially covers all exposed surfaces of active areas of the semiconductor substrate.
摘要翻译：公开了在LOCOS结构的两侧形成有沟槽的隔离结构。通过硅的局部氧化来扩大半导体结构衬垫氧化物层以形成场氧化物。回蚀使场氧化物的最薄部分后退，使得半导体衬底的一部分露出。通过半导体衬底的暴露部分的蚀刻在场氧化物和氮化物层之间形成小尺寸，其横向尺寸小于目前可通过常规光刻法实现的尺寸。在另一个实施例中，如上所述进行微切口的形成，但是在形成沟槽之后立即去除氮化物层。或者，剥除焊盘氧化物层，并重新生长新的氧化物层，其基本上覆盖半导体衬底的有源区域的所有暴露表面。

5. 发明申请

US20050087833A1 Shallow trench isolation using low dielectric constant insulator 有权
标题翻译：使用低介电常数绝缘子的浅沟槽隔离
公开(公告)号：US20050087833A1
公开(公告)日：2005-04-28
申请号：US11012012
申请日：2004-12-13
申请人： Klaus Schuegraf , Aftab Ahmad
发明人： Klaus Schuegraf , Aftab Ahmad
IPC分类号： H01L21/762 , H01L29/00
CPC分类号： H01L21/76224 , Y10S148/05
摘要： A shallow trench isolation is disclosed wherein the trench depth is reduced beyond that achieved in prior art processes. The reduced trench depth helps to eliminate the formation of voids during the trench refill process and provides for greater planarity in the final isolation structure. Effective device isolation is achieved with a reduced trench depth by utilizing refilling dielectric materials having low dielectric constant.
摘要翻译：公开了一种浅沟槽隔离，其中沟槽深度减小到超过现有技术工艺中所达到的深度。减小的沟槽深度有助于在沟槽再填充过程期间消除空隙的形成，并且在最终隔离结构中提供更大的平坦度。通过利用具有低介电常数的再填充介电材料，通过减小沟槽深度实现有效的器件隔离。

6. 发明申请

US20100321977A1 PROGRAMMING REVERSIBLE RESISTANCE SWITCHING ELEMENTS 有权
标题翻译：编程可逆电阻开关元件
公开(公告)号：US20100321977A1
公开(公告)日：2010-12-23
申请号：US12488159
申请日：2009-06-19
申请人： Deepak C. Sekar , Klaus Schuegraf , Roy Scheuerlein
发明人： Deepak C. Sekar , Klaus Schuegraf , Roy Scheuerlein
IPC分类号： G11C11/00 , G11C8/08 , G11C8/00
CPC分类号： G11C13/0007 , G11C7/00 , G11C8/12 , G11C13/0064 , G11C13/0069 , G11C2013/0076 , G11C2013/0088 , G11C2013/009 , G11C2213/32 , G11C2213/34 , G11C2213/72
摘要： A storage system and method for operating the storage system that uses reversible resistance-switching elements is described. Techniques are disclosed herein for varying programming conditions to account for different resistances that memory cells have. These techniques can program memory cells in fewer attempts, which can save time and/or power. Techniques are disclosed herein for achieving a high programming bandwidth while reducing the worst case current and/or power consumption. In one embodiment, a page mapping scheme is provided that programs multiple memory cells in parallel in a way that reduces the worst case current and/or power consumption.
摘要翻译：描述了一种用于操作使用可逆电阻切换元件的存储系统的存储系统和方法。本文公开了用于改变编程条件以解决存储器单元具有的不同电阻的技术。这些技术可以以较少的尝试编程存储器单元，这可以节省时间和/或功率。本文公开了用于实现高编程带宽同时减少最坏情况下的电流和/或功率消耗的技术。在一个实施例中，提供了以减少最坏情况下的电流和/或功率消耗的方式并行地编程多个存储器单元的页面映射方案。

7. 发明授权

US5211995A Method of protecting an organic surface by deposition of an inorganic refractory coating thereon 失效
$Method of protecting an organic surface by deposition of an inorganic refractory coating thereon$
标题翻译：通过在其上沉积无机耐火涂层来保护有机表面的方法
公开(公告)号：US5211995A
公开(公告)日：1993-05-18
申请号：US768159
申请日：1991-09-30
申请人： Manfred R. Kuehnle , Arno K. Hagenlocher , Klaus Schuegraf
发明人： Manfred R. Kuehnle , Arno K. Hagenlocher , Klaus Schuegraf
IPC分类号： B05D5/00 , B05D7/16 , B05D7/24 , C23C16/50
CPC分类号： C23C16/50 , B05D5/00 , B05D7/16 , B05D7/24
摘要： Transparent, refractory coatings and methods for their application to environmentally exposed substrates are disclosed. The coatings can be deposited over organic decorative materials, which generally prevent application of hard, protective, inorganic materials due to emission of exudates and vulnerability to excessive heat. The coatings are applied using plasma-enhanced chemical-vapor deposition techniques that reduce reaction temperatures and produce multilayer structures that seal organic exudates before a final layer of coating is applied, such multilayer protective coating structures being particularly suitable for protecting automobile bodies and the like against degrading external forces.
摘要翻译：公开了透明耐火涂料及其应用于环境暴露的基材的方法。涂层可以沉积在有机装饰材料上，这通常防止由于渗出物的排放和易于过热而施加硬的，保护性的无机材料。使用等离子体增强化学气相沉积技术涂覆涂层，其降低反应温度并产生在施加最终涂层之前密封有机渗出物的多层结构，这种多层保护涂层结构特别适合于保护汽车车身等降低外部力量

8. 发明授权

US08994089B2 Interlayer polysilicon dielectric cap and method of forming thereof 有权
标题翻译：层间多晶硅电介质盖及其形成方法
公开(公告)号：US08994089B2
公开(公告)日：2015-03-31
申请号：US13294608
申请日：2011-11-11
申请人： Matthew S. Rogers , Klaus Schuegraf
发明人： Matthew S. Rogers , Klaus Schuegraf
IPC分类号： H01L29/788 , H01L21/28 , H01L27/115 , H01L21/67
CPC分类号： H01L21/28273 , H01L21/67167 , H01L27/11521
摘要： In some embodiments, an interlayer polysilicon dielectric cap disposed atop a substrate having a first floating gate, a second floating gate and an isolation layer disposed between the first floating gate and the second floating gate may include: a first nitrogen containing layer disposed atop an upper portion and sidewalls of the first floating gate and second floating gate; a first oxygen containing layer disposed atop the first nitrogen containing layer and an upper surface of the isolation layer; a second nitrogen containing layer disposed atop an upper portion and sidewalls of the first oxygen containing layer; and a second oxygen containing layer disposed atop the second nitrogen containing layer and an upper surface of the first oxygen containing layer.
摘要翻译：在一些实施例中，设置在具有第一浮动栅极，第二浮动栅极和设置在第一浮动栅极和第二浮动栅极之间的隔离层的衬底顶部的层间多晶硅介电体盖可以包括：设置在上部第一浮栅和第二浮栅的部分和侧壁; 设置在第一含氮层顶部和隔离层的上表面上的第一含氧层; 设置在第一含氧层的上部和侧壁顶部的第二含氮层; 以及设置在第二含氮层顶部和第一含氧层的上表面上的第二含氧层。

9. 发明申请

US20130045570A1 METHOD AND SYSTEM FOR WAFER LEVEL SINGULATION 失效
标题翻译：用于水平层叠的方法和系统
公开(公告)号：US20130045570A1
公开(公告)日：2013-02-21
申请号：US13399638
申请日：2012-02-17
申请人： Klaus Schuegraf , Seshadri Ramaswami , Michael R. Rice , Mohsen S. Salek , Claes H. Bjorkman
发明人： Klaus Schuegraf , Seshadri Ramaswami , Michael R. Rice , Mohsen S. Salek , Claes H. Bjorkman
IPC分类号： H01L21/78
CPC分类号： H01L21/78 , H01L21/02076 , H01L21/30 , H01L21/302 , H01L21/308 , H01L21/561 , H01L21/568 , H01L21/67017 , H01L21/67207 , H01L21/6836 , H01L23/544 , H01L24/94 , H01L2221/68327 , H01L2924/0002 , H01L2924/12042 , H01L2924/00
摘要： A method of singulating a plurality of semiconductor dies includes providing a carrier substrate and joining a semiconductor substrate to the carrier substrate. The semiconductor substrate includes a plurality of devices. The method also includes forming a mask layer on the semiconductor substrate, exposing a predetermined portion of the mask layer to light, and processing the predetermined portion of the mask layer to form a predetermined mask pattern on the semiconductor substrate. The method further includes forming the plurality of semiconductor dies, each of the plurality of semiconductor dies being associated with the predetermined mask pattern and including one or more of the plurality of devices and separating the plurality of semiconductor dies from the carrier substrate.
摘要翻译：单片化多个半导体管芯的方法包括提供载体衬底并将半导体衬底接合到载体衬底。半导体衬底包括多个器件。该方法还包括在半导体衬底上形成掩模层，将掩模层的预定部分暴露于光，以及处理掩模层的预定部分以在半导体衬底上形成预定的掩模图案。所述方法还包括形成所述多个半导体管芯，所述多个半导体管芯中的每一个与所述预定掩模图案相关联并且包括所述多个器件中的一个或多个并且将所述多个半导体管芯与所述载体衬底分离。

10. 发明授权

US07876620B2 Read disturb mitigation in non-volatile memory 有权
标题翻译：在非易失性存储器中读取干扰减轻
公开(公告)号：US07876620B2
公开(公告)日：2011-01-25
申请号：US12832822
申请日：2010-07-08
申请人： Nima Mokhlesi , Klaus Schuegraf
发明人： Nima Mokhlesi , Klaus Schuegraf
IPC分类号： G11C16/06
CPC分类号： G11C11/5642 , G11C16/3418 , G11C16/3427 , G11C29/00
摘要： Read disturb is reduced in non-volatile storage. In one aspect, when a read command is received from a host for reading a selected word line, a word line which is not selected for reading is randomly chosen and its storage elements are sensed to determine optimized read compare levels for reading the selected word line. Or, a refresh operation may be indicated for the entire block based on an error correction metric obtained in reading the storage elements of the chosen word line. This is useful especially when the selected word line is repeatedly selected for reading, exposing the other word lines to additional read disturb. In another aspect, when multiple data states are stored, one read compare level is obtained from sensing, e.g., from a threshold voltage distribution, and other read compare levels are derived from a formula.
摘要翻译：非易失性存储器中的读取干扰减少。在一个方面，当从主机接收到用于读取所选择的字线的读取命令时，随机选择未被选择用于读取的字线，并且感测其存储元件以确定用于读取所选字线的优化读取比较电平。或者，可以基于在读取所选字线的存储元件中获得的纠错度量，针对整个块指示刷新操作。特别是当所选字线被重复选择用于读取时，这是有用的，将其它字线暴露于额外的读取干扰。在另一方面，当存储多个数据状态时，通过例如来自阈值电压分布的感测获得一个读取比较电平，并且从公式导出其它读取的比较电平。

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