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1. 发明授权

US6090685A Method of forming a LOCOS trench isolation structure 失效
标题翻译：形成LOCOS沟槽隔离结构的方法
公开(公告)号：US6090685A
公开(公告)日：2000-07-18
申请号：US916475
申请日：1997-08-22
申请人： Fernando Gonzales , Mike Violette , Nanseng Jeng , Aftab Ahmad , Klaus Schuegraf
发明人： Fernando Gonzales , Mike Violette , Nanseng Jeng , Aftab Ahmad , Klaus Schuegraf
IPC分类号： H01L21/762 , H01L21/76
CPC分类号： H01L21/76202 , H01L21/76221 , Y10S148/05
摘要： A semiconductor structure pad oxide layer is enlarged by local oxidation of silicon to form a field oxide. An etchback causes the thinnest portions of the field oxide to recede such that a portion of the semiconductor substrate is exposed. An etch through the exposed portion of the semiconductor substrate forms a microtrench between the field oxide and the nitride layer with a lateral dimension that is less than that currently achievable by conventional photolithography. The microtrench is then filled by oxide or nitride growth or by deposition of a dielectric material. In another embodiment, formation of the microtrench is carried out as set forth above, but the nitride layer is removed immediately following trench formation. Alternatively, the pad oxide layer is stripped and a new oxide layer is regrown that substantially covers all exposed surfaces of active areas of the semiconductor substrate. The regrown oxide layer will encroach into all exposed surfaces of active areas and will grow also in the microtrench. Alternatively, the pad oxide layer is etched substantially uniformly at regions distant from nitride layer, whereas the etchant concentrates the etch against the nitride layer such that etching is accelerated at this location. Because of accelerated etching at this location, a breach in the pad oxide layer forms before etching of the pad oxide layer has been generally penetrated. The breach has a width of sub-photolithographic limits preparatory to formation of a microtrench thereunder.
摘要翻译：通过硅的局部氧化来扩大半导体结构衬垫氧化物层以形成场氧化物。回蚀使场氧化物的最薄部分后退，使得半导体衬底的一部分露出。通过半导体衬底的暴露部分的蚀刻在场氧化物和氮化物层之间形成微切口，其横向尺寸小于通过常规光刻法目前可实现的横向尺寸。然后通过氧化物或氮化物生长或通过沉积电介质材料来填充微切口。在另一个实施例中，微沟槽的形成如上所述进行，但是在形成沟槽之后立即去除氮化物层。或者，剥除焊盘氧化物层，并重新生长新的氧化物层，其基本上覆盖半导体衬底的有源区域的所有暴露表面。再生的氧化物层将侵蚀到活性区域的所有暴露表面，并且还将在微型扳手中生长。或者，在远离氮化物层的区域处基本上均匀地蚀刻焊盘氧化物层，而蚀刻剂将蚀刻集中到氮化物层上，使得在该位置加速蚀刻。由于在该位置处的加速蚀刻，在氧化垫层的蚀刻之前形成的衬垫氧化物层中的破裂已经被普遍渗透。该破裂具有准备在其下形成微型切割器的副光刻极限的宽度。

2. 发明授权

US06809395B1 Isolation structure having trench structures formed on both side of a locos 失效
标题翻译：具有形成在位置的两侧的沟槽结构的隔离结构
公开(公告)号：US06809395B1
公开(公告)日：2004-10-26
申请号：US09369579
申请日：1999-08-06
申请人： Fernando Gonzales , Mike Violette , Nanseng Jeng , Aftab Ahmad , Klaus Schuegraf
发明人： Fernando Gonzales , Mike Violette , Nanseng Jeng , Aftab Ahmad , Klaus Schuegraf
IPC分类号： H01L2900
CPC分类号： H01L21/76202 , H01L21/76221 , Y10S148/05
摘要： A semiconductor structure pad oxide layer is enlarged by local oxidation of silicon to form a field oxide. An etchback causes the thinnest portions of the field oxide to recede such that a portion of the semiconductor substrate is exposed. An etch through the exposed portion of the semiconductor substrate forms a microtrench between the field oxide and the nitride layer with a lateral dimension that is less than that currently achievable by conventional photolithography. The microtrench is then filled by oxide or nitride growth or by deposition of a dielectric material. In another embodiment, formation of the microtrench is carried out as set forth above, but the nitride layer is removed immediately following trench formation. Alternatively, the pad oxide layer is stripped and a new oxide layer is regrown that substantially covers all exposed surfaces of active areas of the semiconductor substrate. The regrown oxide layer will encroach into all exposed surfaces of active areas and will grow also in the microtrench. Alternatively, the pad oxide layer is etched substantially uniformly at regions distant from nitride layer, whereas the etchant concentrates the etch against the nitride layer such that etching is accelerated at this location. Because of accelerated etching at this location, a breach in the pad oxide layer forms before etching of the pad oxide layer has been generally penetrated. The breach has a width of sub-photolithographic limits preparatory to formation of a microtrench thereunder.
摘要翻译：通过硅的局部氧化来扩大半导体结构衬垫氧化物层以形成场氧化物。回蚀使场氧化物的最薄部分后退，使得半导体衬底的一部分露出。通过半导体衬底的暴露部分的蚀刻在场氧化物和氮化物层之间形成微切口，其横向尺寸小于通过常规光刻法目前可实现的横向尺寸。然后通过氧化物或氮化物生长或通过沉积电介质材料来填充微切口。在另一个实施例中，微沟槽的形成如上所述进行，但是在形成沟槽之后立即去除氮化物层。或者，剥除焊盘氧化物层，并重新生长新的氧化物层，其基本上覆盖半导体衬底的有源区域的所有暴露表面。再生的氧化物层将侵蚀到活性区域的所有暴露表面，并且还将在微型扳手中生长。或者，在远离氮化物层的区域处基本上均匀地蚀刻焊盘氧化物层，而蚀刻剂将蚀刻集中到氮化物层上，使得在该位置加速蚀刻。由于在该位置处的加速蚀刻，在氧化垫层的蚀刻之前形成的衬垫氧化物层中的破裂已经被普遍渗透。该破裂具有准备在其下形成微型切割器的副光刻极限的宽度。

3. 发明申请

US20050012158A1 Locos trench isolation structure 审中-公开
标题翻译： Locos沟槽隔离结构
公开(公告)号：US20050012158A1
公开(公告)日：2005-01-20
申请号：US10899609
申请日：2004-07-27
申请人： Fernando Gonzalez , Mike Violette , Nanseng Jeng , Aftab Ahmad , Klaus Schuegraf
发明人： Fernando Gonzalez , Mike Violette , Nanseng Jeng , Aftab Ahmad , Klaus Schuegraf
IPC分类号： H01L21/762 , H01L29/76
CPC分类号： H01L21/76202 , H01L21/76221 , Y10S148/05
摘要： A semiconductor structure pad oxide layer is enlarged by local oxidation of silicon to form a field oxide. An etchback causes the thinnest portions of the field oxide to recede such that a portion of the semiconductor substrate is exposed. An etch through the exposed portion of the semiconductor substrate forms a microtrench between the field oxide and the nitride layer with a lateral dimension that is less than that currently achievable by conventional photolithography. The microtrench is then filled by oxide or nitride growth or by deposition of a dielectric material. In another embodiment, formation of the microtrench is carried out as set forth above, but the nitride layer is removed immediately following trench formation. Alternatively, the pad oxide layer is stripped and a new oxide layer is regrown that substantially covers all exposed surfaces of active areas of the semiconductor substrate. The regrown oxide layer will encroach into all exposed surfaces of active areas and will grow also in the microtrench. Alternatively, the pad oxide layer is etched substantially uniformly at regions distant from nitride layer, whereas the etchant concentrates the etch against the nitride layer such that etching is accelerated at this location. Because of accelerated etching at this location, a breach in the pad oxide layer forms before etching of the pad oxide layer has been generally penetrated. The breach has a width of sub-photolithographic limits preparatory to formation of a microtrench thereunder.
摘要翻译：通过硅的局部氧化来扩大半导体结构衬垫氧化物层以形成场氧化物。回蚀使场氧化物的最薄部分后退，使得半导体衬底的一部分露出。通过半导体衬底的暴露部分的蚀刻在场氧化物和氮化物层之间形成微切口，其横向尺寸小于通过常规光刻法目前可实现的横向尺寸。然后通过氧化物或氮化物生长或通过沉积电介质材料来填充微切口。在另一个实施例中，微沟槽的形成如上所述进行，但是在形成沟槽之后立即去除氮化物层。或者，剥除焊盘氧化物层，并重新生长新的氧化物层，其基本上覆盖半导体衬底的有源区域的所有暴露表面。再生的氧化物层将侵蚀到活性区域的所有暴露表面，并且还将在微型扳手中生长。或者，在远离氮化物层的区域处基本上均匀地蚀刻焊盘氧化物层，而蚀刻剂将蚀刻集中到氮化物层上，使得在该位置加速蚀刻。由于在该位置处的加速蚀刻，在氧化垫层的蚀刻之前形成的衬垫氧化物层中的破裂已经被普遍渗透。该破裂具有准备在其下形成微型切割器的副光刻极限的宽度。

4. 发明申请

US20060231902A1 LOCOS trench isolation structures 审中-公开
标题翻译： LOCOS沟槽隔离结构
公开(公告)号：US20060231902A1
公开(公告)日：2006-10-19
申请号：US11452574
申请日：2006-06-14
申请人： Fernando Gonzalez , Mike Violette , Nanseng Jeng , Aftab Ahmad , Klaus Schuegraf
发明人： Fernando Gonzalez , Mike Violette , Nanseng Jeng , Aftab Ahmad , Klaus Schuegraf
IPC分类号： H01L29/76
CPC分类号： H01L21/76202 , H01L21/76221 , Y10S148/05
摘要： Isolation structures having trenches formed on both sides of a LOCOS structure are disclosed. A semiconductor structure pad oxide layer is enlarged by local oxidation of silicon to form a field oxide. An etchback causes the thinnest portions of the field oxide to recede, such that a portion of the semiconductor substrate is exposed. An etch, through the exposed portion of the semiconductor substrate, forms a microtrench between the field oxide and the nitride layer with a lateral dimension that is less than that currently achievable by conventional photolithography. In another embodiment, formation of the microtrench is carried out as set forth above, but the nitride layer is immediately removed following trench formation. Alternatively, the pad oxide layer is stripped and a new oxide layer is regrown that substantially covers all exposed surfaces of active areas of the semiconductor substrate.
摘要翻译：公开了在LOCOS结构的两侧形成有沟槽的隔离结构。通过硅的局部氧化来扩大半导体结构衬垫氧化物层以形成场氧化物。回蚀使场氧化物的最薄部分后退，使得半导体衬底的一部分露出。通过半导体衬底的暴露部分的蚀刻在场氧化物和氮化物层之间形成小尺寸，其横向尺寸小于目前可通过常规光刻法实现的尺寸。在另一个实施例中，如上所述进行微切口的形成，但是在形成沟槽之后立即去除氮化物层。或者，剥除焊盘氧化物层，并重新生长新的氧化物层，其基本上覆盖半导体衬底的有源区域的所有暴露表面。

5. 发明申请

US20050017312A1 Barrier in gate stack for improved gate dielectric integrity 失效
公开(公告)号：US20050017312A1
公开(公告)日：2005-01-27
申请号：US10901552
申请日：2004-07-27
申请人： Nanseng Jeng , Aftab Ahmad
发明人： Nanseng Jeng , Aftab Ahmad
IPC分类号： H01L21/28 , H01L21/8234 , H01L29/49 , H01L29/76
CPC分类号： H01L29/4941 , H01L21/28061 , H01L21/823437
摘要： A barrier layer comprising silicon mixed with an impurity is disclosed for protection of gate dielectrics in integrated transistors. In particular, the barrier layer comprises silicon incorporating nitrogen. The nitrogen can be incorporated into an upper portion of the gate polysilicon during deposition, or a silicon layer doped with nitrogen after silicon deposition. The layer is of particular utility in conjunction with CVD tungsten silicide straps.

6. 发明授权

US06930363B2 Barrier in gate stack for improved gate dielectric integrity 失效
标题翻译：栅极堆叠中的栅极，用于改善栅极电介质完整性
公开(公告)号：US06930363B2
公开(公告)日：2005-08-16
申请号：US10901552
申请日：2004-07-27
申请人： Nanseng Jeng , Aftab Ahmad
发明人： Nanseng Jeng , Aftab Ahmad
IPC分类号： H01L21/28 , H01L21/8234 , H01L29/49 , H01L29/94
CPC分类号： H01L29/4941 , H01L21/28061 , H01L21/823437
摘要： A barrier layer comprising silicon mixed with an impurity is disclosed for protection of gate dielectrics in integrated transistors. In particular, the barrier layer comprises silicon incorporating nitrogen. The nitrogen can be incorporated into an upper portion of the gate polysilicon during deposition, or a silicon layer doped with nitrogen after silicon deposition. The layer is of particular utility in conjunction with CVD tungsten silicide straps.
摘要翻译：公开了包含与杂质混合的硅的阻挡层，用于保护集成晶体管中的栅极电介质。特别地，阻挡层包括掺入氮的硅。在沉积期间可以将氮结合到栅极多晶硅的上部，或在硅沉积之后掺入氮的硅层。该层与CVD钨硅化物带结合是特别实用的。

7. 发明授权

US06770571B2 Barrier in gate stack for improved gate dielectric integrity 有权
标题翻译：栅极堆叠中的栅极，用于改善栅极电介质完整性
公开(公告)号：US06770571B2
公开(公告)日：2004-08-03
申请号：US10339731
申请日：2003-01-08
申请人： Nanseng Jeng , Aftab Ahmad
发明人： Nanseng Jeng , Aftab Ahmad
IPC分类号： H01L2131
CPC分类号： H01L29/4941 , H01L21/28061 , H01L21/823437
摘要： A barrier layer comprising silicon mixed with an impurity is disclosed for protection of gate dielectrics in integrated transistors. In particular, the barrier layer comprises silicon incorporating nitrogen. The nitrogen can be incorporated into an upper portion of the gate polysilicon during deposition, or a silicon layer doped with nitrogen after silicon deposition. The layer is of particular utility in conjunction with CVD tungsten silicide straps.
摘要翻译：公开了包含与杂质混合的硅的阻挡层，用于保护集成晶体管中的栅极电介质。特别地，阻挡层包括掺入氮的硅。在沉积期间可以将氮结合到栅极多晶硅的上部，或在硅沉积之后掺入氮的硅层。该层与CVD钨硅化物带结合是特别实用的。

8. 发明授权

US06373114B1 Barrier in gate stack for improved gate dielectric integrity 有权
标题翻译：栅极堆叠中的栅极，用于改善栅极电介质完整性
公开(公告)号：US06373114B1
公开(公告)日：2002-04-16
申请号：US09178306
申请日：1998-10-23
申请人： Nanseng Jeng , Aftab Ahmad
发明人： Nanseng Jeng , Aftab Ahmad
IPC分类号： H01L2994
CPC分类号： H01L29/4941 , H01L21/28061 , H01L21/823437
摘要： A barrier layer comprising silicon mixed with an impurity is disclosed for protection of gate dielectrics in integrated transistors. In particular, the barrier layer comprises silicon incorporating nitrogen. The nitrogen can be incorporated into an upper portion of the gate polysilicon during deposition, or a silicon layer doped with nitrogen after silicon deposition. The layer is of particular utility in conjunction with CVD tungsten silicide straps.
摘要翻译：公开了包含与杂质混合的硅的阻挡层，用于保护集成晶体管中的栅极电介质。特别地，阻挡层包括掺入氮的硅。在沉积期间可以将氮结合到栅极多晶硅的上部，或在硅沉积之后掺入氮的硅层。该层与CVD钨硅化物带结合是特别实用的。

9. 发明授权

US6127096A Method for reducing photolithographic steps in a semiconductor interconnect process 有权
公开(公告)号：US6127096A
公开(公告)日：2000-10-03
申请号：US286285
申请日：1999-04-05
申请人： Nanseng Jeng , Christophe Pierrat
发明人： Nanseng Jeng , Christophe Pierrat
IPC分类号： G03F1/00 , G03F1/26 , G03F1/29 , G03F1/32 , G03F7/20 , H01L21/027 , H01L21/311 , H01L21/768
CPC分类号： G03F1/26 , G03F1/29 , G03F1/32 , G03F7/2022 , H01L21/0274 , H01L21/31144 , H01L21/76813 , H01L2221/1021
摘要： A semiconductor wafer having a first layer and overlying insulating layer receives a photoresist layer. A first photoresist area is exposed to light having a first dosage, while a second, adjacent photoresist area is concurrently exposed to light having a second dosage. The first area and second area then are concurrently developed to partially expose the photoresist layer. The partial exposure removes photoresist within the first area to one depth and within the second area to a second depth. The second depth differs from the first depth. In one embodiment, the second depth extends through the photoresist down to the insulating layer. After subsequently performing a contact and/or trench etch through the exposed insulating layer and removing excess photoresist above the insulating layer, conductive material is deposited in the contact/trench opening and over the insulating layer. The result is an upper conductive layer coupled to the first layer via a contact or other conductive connection.

10. 发明授权

US5972569A Method for reducing photolithographic steps in a semiconductor interconnect process 失效
标题翻译：减少半导体互连工艺中的光刻步骤的方法
公开(公告)号：US5972569A
公开(公告)日：1999-10-26
申请号：US946462
申请日：1997-10-07
申请人： Nanseng Jeng , Christophe Pierrat
发明人： Nanseng Jeng , Christophe Pierrat
IPC分类号： G03F1/00 , G03F1/26 , G03F1/29 , G03F1/32 , G03F7/20 , H01L21/027 , H01L21/311 , H01L21/768 , G03F7/26
CPC分类号： G03F1/26 , G03F1/29 , G03F1/32 , G03F7/2022 , H01L21/0274 , H01L21/31144 , H01L21/76813 , H01L2221/1021
摘要： A semiconductor wafer having a first layer and overlying insulating layer receives a photoresist layer. A first photoresist area is exposed to light having a first dosage, while a second, adjacent photoresist area is concurrently exposed to light having a second dosage. The first area and second area then are concurrently developed to partially expose the photoresist layer. The partial exposure removes photoresist within the first area to one depth and within the second area to a second depth. The second depth differs from the first depth. In one embodiment the second depth extends through the photoresist down to the insulating layer. After subsequently performing a contact and/or trench etch through the exposed insulating layer and removing excess photoresist above the insulating layer, conductive material is deposited in the contact/trench opening and over the insulating layer. The result is an upper conductive layer coupled to the first layer via a contact or other conductive connection.
摘要翻译：具有第一层和上覆绝缘层的半导体晶片接收光致抗蚀剂层。第一光致抗蚀剂区域暴露于具有第一剂量的光，而第二相邻的光致抗蚀剂区域同时暴露于具有第二剂量的光。然后同时开发第一区域和第二区域以部分地曝光光致抗蚀剂层。部分曝光将第一区域内的光致抗蚀剂移至一个深度并在第二区域内移至第二深度。第二深度与第一深度不同。在一个实施例中，第二深度延伸穿过光致抗蚀剂到达绝缘层。在随后通过暴露的绝缘层进行接触和/或沟槽蚀刻并且去除绝缘层之上的多余的光致抗蚀剂之后，导电材料沉积在接触/沟槽开口中并在绝缘层上方。结果是通过接触或其它导电连接耦合到第一层的上导电层。

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