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1. 发明授权

US06440825B1 Method of controlling outdiffusion in a doped three-dimensional film 有权
标题翻译：控制掺杂三维膜中扩散扩散的方法
公开(公告)号：US06440825B1
公开(公告)日：2002-08-27
申请号：US09616540
申请日：2000-07-14
申请人： Fernando González , D. Mark Durcan , Luan C. Tran , Robert B. Kerr , David F. Cheffings , Howard E. Rhodes
发明人： Fernando González , D. Mark Durcan , Luan C. Tran , Robert B. Kerr , David F. Cheffings , Howard E. Rhodes
IPC分类号： H01L2170
CPC分类号： H01L27/10852 , H01L28/82
摘要： A solid state fabrication technique for controlling the amount of outdiffusion from a three-dimensional film is comprised of the step of providing a first layer of insitu doped film in a manner to define an upper portion and a lower portion. A second layer of undoped film is provided on top of the first layer to similarly define an upper portion and a lower portion. The first and second layers are etched according to a predetermined pattern. The second layer is doped to obtain a desired dopant density which decreases from the upper portion to the lower portion. Outdiffusion of the dopant from the upper portion of the second layer results in the dopant migrating to the lower portion of the second layer. Thus, outdiffusion into the substrate, and the problems caused thereby, are eliminated or greatly reduced.
摘要翻译：用于控制来自三维膜的向外扩散量的固态制造技术包括以限定上部和下部的方式提供第一层原位掺杂膜的步骤。第二层未掺杂的膜设置在第一层的顶部上，以类似地限定上部和下部。根据预定图案蚀刻第一层和第二层。掺杂第二层以获得从上部向下部减小的期望的掺杂剂密度。从第二层的上部扩散掺杂剂导致掺杂剂迁移到第二层的下部。因此，消除或大大降低了向基板的扩散和由此引起的问题。

2. 发明授权

US5994182A Method of reducing outdiffusion from a doped three-dimensional polysilicon film into substrate by using angled implants 失效
标题翻译：通过使用倾斜植入物将掺杂的三维多晶硅膜扩散到衬底中的方法
公开(公告)号：US5994182A
公开(公告)日：1999-11-30
申请号：US587277
申请日：1996-01-18
申请人： Fernando Gonzalez , D. Mark Durcan , Luan C. Tran , Robert B. Kerr , David F. Cheffings , Howard E. Rhodes
发明人： Fernando Gonzalez , D. Mark Durcan , Luan C. Tran , Robert B. Kerr , David F. Cheffings , Howard E. Rhodes
IPC分类号： H01L21/02 , H01L21/8242 , H01L21/70 , H01L21/265
CPC分类号： H01L27/10852 , H01L28/82
摘要： A solid state fabrication technique for controlling the amount of outdiffusion from a three-dimensional film is comprised of the step of providing a first layer of insitu doped film in a manner to define an upper portion and a lower portion. A second layer of undoped film is provided on top of the first layer to similarly define an upper portion and a lower portion. The first and second layers are etched according to a predetermined pattern. The second layer is doped to obtain a desired dopant density which decreases from the upper portion to the lower portion. Outdiffusion of the dopant from the upper portion of the second layer results in the dopant migrating to the lower portion of the second layer. Thus, outdiffusion into the substrate, and the problems caused thereby, are eliminated or greatly reduced.
摘要翻译：用于控制来自三维膜的向外扩散量的固态制造技术包括以限定上部和下部的方式提供第一层原位掺杂膜的步骤。第二层未掺杂的膜设置在第一层的顶部上，以类似地限定上部和下部。根据预定图案蚀刻第一层和第二层。掺杂第二层以获得从上部向下部减小的期望的掺杂剂密度。从第二层的上部扩散掺杂剂导致掺杂剂迁移到第二层的下部。因此，消除或大大降低了向基板的扩散和由此引起的问题。

3. 发明授权

US6159790A Method of controlling outdiffusion in doped three-dimensional film by using angled implants 有权
标题翻译：通过使用倾斜植入物控制掺杂三维膜中的扩散扩散的方法
公开(公告)号：US6159790A
公开(公告)日：2000-12-12
申请号：US310489
申请日：1999-05-12
申请人： Fernando Gonzalez , D. Mark Durcan , Luan C. Tran , Robert B. Kerr , David F. Cheffings , Howard E. Rhodes
发明人： Fernando Gonzalez , D. Mark Durcan , Luan C. Tran , Robert B. Kerr , David F. Cheffings , Howard E. Rhodes
IPC分类号： H01L21/02 , H01L21/8242 , H01L21/70
CPC分类号： H01L27/10852 , H01L28/82
摘要： A solid state fabrication technique for controlling the amount of outdiffusion from a three-dimensional film is comprised of the step of providing a first layer of insitu doped film in a manner to define an upper portion and a lower portion. A second layer of undoped film is provided on top of the first layer to similarly define an upper portion and a lower portion. The first and second layers are etched according to a predetermined pattern. The second layer is doped to obtain a desired dopant density which decreases from the upper portion to the lower portion. Outdiffusion of the dopant from the upper portion of the second layer results in the dopant migrating to the lower portion of the second layer. Thus, outdiffusion into the substrate, and the problems caused thereby, are eliminated or greatly reduced.
摘要翻译：用于控制来自三维膜的向外扩散量的固态制造技术包括以限定上部和下部的方式提供第一层原位掺杂膜的步骤。第二层未掺杂的膜设置在第一层的顶部上，以类似地限定上部和下部。根据预定图案蚀刻第一层和第二层。掺杂第二层以获得从上部向下部减小的期望的掺杂剂密度。从第二层的上部扩散掺杂剂导致掺杂剂迁移到第二层的下部。因此，消除或大大降低了向基板的扩散和由此引起的问题。

4. 发明授权

US06211545B1 Device fabricated by a method of controlling outdiffusion from a doped three-dimensional film 有权
标题翻译：通过控制来自掺杂三维膜的扩散扩散的方法制造的器件
公开(公告)号：US06211545B1
公开(公告)日：2001-04-03
申请号：US09310515
申请日：1999-05-12
申请人： Fernando Gonzalez , D. Mark Durcan , Luan C. Tran , Robert B. Kerr , David F. Cheffings , Howard E. Rhodes
发明人： Fernando Gonzalez , D. Mark Durcan , Luan C. Tran , Robert B. Kerr , David F. Cheffings , Howard E. Rhodes
IPC分类号： H01L27108
CPC分类号： H01L27/10852 , H01L28/82
摘要： A solid state fabrication technique for controlling the amount of outdiffusion from a three-dimensional film is comprised of the step of providing a first layer of insitu doped film in a manner to define an upper portion and a lower portion. A second layer of undoped film is provided on top of the first layer to similarly define an upper portion and a lower portion. The first and second layers are etched according to a predetermined pattern. The second layer is doped to obtain a desired dopant density which decreases from the upper portion to the lower portion. Outdiffusion of the dopant from the upper portion of the second layer results in the dopant migrating to the lower portion of the second layer. Thus, outdiffusion into the substrate, and the problems caused thereby, are eliminated or greatly reduced.
摘要翻译：用于控制来自三维膜的向外扩散量的固态制造技术包括以限定上部和下部的方式提供第一层原位掺杂膜的步骤。第二层未掺杂的膜设置在第一层的顶部上，以类似地限定上部和下部。根据预定图案蚀刻第一层和第二层。掺杂第二层以获得从上部向下部减小的期望的掺杂剂密度。从第二层的上部扩散掺杂剂导致掺杂剂迁移到第二层的下部。因此，消除或大大降低了向基板的扩散和由此引起的问题。

5. 发明授权

US06388314B1 Single deposition layer metal dynamic random access memory 失效
标题翻译：单沉积层金属动态随机存取存储器
公开(公告)号：US06388314B1
公开(公告)日：2002-05-14
申请号：US08516171
申请日：1995-08-17
申请人： Stephen L. Casper , Timothy J. Allen , D. Mark Durcan , Brian M. Shirley , Howard E. Rhodes
发明人： Stephen L. Casper , Timothy J. Allen , D. Mark Durcan , Brian M. Shirley , Howard E. Rhodes
IPC分类号： H01L2352
CPC分类号： H01L23/528 , H01L2924/0002 , H01L2924/1815 , H01L2924/00
摘要： A 16 megabit (224) or greater density single deposition layer metal Dynamic Random Access Memory (DRAM) part is described which allows for a die that fits within an industry-standard 300 ml wide SOJ (Small Outline J-wing) package or a TSOP (Thin, Small Outline Package) with little or no speed loss over previous double metal deposition layered 16 megabit DRAM designs. This is accomplished using a die architecture which allows for a single metal layer signal path, together with the novel use of a lead frame to remove a substantial portion of the power busing from the die, allowing for a smaller, speed-optimized DRAM. The use of a single deposition layer metal results in lower production costs, and shorter production time.
摘要翻译：描述了16兆比特（224）或更大密度的单沉积层金属动态随机存取存储器（DRAM）部件，其允许适用于工业标准的300ml宽SOJ（小外形J翼）封装或TSOP （薄型，小外形封装），与以前的双金属沉积分层16兆位DRAM设计相比，速度损失很少或没有速度损失。这是通过使用允许单个金属层信号路径的管芯架构来实现的，以及引线框架的新颖使用以去除芯片的大部分功率，从而允许较小的速度优化的DRAM。使用单个沉积层金属导致较低的生产成本和较短的生产时间。

6. 发明授权

US5907166A Single deposition layer metal dynamic random access memory 失效
公开(公告)号：US5907166A
公开(公告)日：1999-05-25
申请号：US852905
申请日：1997-05-08
申请人： Stephen L. Casper , Timothy J. Allen , D. Mark Durcan , Brian M. Shirley , Howard E. Rhodes
发明人： Stephen L. Casper , Timothy J. Allen , D. Mark Durcan , Brian M. Shirley , Howard E. Rhodes
IPC分类号： G11C11/401 , H01L23/50 , H01L23/528 , H01L27/10 , H01L31/0328 , H01L31/0336 , H01L31/072
CPC分类号： H01L23/528 , H01L2924/0002 , H01L2924/1815
摘要： A 16 megabit (2.sup.24) or greater density single deposition layer metal Dynamic Random Access Memory (DRAM) part is described which allows for a die that fits within an industry-standard 300 ml wide SOJ (Small Outline J-wing) package or a TSOP (Thin, Small Outline Package) with little or no speed loss over previous double metal deposition layered 16 megabit DRAM designs. This is accomplished using a die architecture which allows for a single metal layer signal path, together with the novel use of a lead frame to remove a substantial portion of the power busing from the die, allowing for a smaller, speed-optimized DRAM. The use of a single deposition layer metal results in lower production costs, and shorter production time.

7. 发明授权

US06569727B1 Method of making a single-deposition-layer-metal dynamic random access memory 失效
标题翻译：制备单沉积层金属动态随机存取存储器的方法
公开(公告)号：US06569727B1
公开(公告)日：2003-05-27
申请号：US08852909
申请日：1997-05-08
申请人： Stephen L. Casper , Timothy J. Allen , D. Mark Durcan , Brian M. Shirley , Howard E. Rhodes
发明人： Stephen L. Casper , Timothy J. Allen , D. Mark Durcan , Brian M. Shirley , Howard E. Rhodes
IPC分类号： H01L218242
CPC分类号： H01L23/528 , H01L2924/0002 , H01L2924/1815 , H01L2924/00
摘要： A 16 megabit (224) or greater density single deposition layer metal Dynamic Random Access Memory (DRAM) part is described which allows for a die that fits within an industry-standard 300 ml wide SOJ (Small Outline J-wing) package or a TSOP (Thin, Small Outline Package) with little or no speed loss over previous double metal deposition layered 16 megabit DRAM designs. This is accomplished using a die architecture which allows for a single metal layer signal path, together with the novel use of a lead frame to remove a substantial portion of the power busing from the die, allowing for a smaller, speed-optimized DRAM. The use of a single deposition layer metal results in lower production costs, and shorter production time.
摘要翻译：描述了16兆比特（224）或更大密度的单沉积层金属动态随机存取存储器（DRAM）部件，其允许适用于工业标准的300ml宽SOJ（小外形J翼）封装或TSOP （薄型，小外形封装），与以前的双金属沉积分层16兆位DRAM设计相比，速度损失很少或没有速度损失。这是通过使用允许单个金属层信号路径的管芯架构来实现的，以及引线框架的新颖使用以去除芯片的大部分功率，从而允许较小的速度优化的DRAM。使用单个沉积层金属导致较低的生产成本和较短的生产时间。

8. 再颁专利

USRE45357E1 Twin p-well CMOS imager 失效
公开(公告)号：USRE45357E1
公开(公告)日：2015-02-03
申请号：US12714339
申请日：2010-02-26
申请人： Howard E. Rhodes
发明人： Howard E. Rhodes
IPC分类号： H01L31/062 , H01L31/113
CPC分类号： H01L27/14609
摘要： A CMOS imager which includes a substrate voltage pump to bias a doped area of a substrate to prevent leakage into the substrate from the transistors formed in the doped area. The invention also provides a CMOS imager where a photodetector sensor array is formed in a first p-well and readout logic is formed in a second p-well. The first p-well can be selectively doped to optimize cross-talk, collection efficiency and transistor leakage, thereby improving the quantum efficiency of the sensor array while the second p-well can be selectively doped and/or biased to improve the speed and drive of the readout circuitry.

9. 发明授权

US08859352B2 Lightly-doped drains (LDD) of image sensor transistors using selective epitaxy 有权
标题翻译：使用选择性外延的图像传感器晶体管的轻掺杂漏极（LDD）
公开(公告)号：US08859352B2
公开(公告)日：2014-10-14
申请号：US13559467
申请日：2012-07-26
申请人： Duli Mao , Hsin-Chih Tai , Howard E. Rhodes , Vincent Venezia , Yin Qian
发明人： Duli Mao , Hsin-Chih Tai , Howard E. Rhodes , Vincent Venezia , Yin Qian
IPC分类号： H01L21/00 , H01L29/66 , H01L27/146
CPC分类号： H01L27/14609 , H01L27/14612 , H01L27/14643 , H01L27/14689 , H01L29/6659 , H01L29/66636
摘要： Embodiments of the present invention are directed to an image sensor having pixel transistors and peripheral transistors disposed in a silicon substrate. For some embodiments, a protective coating is disposed on the peripheral transistors and doped silicon is epitaxially grown on the substrate to form lightly-doped drain (LDD) areas for the pixel transistors. The protective oxide may be used to prevent epitaxial growth of silicon on the peripheral transistors during formation of the LDD areas of the pixel transistors.
摘要翻译：本发明的实施例涉及一种具有设置在硅衬底中的像素晶体管和外围晶体管的图像传感器。对于一些实施例，保护涂层设置在外围晶体管上，并且掺杂的硅在衬底上外延生长以形成用于像素晶体管的轻掺杂漏极（LDD）区域。保护氧化物可以用于在像素晶体管的LDD区域的形成期间防止外围晶体管上的硅的外延生长。

10. 发明授权

US08772898B2 Lateral light shield in backside illuminated imaging sensors 有权
标题翻译：背面照明成像传感器的侧面防护罩
公开(公告)号：US08772898B2
公开(公告)日：2014-07-08
申请号：US13370085
申请日：2012-02-09
申请人： Duli Mao , Hsin-Chih Tai , Vincent Venezia , Yin Qian , Gang Chen , Howard E. Rhodes
发明人： Duli Mao , Hsin-Chih Tai , Vincent Venezia , Yin Qian , Gang Chen , Howard E. Rhodes
IPC分类号： H01L31/0216
CPC分类号： H01L27/1462 , H01L27/14623 , H01L27/1464 , H01L27/14685
摘要： A backside illuminated image sensor includes a semiconductor layer and a trench disposed in the semiconductor layer. The semiconductor layer has a frontside surface and a backside surface. The semiconductor layer includes a light sensing element of a pixel array disposed in a sensor array region of the semiconductor layer. The pixel array is positioned to receive external incoming light through the backside surface of the semiconductor layer. The semiconductor layer also includes a light emitting element disposed in a periphery circuit region of the semiconductor layer external to the sensor array region. The trench is disposed in the semiconductor layer between the light sensing element and the light emitting element. The trench is positioned to impede a light path between the light emitting element and the light sensing element when the light path is internal to the semiconductor layer.
摘要翻译：背面照明图像传感器包括设置在半导体层中的半导体层和沟槽。半导体层具有前表面和背面。半导体层包括设置在半导体层的传感器阵列区域中的像素阵列的光感测元件。像素阵列被定位成接收穿过半导体层的背面的外部入射光。半导体层还包括设置在传感器阵列区域外部的半导体层的外围电路区域中的发光元件。沟槽设置在光感测元件和发光元件之间的半导体层中。当光路在半导体层内部时，沟槽定位成阻碍发光元件和光感测元件之间的光路。

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