专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

US20050196878A1 Single-phase c-axis doped PGO ferroelectric thin films 有权
标题翻译：单相c轴掺杂PGO铁电薄膜
公开(公告)号：US20050196878A1
公开(公告)日：2005-09-08
申请号：US11046620
申请日：2005-01-28
申请人： Fengyan Zhang , Wei-Wei Zhuang , Jong-Jan Lee , Sheng Hsu
发明人： Fengyan Zhang , Wei-Wei Zhuang , Jong-Jan Lee , Sheng Hsu
IPC分类号： H01L21/00 , H01L21/02 , H01L21/316 , H01L41/22
CPC分类号： H01L21/31691 , H01L28/55 , H01L41/317
摘要： A method for forming a doped PGO ferroelectric thin film, and related doped PGO thin film structures are described. The method comprising: forming either an electrically conductive or electrically insulating substrate; forming a doped PGO film overlying the substrate; annealing; crystallizing; and, forming a single-phase c-axis doped PGO thin film overlying the substrate, having a Curie temperature of greater than 200 degrees C. Forming a doped PGO film overlying the substrate includes depositing a doped precursor in the range between 0.1N and 0.5N, with a molecular formula of Pby−xMxGe3O11, where: M is a doping element; y=4.5 to 6; and, x=0.1 to 1. The element M can be Sn, Ba, Sr, Cd, Ca, Pr, Ho, La, Sb, Zr, or Sm.
摘要翻译：描述了用于形成掺杂的PGO铁电薄膜的方法以及相关的掺杂PGO薄膜结构。该方法包括：形成导电或电绝缘的衬底; 在衬底上形成掺杂的PGO膜; 退火; 结晶并且形成覆盖在衬底上的单相c轴掺杂的PGO薄膜，其居里温度大于200℃。形成覆盖在衬底上的掺杂PGO膜包括在0.1N和0.5之间的范围内沉积掺杂的前体 N，具有分子式为Pb x Si x N x N x O 11，其中：M是掺杂物元件; y = 4.5〜6; x = 0.1〜1。元素M可以是Sn，Ba，Sr，Cd，Ca，Pr，Ho，La，Sb，Zr或Sm。

2. 发明申请

US20060088974A1 METHOD OF AFFECTING RRAM CHARACTERISTICS BY DOPING PCMO THIN FILMS 有权
标题翻译：通过PCMO薄膜影响RRAM特性的方法
公开(公告)号：US20060088974A1
公开(公告)日：2006-04-27
申请号：US10971387
申请日：2004-10-21
申请人： Wei-Wei Zhuang , David Evans , Fengyan Zhang , Sheng Hsu
发明人： Wei-Wei Zhuang , David Evans , Fengyan Zhang , Sheng Hsu
IPC分类号： H01L21/20 , H01L21/00
CPC分类号： H01L45/1608 , C23C18/1216 , C23C18/1225 , C23C18/1283 , C23C18/1295 , H01L21/31691 , H01L28/20 , H01L45/04 , H01L45/1233 , H01L45/147
摘要： A method of fabricating a doped-PCMO thin film layer includes preparing a PCMO precursor solution having a transition metal additive therein; and spin-coating the doped-PCMO spin-coating solution onto a wafer.
摘要翻译：制造掺杂PCMO薄膜层的方法包括制备其中具有过渡金属添加剂的PCMO前体溶液; 并将掺杂的PCMO旋涂溶液旋涂到晶片上。

3. 发明申请

US20060099724A1 Memory cell with buffered layer 有权
标题翻译：带缓冲层的存储单元
公开(公告)号：US20060099724A1
公开(公告)日：2006-05-11
申请号：US11314222
申请日：2005-12-21
申请人： Sheng Hsu , Tingkai Li , Fengyan Zhang , Wei Pan , Wei-Wei Zhuang , David Evans , Masayuki Tajiri
发明人： Sheng Hsu , Tingkai Li , Fengyan Zhang , Wei Pan , Wei-Wei Zhuang , David Evans , Masayuki Tajiri
IPC分类号： H01L21/00 , H01L21/20
CPC分类号： H01L27/101 , G11C13/0007 , G11C13/0069 , G11C2013/0073 , G11C2213/31 , G11C2213/51 , G11C2213/56 , G11C2213/79 , H01L27/2436 , H01L45/04 , H01L45/12 , H01L45/1233 , H01L45/147
摘要： A method is provided for forming a buffered-layer memory cell. The method comprises: forming a bottom electrode; forming a colossal magnetoresistance (CMR) memory film overlying the bottom electrode; forming a memory-stable semiconductor buffer layer, typically a metal oxide, overlying the memory film; and, forming a top electrode overlying the semiconductor buffer layer. In some aspects of the method the semiconductor buffer layer is formed from YBa2Cu3O7-X (YBCO), indium oxide (In2O3), or ruthenium oxide (RuO2), having a thickness in the range of 10 to 200 nanometers (nm). The top and bottom electrodes may be TiN/Ti, Pt/TiN/Ti, In/TiN/Ti, PtRhOx compounds, or PtIrOx compounds. The CMR memory film may be a Pr1-XCaXMnO3 (PCMO) memory film, where x is in the region between 0.1 and 0.6, with a thickness in the range of 10 to 200 nm.
摘要翻译：提供了一种用于形成缓冲层存储单元的方法。该方法包括：形成底部电极; 形成覆盖底部电极的巨大磁阻（CMR）记忆膜; 形成存储器稳定的半导体缓冲层，通常为覆盖存储膜的金属氧化物; 并且形成覆盖半导体缓冲层的顶部电极。在该方法的一些方面，半导体缓冲层由YBa 2 N 3 O 7-X（YBCO），氧化铟（In 2或2 O 3）或氧化钌（RuO 2 N 2），其厚度在10-200纳米（nm）的范围内。顶部和底部电极可以是TiN / Ti，Pt / TiN / Ti，In / TiN / Ti，PtRhOx化合物或PtIrOx化合物。 CMR存储器膜可以是Pr 1-X C x MnO 3（PCMO）存储膜，其中x在0.1之间的区域和0.6，厚度在10至200nm的范围内。

4. 发明申请

US20050239262A1 PCMO thin film with memory resistance properties 有权
标题翻译：具有记忆电阻特性的PCMO薄膜
公开(公告)号：US20050239262A1
公开(公告)日：2005-10-27
申请号：US10831677
申请日：2004-04-23
申请人： Wei-Wei Zhuang , Tingkai Li , Sheng Hsu , Fengyan Zhang
发明人： Wei-Wei Zhuang , Tingkai Li , Sheng Hsu , Fengyan Zhang
IPC分类号： H01L27/105 , H01L21/00 , H01L21/20 , H01L27/10 , H01L45/00 , H01L49/02
CPC分类号： H01L45/04 , G11C13/0004 , G11C13/0007 , G11C13/0069 , G11C2013/0073 , G11C2213/31 , H01L45/1233 , H01L45/147 , H01L45/1608
摘要： A method is provided for forming a Pr0.3Ca0.7MnO3 (PCMO) thin film with crystalline structure-related memory resistance properties. The method comprises: forming a PCMO thin film with a first crystalline structure; and, changing the resistance state of the PCMO film using pulse polarities responsive to the first crystalline structure. In one aspect the first crystalline structure is either amorphous or a weak-crystalline. Then, the resistance state of the PCMO film is changed in response to unipolar pulses. In another aspect, the PCMO thin film has either a polycrystalline structure. Then, the resistance state of the PCMO film changes in response to bipolar pulses.
摘要翻译：提供了一种用于形成具有结晶结构相关的记忆电阻性质的Pr 0.3M 3 Ca 0.7 MnO 3（PCMO）薄膜的方法。该方法包括：形成具有第一晶体结构的PCMO薄膜; 并且使用响应于第一晶体结构的脉冲极性来改变PCMO膜的电阻状态。在一个方面，第一晶体结构是无定形或弱结晶。然后，响应于单极脉冲改变PCMO膜的电阻状态。另一方面，PCMO薄膜具有多晶结构。然后，PCMO膜的电阻状态响应于双极性脉冲而改变。

5. 发明申请

US20050054119A1 Buffered-layer memory cell 失效
标题翻译：缓冲层存储单元
公开(公告)号：US20050054119A1
公开(公告)日：2005-03-10
申请号：US10755654
申请日：2004-01-12
申请人： Sheng Hsu , Tingkai Li , Fengyan Zhang , Wei Pan , Wei-Wei Zhuang , David Evans , Masayuki Tajiri
发明人： Sheng Hsu , Tingkai Li , Fengyan Zhang , Wei Pan , Wei-Wei Zhuang , David Evans , Masayuki Tajiri
IPC分类号： H01L27/10 , G11C13/00 , H01L27/24 , H01L45/00 , H01L21/00 , G11C11/00 , H01L21/336 , H01L21/8234
CPC分类号： H01L27/101 , G11C13/0007 , G11C13/0069 , G11C2013/0073 , G11C2213/31 , G11C2213/51 , G11C2213/56 , G11C2213/79 , H01L27/2436 , H01L45/04 , H01L45/12 , H01L45/1233 , H01L45/147
摘要： A method is provided for forming a buffered-layer memory cell. The method comprises: forming a bottom electrode; forming a colossal magnetoresistance (CMR) memory film overlying the bottom electrode; forming a memory-stable semiconductor buffer layer, typically a metal oxide, overlying the memory film; and, forming a top electrode overlying the semiconductor buffer layer. In some aspects of the method the semiconductor buffer layer is formed from YBa2Cu3O7−X (YBCO), indium oxide (In2O3), or ruthenium oxide (RuO2), having a thickness in the range of 10 to 200 nanometers (nm). The top and bottom electrodes may be TiN/Ti, Pt/TiN/Ti, In/TiN/Ti, PtRhOx compounds, or PtIrOx compounds. The CMR memory film may be a Pr1−XCaXMnO3 (PCMO) memory film, where x is in the region between 0.1 and 0.6, with a thickness in the range of 10 to 200 nm.
摘要翻译：提供了一种用于形成缓冲层存储单元的方法。该方法包括：形成底部电极; 形成覆盖底部电极的巨大磁阻（CMR）记忆膜; 形成存储器稳定的半导体缓冲层，通常为覆盖存储膜的金属氧化物; 并且形成覆盖半导体缓冲层的顶部电极。在该方法的某些方面，半导体缓冲层由厚度在10至200纳米（nm）范围内的YBa2Cu3O7-X（YBCO），氧化铟（In2O3）或氧化钌（RuO2）形成。顶部和底部电极可以是TiN / Ti，Pt / TiN / Ti，In / TiN / Ti，PtRhOx化合物或PtIrOx化合物。 CMR存储器膜可以是Pr1-XCaXMnO3（PCMO）记忆膜，其中x在0.1和0.6之间的区域中，厚度在10至200nm的范围内。

6. 发明申请

US20050009286A1 Method of fabricating nano-scale resistance cross-point memory array 有权
标题翻译：制造纳米级电阻交叉点存储阵列的方法
公开(公告)号：US20050009286A1
公开(公告)日：2005-01-13
申请号：US10909218
申请日：2004-07-29
申请人： Sheng Hsu , Wei-Wei Zhuang , Wei Pan , Fengyan Zhang
发明人： Sheng Hsu , Wei-Wei Zhuang , Wei Pan , Fengyan Zhang
IPC分类号： H01L27/105 , G11C13/00 , H01L21/8246 , H01L27/115 , H01L27/24 , H01L43/08 , H01L27/108
CPC分类号： G11C13/0007 , G11C2213/31 , G11C2213/77 , H01L27/2409 , H01L27/2463 , H01L45/04 , H01L45/1233 , H01L45/147 , H01L45/1683
摘要： A method of fabricating a nano-scale resistance cross-point memory array includes preparing a silicon substrate; depositing silicon oxide on the substrate to a predetermined thickness; forming a nano-scale trench in the silicon oxide; depositing a first connection line in the trench; depositing a memory resistor layer in the trench on the first connection line; depositing a second connection line in the trench on the memory resistor layer; and completing the memory array. A cross-point memory array includes a silicon substrate; a first connection line formed on the substrate; a colossal magnetoresistive layer formed on the first connection line; a silicon nitride layer formed on a portion of the colossal magnetoresistive layer; and a second connection line formed adjacent the silicon nitride layer and on the colossal magnetoresistive layer.
摘要翻译：制造纳米尺度电阻交叉点存储器阵列的方法包括制备硅衬底; 在衬底上沉积氧化硅至预定厚度; 在氧化硅中形成纳米尺度的沟槽; 在沟槽中沉积第一连接线; 在第一连接线上的沟槽中沉积记忆电阻层; 在所述存储器电阻层的沟槽中沉积第二连接线; 并完成内存阵列。交叉点存储器阵列包括硅衬底; 形成在所述基板上的第一连接线; 形成在第一连接线上的巨大的磁阻层; 形成在巨磁阻层的一部分上的氮化硅层; 以及与氮化硅层和巨磁阻层相邻形成的第二连接线。

7. 发明申请

US20060246606A1 Self-aligned cross point resistor memory array 有权
标题翻译：自对准交叉点电阻存储器阵列
公开(公告)号：US20060246606A1
公开(公告)日：2006-11-02
申请号：US11120385
申请日：2005-05-02
申请人： Sheng Hsu , Jong-Jan Lee , Jer-Shen Maa , Douglas Tweet , Wei-Wei Zhuang
发明人： Sheng Hsu , Jong-Jan Lee , Jer-Shen Maa , Douglas Tweet , Wei-Wei Zhuang
IPC分类号： H01L21/8234
CPC分类号： H01L27/101 , H01L27/2409 , H01L27/2481 , H01L45/04 , H01L45/1233 , H01L45/147 , H01L45/1683
摘要： A method of fabricating resistor memory array includes preparing a silicon substrate; depositing a bottom electrode, a sacrificial layer, and a hard mask layer on a substrate P+ layer; masking, patterning and etching to remove, in a first direction, a portion of the hard mask, the sacrificial material, the bottom electrode; depositing a layer of silicon oxide; masking, patterning and etching to remove, in a second direction perpendicular to the first direction, a portion of the hard mask, the sacrificial material, the bottom electrode;, and over etching to an N+ layer and at least 100 nm of the silicon substrate; depositing of a layer of silicon oxide; etching to remove any remaining hard mask and any remaining sacrificial material; depositing a layer of CMR material; depositing a top electrode; applying photoresist, patterning the photoresist and etching the top electrode; and incorporating the memory array into an integrated circuit.
摘要翻译：制造电阻器存储器阵列的方法包括制备硅衬底; 在衬底P +层上沉积底部电极，牺牲层和硬掩模层; 掩模，图案化和蚀刻以在第一方向上去除硬掩模，牺牲材料，底部电极的一部分; 沉积一层氧化硅; 掩模，图案化和蚀刻以在垂直于第一方向的第二方向上去除硬掩模，牺牲材料，底部电极的一部分，并且对N +层和至少100nm的硅衬底进行过蚀刻 ; 沉积一层氧化硅; 蚀刻以除去任何剩余的硬掩模和任何剩余的牺牲材料; 沉积一层CMR材料; 沉积顶部电极; 施加光致抗蚀剂，图案化光致抗蚀剂并蚀刻顶部电极; 并将存储器阵列并入集成电路中。

8. 发明申请

US20080010707A1 Ambient environment nanowire sensor 失效
标题翻译：环境纳米线传感器
公开(公告)号：US20080010707A1
公开(公告)日：2008-01-10
申请号：US11264113
申请日：2005-11-01
申请人： Fengyan Zhang , Robert Barrowcliff , Jong-Jan Lee , Sheng Hsu
发明人： Fengyan Zhang , Robert Barrowcliff , Jong-Jan Lee , Sheng Hsu
IPC分类号： C30B25/00 , C30B23/00 , C30B28/12
CPC分类号： B81C1/00182 , B81B2201/0214 , Y10S977/712 , Y10S977/762
摘要： An ambient environment nanowire sensor and corresponding fabrication method have been provided. The method includes: forming a substrate such as Silicon (Si) or glass; growing nanowires; depositing an insulator layer overlying the nanowires; etching to expose tips of the nanowires; forming a patterned metal electrode, with edges, overlying the tips of the nanowires; and, etching to expose the nanowires underlying the electrode edges. The nanowires can be a material such as IrO2, TiO2, InO, ZnO, SnO2, Sb2O3, or In2O3, to mane just a few examples. The insulator layer can be a spin-on glass (SOG) or low-k dielectric. In one aspect, the resultant structure includes exposed nanowires grown from the doped substrate regions and an insulator core with embedded nanowires. In a different aspect, the method forms a growth promotion layer overlying the substrate. The resultant structure includes exposed nanowires grown from the selectively formed growth promotion layer.
摘要翻译：提供了一种周围环境纳米线传感器和相应的制造方法。该方法包括：形成诸如硅（Si）或玻璃的衬底; 生长纳米线沉积覆盖在纳米线上的绝缘体层; 蚀刻以暴露纳米线的尖端; 形成图案化的金属电极，其边缘覆盖在纳米线的尖端上; 并且蚀刻以暴露电极边缘下方的纳米线。纳米线可以是诸如IrO 2，TiO 2，InO，ZnO，SnO 2，Sb 2，N 2的材料例如，在实施例3中，可以举出例如“O 3”，“3”，“ 绝缘体层可以是旋涂玻璃（SOG）或低k电介质。一方面，所得结构包括从掺杂衬底区域生长的暴露的纳米线和具有嵌入的纳米线的绝缘体芯。在不同的方面，该方法形成覆盖衬底的生长促进层。所得结构包括从选择性形成的生长促进层生长的暴露的纳米线。

9. 发明申请

US20070048990A1 Method of buffer layer formation for RRAM thin film deposition 审中-公开
标题翻译： RRAM薄膜沉积缓冲层形成方法
公开(公告)号：US20070048990A1
公开(公告)日：2007-03-01
申请号：US11215520
申请日：2005-08-30
申请人： Wei-Wei Zhuang , Sheng Hsu , David Evans , Tingkai Li , Lawrence Charneski
发明人： Wei-Wei Zhuang , Sheng Hsu , David Evans , Tingkai Li , Lawrence Charneski
IPC分类号： H01L21/3205
CPC分类号： H01L45/04 , H01L45/1233 , H01L45/147 , H01L45/1608
摘要： A method of buffer layer formation for RRAM thin film deposition includes preparing a substrate; depositing a bottom electrode on the substrate; depositing a thin layer of a transition metal having a multiple valence on the bottom electrode; depositing a layer of metal oxide on the transition metal; depositing a top electrode on the metal oxide; annealing the substrate and the layers formed thereon; and completing the RRAM.
摘要翻译：用于RRAM薄膜沉积的缓冲层形成方法包括制备衬底; 在底物上沉积底部电极; 在底部电极上沉积具有多价的过渡金属的薄层; 在过渡金属上沉积一层金属氧化物; 在金属氧化物上沉积顶部电极; 退火衬底及其上形成的层; 并完成RRAM。

10. 发明申请

US20050245039A1 PCMO thin film with resistance random access memory (RRAM) characteristics 有权
标题翻译：具有电阻随机存取存储器（RRAM）特性的PCMO薄膜
公开(公告)号：US20050245039A1
公开(公告)日：2005-11-03
申请号：US10836689
申请日：2004-04-30
申请人： Tingkai Li , Wei-Wei Zhuang , David Evans , Sheng Hsu
发明人： Tingkai Li , Wei-Wei Zhuang , David Evans , Sheng Hsu
IPC分类号： C01G45/00 , C01F11/02 , C01F17/00 , C01G99/00 , G11C13/00 , H01L21/00 , H01L21/20 , H01L27/10 , H01L43/08 , H01L45/00
CPC分类号： G11C13/0007 , G11C2213/31 , H01L45/04 , H01L45/1233 , H01L45/147
摘要： PrCaMnO (PCMO) thin films with predetermined memory-resistance characteristics and associated formation processes have been provided. In one aspect the method comprises: forming a Pr3+1−xCa2+xMnO thin film composition, where 0.1
摘要翻译：已经提供了具有预定的记忆电阻特性和相关的形成过程的PrCaMnO（PCMO）薄膜。在一个方面，所述方法包括：形成Pr 3+ 1-x 2 Ca 2 O 3 x MnO薄膜组成，其中0.1 _0.78Mn^{4+</SUP>_0.22O^2-_{2.96 组合， Mn和O离子的比例变化如下：O 2 - （2.96）; Mn（3+）+（（1-x）+ 8％）; 和Mn 4+（x-8％）。在另一方面，该方法响应于晶体取向在PCMO膜中产生密度。例如，如果PCMO膜具有（110）取向，则在垂直于（110）取向的平面中产生在每平方英尺5至6.76个Mn原子的范围内的密度。}}

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式