专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US06670283B2 Backside protection films 失效
标题翻译：背面保护膜
公开(公告)号：US06670283B2
公开(公告)日：2003-12-30
申请号：US09989389
申请日：2001-11-20
申请人： Faye D. Baker , Casey J. Grant , Mousa H. Ishaq , Joel M. Sharrow , James D. Weil
发明人： Faye D. Baker , Casey J. Grant , Mousa H. Ishaq , Joel M. Sharrow , James D. Weil
IPC分类号： H01L2131
CPC分类号： H01L21/02164 , H01L21/02115 , H01L21/0217 , H01L21/022 , H01L21/02271 , H01L21/02274 , H01L21/31612
摘要： Disclosed is a method of fabricating a semiconductor device, comprising: (a) providing a bare semiconductor substrate, the substrate having a frontside and a backside; (b) forming one or more protective films on the backside of the substrate; and (c) performing one or more wafer fabrication steps. Some or all the protective films may be removed and the method repeated multiple times during fabrication of the semiconductor device.
摘要翻译：公开了一种制造半导体器件的方法，包括：（a）提供裸半导体衬底，所述衬底具有前侧和后侧; （b）在衬底的背面形成一个或多个保护膜; 和（c）执行一个或多个晶片制造步骤。可以去除一些或全部保护膜，并且在制造半导体器件期间该方法重复多次。

2. 发明授权

US06939408B1 Method for surface preparation of workpieces utilizing fluid separation techniques 失效
标题翻译：利用流体分离技术对工件进行表面处理的方法
公开(公告)号：US06939408B1
公开(公告)日：2005-09-06
申请号：US09650103
申请日：2000-08-29
申请人： Francis A. Abramovich , Nicole S. Carpenter , Joseph R. Drennan , Rick H. Gaylord , Casey J. Grant , Kenneth F. McAvey, Jr. , Mark A. Pakulski , Joel M. Sharrow , William A. Syverson , Alison K. Easton , Kenneth H. Yao
发明人： Francis A. Abramovich , Nicole S. Carpenter , Joseph R. Drennan , Rick H. Gaylord , Casey J. Grant , Kenneth F. McAvey, Jr. , Mark A. Pakulski , Joel M. Sharrow , William A. Syverson , Alison K. Easton , Kenneth H. Yao
IPC分类号： B08B3/00 , B08B3/08 , H01L21/00 , H01L21/306
CPC分类号： H01L21/02052 , B08B3/08 , H01L21/02019 , H01L21/30604 , H01L21/67086 , Y10S134/902
摘要： A method for preparing a workpiece surface utilizing two more fluids of differing density and miscibility which create one or more fluid interfaces wherein the fluids are chosen such that the solubility or affinity of one of the fluids is high for a material to be removed from the workpiece surface while the other fluid has a low solubility or affinity for the material to be removed. The workpiece surface is treated by passing the workpiece through the fluid interface. The two or more fluids are preferably dispensed into an apparatus and allowed to settle into two or more predominant layers separated by an interface. Surface preparation techniques which may benefit from the present invention include etching, cleaning or drying processes and the like.
摘要翻译：一种用于制备工件表面的方法，其使用两种不同密度和混溶性的流体，其产生一个或多个流体界面，其中选择流体使得流体之一的溶解度或亲和力对于从工件中去除的材料是高的而另一种流体对待除去的材料具有低溶解度或亲和性。通过使工件通过流体界面来处理工件表面。两种或更多种流体优选地分配到装置中并允许沉降到由界面分开的两个或更多个主要层中。可受益于本发明的表面处理技术包括蚀刻，清洗或干燥过程等。

3. 发明授权

US06776171B2 Cleaning of semiconductor wafers by contaminate encapsulation 失效
公开(公告)号：US06776171B2
公开(公告)日：2004-08-17
申请号：US09892954
申请日：2001-06-27
申请人： Nicole S. Carpenter , Joseph R. Drennan , Alison K. Easton , Casey J. Grant , Andrew S. Hoadley , Kenneth F. McAvey, Jr. , Joel M. Sharrow , William A. Syverson , Kenneth H. Yao
发明人： Nicole S. Carpenter , Joseph R. Drennan , Alison K. Easton , Casey J. Grant , Andrew S. Hoadley , Kenneth F. McAvey, Jr. , Joel M. Sharrow , William A. Syverson , Kenneth H. Yao
IPC分类号： B08B700
CPC分类号： B08B7/0014
摘要： An apparatus and method are provided for removing contaminate particulate matter from substrate surfaces such as semiconductor wafers. The method and apparatus use a material, preferably a liquid curable polymer, which is applied as a sacrificial coating to the surface of a substrate containing contaminate particulate matter thereon. An energy source is used to dislodge the contaminate particulate matter from the surface of the wafer into the sacrificial coating so that the particles are partially or fully encapsulated and suspended in the sacrificial coating. The sacrificial coating is then removed. The coating is preferably formed into a film to facilitate removal of the coating by pulling (stripping) the film providing a cleaner substrate surface.

4. 发明授权

US06992014B2 Method and apparatus for etch rate uniformity control 有权
标题翻译：用于蚀刻速率均匀性控制的方法和装置
公开(公告)号：US06992014B2
公开(公告)日：2006-01-31
申请号：US10065720
申请日：2002-11-13
申请人： Casey J. Grant , Joel M. Sharrow , John J. Snyder
发明人： Casey J. Grant , Joel M. Sharrow , John J. Snyder
IPC分类号： H01L21/302 , H01L21/461
CPC分类号： H01L21/67253 , H01L21/31111
摘要： A method for controlling a process on a substrate. The method comprising: providing the substrate, the substrate having an upper surface, an opposite lower surface and an edge between the upper and lower surfaces; processing the upper surface of the substrate with a first fluid; directing a second fluid against a portion of the lower surface proximate to the edge of the substrate, wherein the second fluid flows adjacent to the edge of the substrate; and controlling the temperature of the second fluid in order to affect a processing of an edge region of the upper side of the substrate.
摘要翻译：一种用于控制衬底上的工艺的方法。所述方法包括：提供所述基底，所述基底具有上表面，相对的下表面和所述上表面和所述下表面之间的边缘; 用第一流体处理衬底的上表面; 将第二流体引导靠近所述基底的边缘的所述下表面的一部分，其中所述第二流体邻近所述基底的边缘流动; 以及控制第二流体的温度，以便影响衬底的上侧的边缘区域的处理。

5. 发明授权

US06884722B2 Method of fabricating a narrow polysilicon line 失效
标题翻译：制造窄多晶硅生产线的方法
公开(公告)号：US06884722B2
公开(公告)日：2005-04-26
申请号：US09964918
申请日：2001-09-27
申请人： Casey J. Grant , Robert K. Leidy , Joel M. Sharrow
发明人： Casey J. Grant , Robert K. Leidy , Joel M. Sharrow
IPC分类号： H01L21/28 , H01L21/3213 , H01L21/336 , H01L21/302
CPC分类号： H01L29/6659 , H01L21/28114 , H01L21/32134 , H01L21/32139
摘要： Disclosed is a method of fabricating a polysilicon line, comprising: forming a patterned hard mask layer over a polysilicon layer; patterning the polysilicon layer to provide a hard mask-capped polysilicon line having a first width; and isotropically removing portions of the polysilicon line to a second width.
摘要翻译：公开了一种制造多晶硅线的方法，包括：在多晶硅层上形成图案化的硬掩模层; 图案化多晶硅层以提供具有第一宽度的硬掩模帽多晶硅线; 并且将多晶硅线的各向同性地去除到第二宽度。

6. 发明授权

US08399181B2 Methods of fabricating photomasks for improving damascene wire uniformity without reducing performance 有权
标题翻译：制造光掩模以改善镶嵌丝均匀性而不降低性能的方法
公开(公告)号：US08399181B2
公开(公告)日：2013-03-19
申请号：US13346776
申请日：2012-01-10
申请人： Casey J. Grant , Jude L. Hankey
发明人： Casey J. Grant , Jude L. Hankey
IPC分类号： G03F7/16 , G03F7/20 , G03F7/40 , G06F17/50
CPC分类号： H01L21/7684 , G03F1/36 , H01L21/3212 , H01L23/522 , H01L2924/0002 , H01L2924/00
摘要： A method of improving damascene wire uniformity without reducing performance. The method includes simultaneously forming a multiplicity of damascene wires and a multiplicity of metal dummy shapes in a dielectric layer of a wiring level of an integrated circuit chip, the metal dummy shapes being dispersed between damascene wires of the multiplicity of damascene wires; and removing or modifying those metal dummy shapes of the multiplicity of metal dummy shapes within exclusion regions around selected damascene wires of the multiplicity of damascene wires. Also a method of fabricating a photomask and a photomask for use in improving damascene wire uniformity without reducing performance.
摘要翻译：改善镶嵌丝均匀性而不降低性能的方法。该方法包括在集成电路芯片的布线层的电介质层中同时形成多个镶嵌线和多个金属虚拟形状，金属虚拟形状分散在多个镶嵌线的镶嵌线之间; 以及在多个镶嵌线的所选择的镶嵌线周围的排除区域内去除或修改多个金属假形状的那些金属虚拟形状。还有一种制造光掩模和光掩模的方法，其用于改善镶嵌线的均匀性而不降低性能。

7. 发明授权

US07205216B2 Modification of electrical properties for semiconductor wafers 失效
标题翻译：半导体晶圆的电性能的改进
公开(公告)号：US07205216B2
公开(公告)日：2007-04-17
申请号：US10710700
申请日：2004-07-29
申请人： Casey J. Grant , Heidi L. Greer , Steven M. Shank , Michael C. Triplett
发明人： Casey J. Grant , Heidi L. Greer , Steven M. Shank , Michael C. Triplett
IPC分类号： H01L21/20 , H01L21/31
CPC分类号： H01L21/324 , H01L22/20
摘要： A method and structure for fabricating semiconductor wafers. The method comprises providing a plurality of semiconductor wafers. The plurality of semiconductor wafers comprises a first semiconductor wafer and a second semiconductor wafer. The first semiconductor wafer is located adjacent to the second semiconductor wafer. A relationship is provided between a plurality of values for an electrical characteristic and a plurality of materials. A material is chosen from the plurality of materials existing in the relationship. A substructure is formed comprising the material sandwiched between a topside of the first semiconductor wafer and a backside of a portion of the of the second semiconductor wafer. The plurality of semiconductor wafers are placed into a furnace comprising an elevated temperature for processing resulting in a value for the first semiconductor wafer of the electrical characteristic that corresponds to said material in said relationship.
摘要翻译：一种用于制造半导体晶片的方法和结构。该方法包括提供多个半导体晶片。多个半导体晶片包括第一半导体晶片和第二半导体晶片。第一半导体晶片位于第二半导体晶片附近。在电特性和多种材料的多个值之间提供关系。从存在于该关系中的多种材料中选择材料。形成了包括夹在第一半导体晶片的顶侧和第二半导体晶片的一部分的背面之间的材料的子结构。将多个半导体晶片放置在包括用于处理的升高的温度的炉中，从而产生与所述关系中的所述材料对应的电特性的第一半导体晶片的值。

8. 发明授权

US08849440B2 Manufacturing control based on a final design structure incorporating both layout and client-specific manufacturing information 有权
标题翻译：基于结合布局和客户特定制造信息的最终设计结构的制造控制
公开(公告)号：US08849440B2
公开(公告)日：2014-09-30
申请号：US13485862
申请日：2012-05-31
申请人： Casey J. Grant , Kurt A. Tallman , Sabastian T. Ventrone
发明人： Casey J. Grant , Kurt A. Tallman , Sabastian T. Ventrone
IPC分类号： G05B13/02
CPC分类号： G05B19/4097 , G05B2219/32031 , G05B2219/32033 , G05B2219/45031
摘要： Disclosed are embodiments of an improved design method, the results of which are a final design structure for an integrated circuit that incorporates, not only layout information, but also client-specific manufacturing information (e.g., import/export information, service requests, processing directives, purchase order requirements, design rule information, etc.) in the same data format in hierarchical form. Also disclosed are embodiments of a manufacturing control method and system. In these embodiments, a final design structure, such as that described above, is received at tape-in. The information contained therein (particularly, the client-specific manufacturing information) is sorted by type and then forwarded to the appropriate tools within the manufacturing facility for processing. By providing the client-specific manufacturing information directly to each manufacturing facility in the final design structure in conjunction with the layout information, the embodiments eliminate the need for independent information gathering by each manufacturing facility.
摘要翻译：公开了一种改进的设计方法的实施例，其结果是集成电路的最终设计结构，不仅包括布局信息，而且包括客户特定制造信息（例如，导入/导出信息，服务请求，处理指令，采购订单要求，设计规则信息等）以相同的数据格式分层格式。还公开了制造控制方法和系统的实施例。在这些实施例中，诸如上述的最终设计结构在磁带入口处被接收。其中包含的信息（特别是客户特定的制造信息）按类型排序，然后转发到制造设施内的适当工具进行处理。结合布局信息，通过在终端设计结构中直接向每个制造设施提供特定于客户的制造信息，实施例消除了对每个制造设备的独立信息收集的需要。

9. 发明申请

US20120151748A1 METHODS OF DESIGNING AN INDUCTOR HAVING OPENING ENCLOSED WITHIN CONDUCTIVE LINE 有权
标题翻译：设计在导线中封闭的电感器的方法
公开(公告)号：US20120151748A1
公开(公告)日：2012-06-21
申请号：US13404485
申请日：2012-02-24
申请人： Mete Erturk , John D. Gillis , Casey J. Grant , David Scagnelli , Anthony K. Stamper
发明人： Mete Erturk , John D. Gillis , Casey J. Grant , David Scagnelli , Anthony K. Stamper
IPC分类号： G01R31/28 , G06F17/50
CPC分类号： H01F17/0006 , H01F17/04 , H01F27/2847 , H01F41/04 , H01F41/041 , H01F41/045 , H01F2017/0053 , H01F2017/0073 , H01F2017/046 , H01L23/5227 , H01L23/528 , H01L23/645 , H01L28/10 , H01L2924/0002 , H01L2924/3011 , Y10T29/49004 , Y10T29/4902 , Y10T29/49069 , Y10T29/49073 , Y10T29/49156 , H01L2924/00
摘要： Embodiments disclosed include methods of designing an inductor. The inductor can include a conductive line including at least one turn and an opening positioned within an interior of a region of the conductive line.
摘要翻译：公开的实施例包括设计电感器的方法。电感器可以包括包括至少一个匝的导电线和位于导电线的区域的内部内的开口。

10. 发明申请

US20130325156A1 MANUFACTURING CONTROL BASED ON A FINAL DESIGN STRUCTURE INCORPORATING BOTH LAYOUT AND CLIENT-SPECIFIC MANUFACTURING INFORMATION 有权
标题翻译：基于最终设计结构的制造控制，包括两个布局和客户特定的制造信息
公开(公告)号：US20130325156A1
公开(公告)日：2013-12-05
申请号：US13485862
申请日：2012-05-31
申请人： Casey J. Grant , Kurt A. Tallman , Sebastian T. Ventrone
发明人： Casey J. Grant , Kurt A. Tallman , Sebastian T. Ventrone
IPC分类号： G05B13/02
CPC分类号： G05B19/4097 , G05B2219/32031 , G05B2219/32033 , G05B2219/45031
摘要： Disclosed are embodiments of an improved design method, the results of which are a final design structure for an integrated circuit that incorporates, not only layout information, but also client-specific manufacturing information (e.g., import/export information, service requests, processing directives, purchase order requirements, design rule information, etc.) in the same data format in hierarchical form. Also disclosed are embodiments of a manufacturing control method and system. In these embodiments, a final design structure, such as that described above, is received at tape-in. The information contained therein (particularly, the client-specific manufacturing information) is sorted by type and then forwarded to the appropriate tools within the manufacturing facility for processing. By providing the client-specific manufacturing information directly to each manufacturing facility in the final design structure in conjunction with the layout information, the embodiments eliminate the need for independent information gathering by each manufacturing facility.
摘要翻译：公开了一种改进的设计方法的实施例，其结果是集成电路的最终设计结构，不仅包括布局信息，而且包括客户特定制造信息（例如，导入/导出信息，服务请求，处理指令，采购订单要求，设计规则信息等）以相同的数据格式分层格式。还公开了制造控制方法和系统的实施例。在这些实施例中，诸如上述的最终设计结构在磁带入口处被接收。其中包含的信息（特别是客户特定的制造信息）按类型排序，然后转发到制造设施内的适当工具进行处理。结合布局信息，通过在终端设计结构中直接向每个制造设施提供特定于客户的制造信息，实施例消除了对每个制造设备的独立信息收集的需要。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式