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1. 发明申请

US20070194385A1 GATE STACKS 有权
标题翻译：门盖
公开(公告)号：US20070194385A1
公开(公告)日：2007-08-23
申请号：US11463039
申请日：2006-08-08
申请人： Dale W. Martin , Steven M. Shank , Michael C. Triplett , Deborah A. Tucker
发明人： Dale W. Martin , Steven M. Shank , Michael C. Triplett , Deborah A. Tucker
IPC分类号： H01L29/94
CPC分类号： H01L21/28247 , H01L21/28035 , H01L29/4916 , Y10S257/90
摘要： A gate stack structure. The structure includes (a) a semiconductor region and (b) a gate stack on top of the semiconductor region. The gate stack includes (i) a gate dielectric region on top of the semiconductor region, (ii) a first gate polysilicon region on top of the gate dielectric region, and (iii) a second gate polysilicon region on top of the first gate polysilicon region and doped with a type of dopants. The structure further includes (c) a diffusion barrier region and a spacer oxide region on a side wall of the gate stack. The diffusion barrier region (i) is sandwiched between the gate stack and the spacer oxide region and (ii) is in direct physical contact with both the first and second gate polysilicon regions, and (iii) comprises a material having a property of preventing a diffusion of oxygen-containing materials through the diffusion barrier region.
摘要翻译：门堆栈结构。该结构包括（a）半导体区域和（b）在半导体区域的顶部上的栅极堆叠。栅极堆叠包括（i）在半导体区域的顶部上的栅极电介质区域，（ii）位于栅极电介质区域顶部的第一栅极多晶硅区域，以及（iii）位于第一栅极多晶硅顶部的第二栅极多晶硅区域并掺杂一种掺杂剂。该结构还包括（c）栅叠层的侧壁上的扩散阻挡区和间隔氧化物区。扩散阻挡区域（i）夹在栅极叠层和间隔氧化物区域之间，（ii）与第一和第二栅极多晶硅区域直接物理接触，并且（iii）包括具有防止含氧材料通过扩散阻挡区扩散。

2. 发明授权

US07205216B2 Modification of electrical properties for semiconductor wafers 失效
标题翻译：半导体晶圆的电性能的改进
公开(公告)号：US07205216B2
公开(公告)日：2007-04-17
申请号：US10710700
申请日：2004-07-29
申请人： Casey J. Grant , Heidi L. Greer , Steven M. Shank , Michael C. Triplett
发明人： Casey J. Grant , Heidi L. Greer , Steven M. Shank , Michael C. Triplett
IPC分类号： H01L21/20 , H01L21/31
CPC分类号： H01L21/324 , H01L22/20
摘要： A method and structure for fabricating semiconductor wafers. The method comprises providing a plurality of semiconductor wafers. The plurality of semiconductor wafers comprises a first semiconductor wafer and a second semiconductor wafer. The first semiconductor wafer is located adjacent to the second semiconductor wafer. A relationship is provided between a plurality of values for an electrical characteristic and a plurality of materials. A material is chosen from the plurality of materials existing in the relationship. A substructure is formed comprising the material sandwiched between a topside of the first semiconductor wafer and a backside of a portion of the of the second semiconductor wafer. The plurality of semiconductor wafers are placed into a furnace comprising an elevated temperature for processing resulting in a value for the first semiconductor wafer of the electrical characteristic that corresponds to said material in said relationship.
摘要翻译：一种用于制造半导体晶片的方法和结构。该方法包括提供多个半导体晶片。多个半导体晶片包括第一半导体晶片和第二半导体晶片。第一半导体晶片位于第二半导体晶片附近。在电特性和多种材料的多个值之间提供关系。从存在于该关系中的多种材料中选择材料。形成了包括夹在第一半导体晶片的顶侧和第二半导体晶片的一部分的背面之间的材料的子结构。将多个半导体晶片放置在包括用于处理的升高的温度的炉中，从而产生与所述关系中的所述材料对应的电特性的第一半导体晶片的值。

3. 发明授权

US07521748B2 Method to eliminate arsenic contamination in trench capacitors 失效
标题翻译：消除沟槽电容器中砷污染的方法
公开(公告)号：US07521748B2
公开(公告)日：2009-04-21
申请号：US11875503
申请日：2007-10-19
申请人： Marshall J. Fleming, Jr. , Mousa H. Ishaq , Steven M. Shank , Michael C. Triplett
发明人： Marshall J. Fleming, Jr. , Mousa H. Ishaq , Steven M. Shank , Michael C. Triplett
IPC分类号： H01L27/108
CPC分类号： H01L27/1087 , H01L29/66181 , H01L29/945
摘要： A trench capacitor structure in which arsenic contamination is substantially reduced and/or essentially eliminated from diffusing into a semiconductor substrate along sidewalls of a trench opening having a high aspect ratio is provided. The present invention also provides a method of fabricating such a trench capacitor structure as well as a method for detecting the arsenic contamination during the drive-in annealing step. The detection of arsenic for product running through the manufacturing lines uses the effect of arsenic enhanced oxidation. That is, the high temperature oxidation anneal used to drive arsenic into the semiconductor substrate is monitored for thickness. For large levels of arsenic outdiffusion, the oxidation rate will increase resulting in a thicker oxide layer. If such an event is detected, the product that has been through the process steps to form the buried plate up to the drive-in anneal, can be reworked to reduce arsenic contamination.
摘要翻译：提供了一种沟槽电容器结构，其中砷污染被基本上减少和/或基本上从通过具有高纵横比的沟槽开口的侧壁扩散到半导体衬底中被消除。本发明还提供一种制造这种沟槽电容器结构的方法以及在驱动退火步骤期间检测砷污染的方法。通过生产线运行的产品中砷的检测采用砷增强氧化的作用。也就是说，监测用于将砷驱入半导体衬底的高温氧化退火的厚度。对于大量的砷扩散，氧化速率将增加，导致较厚的氧化物层。如果检测到这样的事件，则可以重新加工已经通过工艺步骤形成掩埋板直到驱动退火的产品，以减少砷的污染。

4. 发明授权

US07378712B2 Gate stacks 有权
标题翻译：门堆叠
公开(公告)号：US07378712B2
公开(公告)日：2008-05-27
申请号：US11463039
申请日：2006-08-08
申请人： Dale W. Martin , Steven M. Shank , Michael C. Triplett , Deborah A. Tucker
发明人： Dale W. Martin , Steven M. Shank , Michael C. Triplett , Deborah A. Tucker
IPC分类号： H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113 , H01L31/119
CPC分类号： H01L21/28247 , H01L21/28035 , H01L29/4916 , Y10S257/90
摘要： A gate stack structure. The structure includes (a) a semiconductor region and (b) a gate stack on top of the semiconductor region. The gate stack includes (i) a gate dielectric region on top of the semiconductor region, (ii) a first gate polysilicon region on top of the gate dielectric region, and (iii) a second gate polysilicon region on top of the first gate polysilicon region and doped with a type of dopants. The structure further includes (c) a diffusion barrier region and a spacer oxide region on a side wall of the gate stack. The diffusion barrier region (i) is sandwiched between the gate stack and the spacer oxide region and (ii) is in direct physical contact with both the first and second gate polysilicon regions, and (iii) comprises a material having a property of preventing a diffusion of oxygen-containing materials through the diffusion barrier region.
摘要翻译：门堆栈结构。该结构包括（a）半导体区域和（b）在半导体区域的顶部上的栅极堆叠。栅极堆叠包括（i）在半导体区域的顶部上的栅极电介质区域，（ii）位于栅极电介质区域顶部的第一栅极多晶硅区域，以及（iii）位于第一栅极多晶硅顶部的第二栅极多晶硅区域并掺杂一种掺杂剂。该结构还包括（c）栅叠层的侧壁上的扩散阻挡区和间隔氧化物区。扩散阻挡区域（i）夹在栅极叠层和间隔氧化物区域之间，（ii）与第一和第二栅极多晶硅区域直接物理接触，并且（iii）包括具有防止含氧材料通过扩散阻挡区扩散。

5. 发明授权

US07294554B2 Method to eliminate arsenic contamination in trench capacitors 失效
标题翻译：消除沟槽电容器中砷污染的方法
公开(公告)号：US07294554B2
公开(公告)日：2007-11-13
申请号：US11276024
申请日：2006-02-10
申请人： Marshall J. Fleming, Jr. , Mousa H. Ishaq , Steven M. Shank , Michael C. Triplett
发明人： Marshall J. Fleming, Jr. , Mousa H. Ishaq , Steven M. Shank , Michael C. Triplett
IPC分类号： H01L21/20
CPC分类号： H01L27/1087 , H01L29/66181 , H01L29/945
摘要： A trench capacitor structure in which arsenic contamination is substantially reduced and/or essentially eliminated from diffusing into a semiconductor substrate along sidewalls of a trench opening having a high aspect ratio is provided. The present invention also provides a method of fabricating such a trench capacitor structure as well as a method for detecting the arsenic contamination during the drive-in annealing step. The detection of arsenic for product running through the manufacturing lines uses the effect of arsenic enhanced oxidation. That is, the high temperature oxidation anneal used to drive arsenic into the semiconductor substrate is monitored for thickness. For large levels of arsenic outdiffusion, the oxidation rate will increase resulting in a thicker oxide layer. If such an event is detected, the product that has been through the process steps to form the buried plate up to the drive-in anneal, can be reworked to reduce arsenic contamination.
摘要翻译：提供了一种沟槽电容器结构，其中砷污染被基本上减少和/或基本上从通过具有高纵横比的沟槽开口的侧壁扩散到半导体衬底中被消除。本发明还提供一种制造这种沟槽电容器结构的方法以及在驱动退火步骤期间检测砷污染的方法。通过生产线运行的产品中砷的检测采用砷增强氧化的作用。也就是说，监测用于将砷驱入半导体衬底的高温氧化退火的厚度。对于大量的砷扩散，氧化速率将增加，导致较厚的氧化物层。如果检测到这样的事件，则可以重新加工已经通过工艺步骤形成掩埋板直到驱动退火的产品，以减少砷污染。

6. 发明授权

US06864189B2 Methodology for measuring and controlling film thickness profiles 失效
标题翻译：测量和控制薄膜厚度分布的方法
公开(公告)号：US06864189B2
公开(公告)日：2005-03-08
申请号：US10604148
申请日：2003-06-27
申请人： Timothy S. Hayes , Michael C. Triplett
发明人： Timothy S. Hayes , Michael C. Triplett
IPC分类号： H01L21/66
CPC分类号： H01L22/20 , H01L2924/0002 , H01L2924/00
摘要： A method evaluating an integrated circuit manufacturing process first establishes a “desired” profile of a given film in a prescribed manufacturing process by first recording multiple thickness measures taken at regular intervals along a number of lines crossing a plurality of different sample production runs of the same film formed in the integrated circuit manufacturing process. Next, the invention plots the thickness measures to produce sample film profiles of the film. These sample film profiles are averaged in a statistical process to produce the desired film profile. The desired film profile is compared to an actual production run. If the actual film profile does not match the desired film profile, the integrated circuit manufacturing process used to make the actual film profile can then be adjusted to make the actual film profile match the desired film profile more closely.
摘要翻译：评估集成电路制造过程的方法首先在规定的制造过程中建立给定胶片的“期望”轮廓，首先记录沿着穿过多个不同样品生产运行的多条线的规则间隔采取的多个厚度测量电影在集成电路制造过程中形成。接下来，本发明绘制了制备膜的样品膜轮廓的厚度测量。在统计过程中对这些样品膜分布进行平均以产生所需的膜分布。将所需的胶片轮廓与实际的生产运行进行比较。如果实际的胶片轮廓与期望的胶片轮廓不匹配，则可以调节用于制作实际胶片轮廓的集成电路制造工艺，以使得实际的胶片轮廓更接近地匹配所需的胶片轮廓。

7. 发明授权

US06774019B2 Incorporation of an impurity into a thin film 有权
公开(公告)号：US06774019B2
公开(公告)日：2004-08-10
申请号：US10063846
申请日：2002-05-17
申请人： Charles Augustus Choate, IV , Timothy S. Hayes , Michael Raymond Lunn , Paul R. Nisson , Dean W. Siegel , Michael C. Triplett
发明人： Charles Augustus Choate, IV , Timothy S. Hayes , Michael Raymond Lunn , Paul R. Nisson , Dean W. Siegel , Michael C. Triplett
IPC分类号： C23C1644
CPC分类号： C30B29/06 , C23C16/4485 , C30B25/14
摘要： The present invention describes a method of forming a thin film on a substrate arranged in a deposition system comprising the step of introducing a pre-determined amount of an impurity in a confined volume in the deposition system. One or more gases are introduced into the deposition system for forming the thin film. The impurity is removed from the confined volume in a gas phase during formation of the thin film. The impurity in the gas phase is incorporated into the thin film.

8. 发明授权

US07157341B2 Gate stacks 失效
标题翻译：门堆叠
公开(公告)号：US07157341B2
公开(公告)日：2007-01-02
申请号：US10711742
申请日：2004-10-01
申请人： Dale W. Martin , Steven M. Shank , Michael C. Triplett , Deborah A. Tucker
发明人： Dale W. Martin , Steven M. Shank , Michael C. Triplett , Deborah A. Tucker
IPC分类号： H01L21/336 , H01L21/8238
CPC分类号： H01L21/28247 , H01L21/28035 , H01L29/4916 , Y10S257/90
摘要： A structure and fabrication method for a gate stack used to define source/drain regions in a semiconductor substrate. The method comprises (a) forming a gate dielectric layer on top of the substrate, (b) forming a gate polysilicon layer on top of the gate dielectric layer, (c) implanting n-type dopants in a top layer of the gate polysilicon layer, (d) etching away portions of the gate polysilicon layer and the gate dielectric layer so as to form a gate stack on the substrate, and (e) thermally oxidizing side walls of the gate stack with the presence of a nitrogen-carrying gas. As a result, a diffusion barrier layer is formed at the same depth in the polysilicon material of the gate stack regardless of the doping concentration. Therefore, the n-type doped region of the gate stack has the same width as that of the undoped region of the gate stack.
摘要翻译：用于限定半导体衬底中的源极/漏极区域的栅堆叠的结构和制造方法。该方法包括：（a）在衬底的顶部形成栅介质层，（b）在栅极介电层的顶部形成栅极多晶硅层，（c）在栅极多晶硅层的顶层中注入n型掺杂剂，（d）蚀刻掉栅极多晶硅层和栅极电介质层的部分，以在衬底上形成栅极堆叠，以及（e）在存在氮气的气体下热氧化栅极堆叠的侧壁。结果，无论掺杂浓度如何，在栅叠层的多晶硅材料中，在相同的深度处形成扩散阻挡层。因此，栅极堆叠的n型掺杂区域具有与栅极堆叠的未掺杂区域相同的宽度。

9. 发明授权

US6060397A Gas chemistry for improved in-situ cleaning of residue for a CVD apparatus 失效
标题翻译：用于改善CVD设备残留物原位清洗的气体化学
公开(公告)号：US6060397A
公开(公告)日：2000-05-09
申请号：US502688
申请日：1995-07-14
申请人： Martin Seamons , Cary Ching , Kou Imaoka , Tatsuya Sato , Tirunelveli S. Ravi , Michael C. Triplett
发明人： Martin Seamons , Cary Ching , Kou Imaoka , Tatsuya Sato , Tirunelveli S. Ravi , Michael C. Triplett
IPC分类号： C23C16/44 , C23C16/56 , H01L21/203 , H01L21/205 , H01L21/304 , H01L21/31 , H01L21/00
CPC分类号： C23C16/4405 , Y10S438/905
摘要： A method (100) of cleaning residues from a chemical vapor deposition apparatus (10) is provided. The present method (100) includes introducing into a chamber (12) cleaning gases such as N.sub.2, C.sub.2 F.sub.6, and O.sub.2, and forming a plasma from the cleaning gases. The present method also includes removing residues from interior surfaces of the chamber 12 by forming a volatile product from the residues and at least one of the cleaning gases.
摘要翻译：提供了从化学气相沉积装置（10）清洗残留物的方法（100）。本方法（100）包括将清洁气体如N 2，C 2 F 6和O 2的腔室（12）引入并从清洗气体形成等离子体。本方法还包括通过从残余物和至少一种清洁气体形成挥发性产物来从室12的内表面去除残留物。

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