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1. 发明授权

US07650552B2 Apparatus and method for detecting and recovering errors caused by electrostatic discharge 有权
标题翻译：用于检测和恢复由静电放电引起的误差的装置和方法
公开(公告)号：US07650552B2
公开(公告)日：2010-01-19
申请号：US11278199
申请日：2006-03-31
申请人： Fariborz Pourbigharaz , Milivoje Aleksic , Carl Mizuyabu , Aris Balatsos , Zeeshan Syed
发明人： Fariborz Pourbigharaz , Milivoje Aleksic , Carl Mizuyabu , Aris Balatsos , Zeeshan Syed
IPC分类号： G01R31/28
CPC分类号： G06F11/0751 , G06F11/0742
摘要： A method and apparatus for detecting an error compares a hardwired reference value to a corresponding predetermined value and generates an error indication in response to a change in the predetermined value. In one embodiment, the predetermined value is set to be the same as the hardwired reference value and in response to an electrostatic discharge event or any other suitable cause of error, the predetermined value changes so that a comparison indicates that an error has occurred. An error indication is then generated which may be, for example, an interrupt to recovery logic that generates recovery control information to reset a functional block that was corrupted or to perform in an entire chip reset if desired.
摘要翻译：用于检测错误的方法和装置将硬连线参考值与对应的预定值进行比较，并响应于预定值的变化而产生错误指示。在一个实施例中，将预定值设置为与硬连线参考值相同，并且响应于静电放电事件或任何其它合适的错误原因，预定值改变，使得比较指示发生错误。然后产生错误指示，其可以是例如产生恢复控制信息的恢复逻辑的中断，以恢复被破坏的功能块或者如果需要在整个芯片复位中执行。

2. 发明申请

US20070250750A1 ERROR DETECTION APPARATUS AND METHOD 有权
标题翻译：错误检测装置和方法
公开(公告)号：US20070250750A1
公开(公告)日：2007-10-25
申请号：US11278199
申请日：2006-03-31
申请人： Fariborz Pourbigharaz , Milivoje Aleksic , Carl Mizuyabu , Aris Balatsos , Zeeshan Syed
发明人： Fariborz Pourbigharaz , Milivoje Aleksic , Carl Mizuyabu , Aris Balatsos , Zeeshan Syed
IPC分类号： H04L1/00 , H03M13/00 , G08C25/00 , G06F11/00 , G06F11/30
CPC分类号： G06F11/0751 , G06F11/0742
摘要： A method and apparatus for detecting an error compares a hardwired reference value to a corresponding predetermined value and generates an error indication in response to a change in the predetermined value. In one embodiment, the predetermined value is set to be the same as the hardwired reference value and in response to an electrostatic discharge event or any other suitable cause of error, the predetermined value changes so that a comparison indicates that an error has occurred. An error indication is then generated which may be, for example, an interrupt to recovery logic that generates recovery control information to reset a functional block that was corrupted or to perform in an entire chip reset if desired.
摘要翻译：用于检测错误的方法和装置将硬连线参考值与对应的预定值进行比较，并响应于预定值的变化而产生错误指示。在一个实施例中，将预定值设置为与硬连线参考值相同，并且响应于静电放电事件或任何其它合适的错误原因，预定值改变，使得比较指示发生错误。然后产生错误指示，其可以是例如产生恢复控制信息的恢复逻辑的中断，以恢复被破坏的功能块或者如果需要在整个芯片复位中执行。

3. 发明授权

US07929648B2 Clock error detection apparatus and method 有权
标题翻译：时钟误差检测装置及方法
公开(公告)号：US07929648B2
公开(公告)日：2011-04-19
申请号：US11278221
申请日：2006-03-31
申请人： Fariborz Pourbigharaz , Milivoje Aleksic , Carl Mizuyabu , Aris Balatsos
发明人： Fariborz Pourbigharaz , Milivoje Aleksic , Carl Mizuyabu , Aris Balatsos
IPC分类号： H04L27/06
CPC分类号： H04L7/0083
摘要： An error detection apparatus and method compares a first hardwired value such as a first clock threshold, and a second hardwired value such as a second clock threshold, and generates an indication that there is an error in a clock signal based on a comparison of the first hardwired value and the second hardwired value to the clock signal. If an error is detected, the error detection apparatus will, for example, interrupt clock recovery logic to take proper action for recovery of a clock generation circuit that generated the clock signal. The clock signal may be generated based on, for example, a reference clock signal that may be provided by an external source clock, or any other suitable source.
摘要翻译：错误检测装置和方法比较第一硬连线值（例如第一时钟阈值）和第二硬连线值（例如第二时钟阈值），并且基于第一时钟阈值的比较生成时钟信号中存在错误的指示硬连线值和第二个硬连线值到时钟信号。如果检测到错误，则错误检测装置将例如中断时钟恢复逻辑以采取适当的动作来恢复生成时钟信号的时钟产生电路。时钟信号可以基于例如可由外部源时钟提供的参考时钟信号或任何其它合适的源来产生。

4. 发明申请

US20070230647A1 CLOCK ERROR DETECTION APPARATUS AND METHOD 有权
标题翻译：时钟错误检测装置和方法
公开(公告)号：US20070230647A1
公开(公告)日：2007-10-04
申请号：US11278221
申请日：2006-03-31
申请人： Fariborz Pourbigharaz , Milivoje Aleksic , Carl Mizuyabu , Aris Balatsos
发明人： Fariborz Pourbigharaz , Milivoje Aleksic , Carl Mizuyabu , Aris Balatsos
IPC分类号： H04L7/00
CPC分类号： H04L7/0083
摘要： An error detection apparatus and method compares a first hardwired value such as a first clock threshold, and a second hardwired value such as a second clock threshold, and generates an indication that there is an error in a clock signal based on a comparison of the first hardwired value and the second hardwired value to the clock signal. If an error is detected, the error detection apparatus will, for example, interrupt clock recovery logic to take proper action for recovery of a clock generation circuit that generated the clock signal. The clock signal may be generated based on, for example, a reference clock signal that may be provided by an external source clock, or any other suitable source.
摘要翻译：错误检测装置和方法比较第一硬连线值（例如第一时钟阈值）和第二硬连线值（例如第二时钟阈值），并且基于第一时钟阈值的比较生成时钟信号中存在错误的指示硬连线值和第二个硬连线值到时钟信号。如果检测到错误，则错误检测装置将例如中断时钟恢复逻辑以采取适当的动作来恢复生成时钟信号的时钟产生电路。时钟信号可以基于例如可由外部源时钟提供的参考时钟信号或任何其它合适的源来产生。

5. 发明授权

US07937519B2 Lane merging 有权
标题翻译：车道合并
公开(公告)号：US07937519B2
公开(公告)日：2011-05-03
申请号：US12500764
申请日：2009-07-10
申请人： Sergiu Goma , Fariborz Pourbigharaz , Milivoje Aleksic
发明人： Sergiu Goma , Fariborz Pourbigharaz , Milivoje Aleksic
IPC分类号： G06F13/36 , G06F3/00 , G06F13/00 , G06F1/32
CPC分类号： G06F13/4018 , Y02D10/14 , Y02D10/151
摘要： A buffer is associated with each of a plurality of data lanes of a multi-lane serial data bus. Data words are timed through the buffers of active ones of the data lanes. Words timed through buffers of active data lanes are merged onto a parallel bus such that data words from each of the active data lanes are merged onto the parallel bus in a pre-defined repeating sequence of data lanes. This approach allows other, non-active, data lanes to remain in a power conservation state.
摘要翻译：缓冲器与多通道串行数据总线的多个数据通道中的每一条相关联。数据字通过数据通道中的活动缓冲区进行定时。通过活动数据通道的缓冲器定时的字被合并到并行总线上，使得来自每个活动数据通道的数据字以预定义的数据通道重复序列合并到并行总线上。这种方法允许其他非活动的数据通道保持在省电状态。

6. 发明申请

US20090276558A1 LANE MERGING 有权
公开(公告)号：US20090276558A1
公开(公告)日：2009-11-05
申请号：US12500764
申请日：2009-07-10
申请人： Sergiu Goma , Fariborz Pourbigharaz , Milivoje Aleksic
发明人： Sergiu Goma , Fariborz Pourbigharaz , Milivoje Aleksic
IPC分类号： G06F13/36 , G06F13/00
CPC分类号： G06F13/4018 , Y02D10/14 , Y02D10/151
摘要： A buffer is associated with each of a plurality of data lanes of a multi-lane serial data bus. Data words are timed through the buffers of active ones of the data lanes. Words timed through buffers of active data lanes are merged onto a parallel bus such that data words from each of the active data lanes are merged onto the parallel bus in a pre-defined repeating sequence of data lanes. This approach allows other, non-active, data lanes to remain in a power conservation state.
摘要翻译：缓冲器与多通道串行数据总线的多个数据通道中的每一条相关联。数据字通过数据通道中的活动缓冲区进行定时。通过活动数据通道的缓冲器定时的字被合并到并行总线上，使得来自每个活动数据通道的数据字以预定义的数据通道重复序列合并到并行总线上。这种方法允许其他非活动的数据通道保持在省电状态。

7. 发明申请

US20130010168A1 GRAPHICS MULTI-MEDIA IC AND METHOD OF ITS OPERATION 有权
标题翻译：图形多媒体IC及其操作方法
公开(公告)号：US20130010168A1
公开(公告)日：2013-01-10
申请号：US13495518
申请日：2012-06-13
申请人： Fariborz Pourbigharaz , Sergiu Goma , Milivoje Aleksic , Andrzej Mamona
发明人： Fariborz Pourbigharaz , Sergiu Goma , Milivoje Aleksic , Andrzej Mamona
IPC分类号： G06F13/14 , H04N5/222
CPC分类号： G09G5/363 , G06F3/14 , G09G5/006 , G09G5/39 , G09G2330/021 , G09G2360/06 , G09G2370/04 , G09G2370/10 , H04N1/00278
摘要： A graphics multi-media integrated circuit (GMIC) is connected to a host processor over two serial links: a half duplex bi-directional serial link which accords to a display serial interface protocol, and a uni-directional serial link which accords to a camera serial interface protocol. The GMIC receives packets from the host over the half duplex bi-directional serial link and processes these packets. The GMIC sends packets over the uni-directional serial link. A packet from the host can request a processing operation by the GMIC or can initiate a memory operation at the memory of the GMIC. The GMIC can also send packets to the host to initiate a host memory operation and may be connected to a display over a bi-directional serial link and to a camera over a uni-directional serial link and a bi-directional control link allowing the host to control the display and camera.
摘要翻译：图形多媒体集成电路（GMIC）通过两个串行链路连接到主处理器：符合显示串行接口协议的半双工双向串行链路和符合相机的单向串行链路串行接口协议 GMIC通过半双工双向串行链路从主机接收数据包，并处理这些数据包。 GMIC通过单向串行链路发送数据包。来自主机的分组可以请求GMIC的处理操作，或者可以在GMIC的存储器处启动存储器操作。 GMIC还可以向主机发送数据包以启动主机存储器操作，并且可以通过双向串行链路连接到显示器，并且可以通过单向串行链路和允许主机的双向控制链路连接到摄像机来控制显示器和相机。

8. 发明申请

US20100185800A1 COMMUNICATION PROTOCOL FOR SHARING MEMORY RESOURCES BETWEEN COMPONENTS OF A DEVICE 有权
标题翻译：用于在设备的组件之间共享存储资源的通信协议
公开(公告)号：US20100185800A1
公开(公告)日：2010-07-22
申请号：US12356898
申请日：2009-01-21
申请人： Fariborz Pourbigharaz , Milivoje Aleksic
发明人： Fariborz Pourbigharaz , Milivoje Aleksic
IPC分类号： G06F13/00
CPC分类号： G06F13/404
摘要： In a device, such as a cell phone, memory resource sharing is enabled between components, such as integrated circuits, each of which has memory resources. This may be accomplished by providing an interconnect between the components and constructing transaction units which are sent over the interconnect to initiate memory access operations. The approach may also be used to allow for a degree of communication between device components.
摘要翻译：在诸如蜂窝电话的设备中，在诸如具有存储器资源的集成电路的组件之间启用存储器资源共享。这可以通过在组件之间提供互连并构建通过互连发送以发起存储器访问操作的事务单元来实现。该方法还可以用于允许设备组件之间的一定程度的通信。

9. 发明授权

US08223796B2 Graphics multi-media IC and method of its operation 有权
标题翻译：图形多媒体IC及其操作方法
公开(公告)号：US08223796B2
公开(公告)日：2012-07-17
申请号：US12141358
申请日：2008-06-18
申请人： Fariborz Pourbigharaz , Sergiu Goma , Milivoje Aleksic , Andrzej Mamona
发明人： Fariborz Pourbigharaz , Sergiu Goma , Milivoje Aleksic , Andrzej Mamona
IPC分类号： H04J3/16
CPC分类号： G09G5/363 , G06F3/14 , G09G5/006 , G09G5/39 , G09G2330/021 , G09G2360/06 , G09G2370/04 , G09G2370/10 , H04N1/00278
摘要： A graphics multi-media integrated circuit (GMIC) is connected to a host processor over two serial links: a half duplex bi-directional serial link which accords to a protocol defined for a display serial interface, and a uni-directional serial link which accords to a compatible protocol defined for a camera serial interface. The GMIC receives packets according to the protocol from the host over the half duplex bi-directional serial link and processes these packets. The GMIC sends packets according to the protocol to the host over the uni-directional serial link. A packet from the host can request a processing operation by the GMIC or can initiate a memory operation at the memory of the GMIC. The GMIC can also send packets to the host to initiate a memory operation at the memory of the host. The GMIC may be connected to a display over a bi-directional serial link according to the display serial interface protocol and to a camera over a uni-directional serial link and a bi-directional control link according to the camera serial interface so that the host controls the display and camera indirectly through the GMIC.
摘要翻译：图形多媒体集成电路（GMIC）通过两个串行链路连接到主处理器：符合为显示串行接口定义的协议的半双工双向串行链路和符合协议的单向串行链路到为相机串行接口定义的兼容协议。 GMIC根据通过半双工双向串行链路的主机的协议接收数据包，并处理这些数据包。 GMIC根据协议将数据包通过单向串行链路发送到主机。来自主机的分组可以请求GMIC的处理操作，或者可以在GMIC的存储器处启动存储器操作。 GMIC还可以向主机发送数据包，以在主机的内存中启动内存操作。 GMIC可以根据显示串行接口协议通过双向串行链路连接到显示器，并且可以根据相机串行接口通过单向串行链路和双向控制链路连接到相机，使得主机通过GMIC间接控制显示和相机。

10. 发明申请

US20070079047A1 LANE MERGING 有权
公开(公告)号：US20070079047A1
公开(公告)日：2007-04-05
申请号：US11536365
申请日：2006-09-28
申请人： Sergiu Goma , Fariborz Pourbigharaz , Milivoje Aleksic
发明人： Sergiu Goma , Fariborz Pourbigharaz , Milivoje Aleksic
IPC分类号： G06F13/00
CPC分类号： G06F13/4018 , Y02D10/14 , Y02D10/151
摘要： A buffer is associated with each of a plurality of data lanes of a multi-lane serial data bus. Data words are timed through the buffers of active ones of the data lanes. Words timed through buffers of active data lanes are merged onto a parallel bus such that data words from each of the active data lanes are merged onto the parallel bus in a pre-defined repeating sequence of data lanes. This approach allows other, non-active, data lanes to remain in a power conservation state.
摘要翻译：缓冲器与多通道串行数据总线的多个数据通道中的每一条相关联。数据字通过数据通道中的活动缓冲区进行定时。通过活动数据通道的缓冲器定时的字被合并到并行总线上，使得来自每个活动数据通道的数据字以预定义的数据通道重复序列合并到并行总线上。这种方法允许其他非活动数据通道保持在功率节省状态。

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