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1. 发明申请

US20130010168A1 GRAPHICS MULTI-MEDIA IC AND METHOD OF ITS OPERATION 有权
标题翻译：图形多媒体IC及其操作方法
公开(公告)号：US20130010168A1
公开(公告)日：2013-01-10
申请号：US13495518
申请日：2012-06-13
申请人： Fariborz Pourbigharaz , Sergiu Goma , Milivoje Aleksic , Andrzej Mamona
发明人： Fariborz Pourbigharaz , Sergiu Goma , Milivoje Aleksic , Andrzej Mamona
IPC分类号： G06F13/14 , H04N5/222
CPC分类号： G09G5/363 , G06F3/14 , G09G5/006 , G09G5/39 , G09G2330/021 , G09G2360/06 , G09G2370/04 , G09G2370/10 , H04N1/00278
摘要： A graphics multi-media integrated circuit (GMIC) is connected to a host processor over two serial links: a half duplex bi-directional serial link which accords to a display serial interface protocol, and a uni-directional serial link which accords to a camera serial interface protocol. The GMIC receives packets from the host over the half duplex bi-directional serial link and processes these packets. The GMIC sends packets over the uni-directional serial link. A packet from the host can request a processing operation by the GMIC or can initiate a memory operation at the memory of the GMIC. The GMIC can also send packets to the host to initiate a host memory operation and may be connected to a display over a bi-directional serial link and to a camera over a uni-directional serial link and a bi-directional control link allowing the host to control the display and camera.
摘要翻译：图形多媒体集成电路（GMIC）通过两个串行链路连接到主处理器：符合显示串行接口协议的半双工双向串行链路和符合相机的单向串行链路串行接口协议 GMIC通过半双工双向串行链路从主机接收数据包，并处理这些数据包。 GMIC通过单向串行链路发送数据包。来自主机的分组可以请求GMIC的处理操作，或者可以在GMIC的存储器处启动存储器操作。 GMIC还可以向主机发送数据包以启动主机存储器操作，并且可以通过双向串行链路连接到显示器，并且可以通过单向串行链路和允许主机的双向控制链路连接到摄像机来控制显示器和相机。

2. 发明授权

US08223796B2 Graphics multi-media IC and method of its operation 有权
标题翻译：图形多媒体IC及其操作方法
公开(公告)号：US08223796B2
公开(公告)日：2012-07-17
申请号：US12141358
申请日：2008-06-18
申请人： Fariborz Pourbigharaz , Sergiu Goma , Milivoje Aleksic , Andrzej Mamona
发明人： Fariborz Pourbigharaz , Sergiu Goma , Milivoje Aleksic , Andrzej Mamona
IPC分类号： H04J3/16
CPC分类号： G09G5/363 , G06F3/14 , G09G5/006 , G09G5/39 , G09G2330/021 , G09G2360/06 , G09G2370/04 , G09G2370/10 , H04N1/00278
摘要： A graphics multi-media integrated circuit (GMIC) is connected to a host processor over two serial links: a half duplex bi-directional serial link which accords to a protocol defined for a display serial interface, and a uni-directional serial link which accords to a compatible protocol defined for a camera serial interface. The GMIC receives packets according to the protocol from the host over the half duplex bi-directional serial link and processes these packets. The GMIC sends packets according to the protocol to the host over the uni-directional serial link. A packet from the host can request a processing operation by the GMIC or can initiate a memory operation at the memory of the GMIC. The GMIC can also send packets to the host to initiate a memory operation at the memory of the host. The GMIC may be connected to a display over a bi-directional serial link according to the display serial interface protocol and to a camera over a uni-directional serial link and a bi-directional control link according to the camera serial interface so that the host controls the display and camera indirectly through the GMIC.
摘要翻译：图形多媒体集成电路（GMIC）通过两个串行链路连接到主处理器：符合为显示串行接口定义的协议的半双工双向串行链路和符合协议的单向串行链路到为相机串行接口定义的兼容协议。 GMIC根据通过半双工双向串行链路的主机的协议接收数据包，并处理这些数据包。 GMIC根据协议将数据包通过单向串行链路发送到主机。来自主机的分组可以请求GMIC的处理操作，或者可以在GMIC的存储器处启动存储器操作。 GMIC还可以向主机发送数据包，以在主机的内存中启动内存操作。 GMIC可以根据显示串行接口协议通过双向串行链路连接到显示器，并且可以根据相机串行接口通过单向串行链路和双向控制链路连接到相机，使得主机通过GMIC间接控制显示和相机。

3. 发明申请

US20070079047A1 LANE MERGING 有权
公开(公告)号：US20070079047A1
公开(公告)日：2007-04-05
申请号：US11536365
申请日：2006-09-28
申请人： Sergiu Goma , Fariborz Pourbigharaz , Milivoje Aleksic
发明人： Sergiu Goma , Fariborz Pourbigharaz , Milivoje Aleksic
IPC分类号： G06F13/00
CPC分类号： G06F13/4018 , Y02D10/14 , Y02D10/151
摘要： A buffer is associated with each of a plurality of data lanes of a multi-lane serial data bus. Data words are timed through the buffers of active ones of the data lanes. Words timed through buffers of active data lanes are merged onto a parallel bus such that data words from each of the active data lanes are merged onto the parallel bus in a pre-defined repeating sequence of data lanes. This approach allows other, non-active, data lanes to remain in a power conservation state.
摘要翻译：缓冲器与多通道串行数据总线的多个数据通道中的每一条相关联。数据字通过数据通道中的活动缓冲区进行定时。通过活动数据通道的缓冲器定时的字被合并到并行总线上，使得来自每个活动数据通道的数据字以预定义的数据通道重复序列合并到并行总线上。这种方法允许其他非活动数据通道保持在功率节省状态。

4. 发明授权

US08873581B2 Graphics multi-media IC and method of its operation 有权
标题翻译：图形多媒体IC及其操作方法
公开(公告)号：US08873581B2
公开(公告)日：2014-10-28
申请号：US13495518
申请日：2012-06-13
申请人： Fariborz Pourbigharaz , Sergiu Goma , Milivoje Aleksic , Andrzej Mamona
发明人： Fariborz Pourbigharaz , Sergiu Goma , Milivoje Aleksic , Andrzej Mamona
IPC分类号： H04L12/42 , G09G5/00 , G06F3/14 , G09G5/39 , H04N1/00 , G09G5/36
CPC分类号： G09G5/363 , G06F3/14 , G09G5/006 , G09G5/39 , G09G2330/021 , G09G2360/06 , G09G2370/04 , G09G2370/10 , H04N1/00278
摘要： A graphics multi-media integrated circuit (GMIC) is connected to a host processor over two serial links: a half duplex bi-directional serial link which accords to a display serial interface protocol, and a uni-directional serial link which accords to a camera serial interface protocol. The GMIC receives packets from the host over the half duplex bi-directional serial link and processes these packets. The GMIC sends packets over the uni-directional serial link. A packet from the host can request a processing operation by the GMIC or can initiate a memory operation at the memory of the GMIC. The GMIC can also send packets to the host to initiate a host memory operation and may be connected to a display over a bi-directional serial link and to a camera over a uni-directional serial link and a bi-directional control link allowing the host to control the display and camera.
摘要翻译：图形多媒体集成电路（GMIC）通过两个串行链路连接到主处理器：符合显示串行接口协议的半双工双向串行链路和符合相机的单向串行链路串行接口协议 GMIC通过半双工双向串行链路从主机接收数据包，并处理这些数据包。 GMIC通过单向串行链路发送数据包。来自主机的分组可以请求GMIC的处理操作，或者可以在GMIC的存储器处启动存储器操作。 GMIC还可以向主机发送数据包以启动主机存储器操作，并且可以通过双向串行链路连接到显示器，并且可以通过单向串行链路和允许主机的双向控制链路连接到摄像机来控制显示器和相机。

5. 发明授权

US07937519B2 Lane merging 有权
标题翻译：车道合并
公开(公告)号：US07937519B2
公开(公告)日：2011-05-03
申请号：US12500764
申请日：2009-07-10
申请人： Sergiu Goma , Fariborz Pourbigharaz , Milivoje Aleksic
发明人： Sergiu Goma , Fariborz Pourbigharaz , Milivoje Aleksic
IPC分类号： G06F13/36 , G06F3/00 , G06F13/00 , G06F1/32
CPC分类号： G06F13/4018 , Y02D10/14 , Y02D10/151
摘要： A buffer is associated with each of a plurality of data lanes of a multi-lane serial data bus. Data words are timed through the buffers of active ones of the data lanes. Words timed through buffers of active data lanes are merged onto a parallel bus such that data words from each of the active data lanes are merged onto the parallel bus in a pre-defined repeating sequence of data lanes. This approach allows other, non-active, data lanes to remain in a power conservation state.
摘要翻译：缓冲器与多通道串行数据总线的多个数据通道中的每一条相关联。数据字通过数据通道中的活动缓冲区进行定时。通过活动数据通道的缓冲器定时的字被合并到并行总线上，使得来自每个活动数据通道的数据字以预定义的数据通道重复序列合并到并行总线上。这种方法允许其他非活动的数据通道保持在省电状态。

6. 发明申请

US20090276558A1 LANE MERGING 有权
公开(公告)号：US20090276558A1
公开(公告)日：2009-11-05
申请号：US12500764
申请日：2009-07-10
申请人： Sergiu Goma , Fariborz Pourbigharaz , Milivoje Aleksic
发明人： Sergiu Goma , Fariborz Pourbigharaz , Milivoje Aleksic
IPC分类号： G06F13/36 , G06F13/00
CPC分类号： G06F13/4018 , Y02D10/14 , Y02D10/151
摘要： A buffer is associated with each of a plurality of data lanes of a multi-lane serial data bus. Data words are timed through the buffers of active ones of the data lanes. Words timed through buffers of active data lanes are merged onto a parallel bus such that data words from each of the active data lanes are merged onto the parallel bus in a pre-defined repeating sequence of data lanes. This approach allows other, non-active, data lanes to remain in a power conservation state.
摘要翻译：缓冲器与多通道串行数据总线的多个数据通道中的每一条相关联。数据字通过数据通道中的活动缓冲区进行定时。通过活动数据通道的缓冲器定时的字被合并到并行总线上，使得来自每个活动数据通道的数据字以预定义的数据通道重复序列合并到并行总线上。这种方法允许其他非活动的数据通道保持在省电状态。

7. 发明申请

US20090315899A1 GRAPHICS MULTI-MEDIA IC AND METHOD OF ITS OPERATION 有权
标题翻译：图形多媒体IC及其操作方法
公开(公告)号：US20090315899A1
公开(公告)日：2009-12-24
申请号：US12141358
申请日：2008-06-18
申请人： Fariborz Pourbigharaz , Sergiu Goma , Milivoje Aleksic , Andrzej Mamona
发明人： Fariborz Pourbigharaz , Sergiu Goma , Milivoje Aleksic , Andrzej Mamona
IPC分类号： G06T1/00 , G06F13/14
CPC分类号： G09G5/363 , G06F3/14 , G09G5/006 , G09G5/39 , G09G2330/021 , G09G2360/06 , G09G2370/04 , G09G2370/10 , H04N1/00278
摘要： A graphics multi-media integrated circuit (GMIC) is connected to a host processor over two serial links: a half duplex bi-directional serial link which accords to a protocol defined for a display serial interface, and a uni-directional serial link which accords to a compatible protocol defined for a camera serial interface. The GMIC receives packets according to the protocol from the host over the half duplex bi-directional serial link and processes these packets. The GMIC sends packets according to the protocol to the host over the uni-directional serial link. A packet from the host can request a processing operation by the GMIC or can initiate a memory operation at the memory of the GMIC. The GMIC can also send packets to the host to initiate a memory operation at the memory of the host. The GMIC may be connected to a display over a bi-directional serial link according to the display serial interface protocol and to a camera over a uni-directional serial link and a bi-directional control link according to the camera serial interface so that the host controls the display and camera indirectly through the GMIC.
摘要翻译：图形多媒体集成电路（GMIC）通过两个串行链路连接到主处理器：符合为显示串行接口定义的协议的半双工双向串行链路和符合协议的单向串行链路到为相机串行接口定义的兼容协议。 GMIC根据通过半双工双向串行链路的主机的协议接收数据包，并处理这些数据包。 GMIC根据协议将数据包通过单向串行链路发送到主机。来自主机的分组可以请求GMIC的处理操作，或者可以在GMIC的存储器处启动存储器操作。 GMIC还可以向主机发送数据包，以在主机的内存中启动内存操作。 GMIC可以根据显示串行接口协议通过双向串行链路连接到显示器，并且可以根据相机串行接口通过单向串行链路和双向控制链路连接到相机，使得主机通过GMIC间接控制显示和相机。

8. 发明授权

US07571271B2 Lane merging 有权
标题翻译：车道合并
公开(公告)号：US07571271B2
公开(公告)日：2009-08-04
申请号：US11536365
申请日：2006-09-28
申请人： Sergiu Goma , Fariborz Pourbigharaz , Milivoje Aleksic
发明人： Sergiu Goma , Fariborz Pourbigharaz , Milivoje Aleksic
IPC分类号： G06F13/36 , G06F5/00 , G06F1/32
CPC分类号： G06F13/4018 , Y02D10/14 , Y02D10/151
摘要： A buffer is associated with each of a plurality of data lanes of a multi-lane serial data bus. Data words are timed through the buffers of active ones of the data lanes. Words timed through buffers of active data lanes are merged onto a parallel bus such that data words from each of the active data lanes are merged onto the parallel bus in a pre-defined repeating sequence of data lanes. This approach allows other, non-active, data lanes to remain in a power conservation state.
摘要翻译：缓冲器与多通道串行数据总线的多个数据通道中的每一条相关联。数据字通过数据通道中的活动缓冲区进行定时。通过活动数据通道的缓冲器定时的字被合并到并行总线上，使得来自每个活动数据通道的数据字以预定义的数据通道重复序列合并到并行总线上。这种方法允许其他非活动的数据通道保持在省电状态。

9. 发明授权

US08667375B2 Method and apparatus for error management 有权
标题翻译：错误管理方法和装置
公开(公告)号：US08667375B2
公开(公告)日：2014-03-04
申请号：US13367059
申请日：2012-02-06
申请人： Sergiu Goma , Milivoje Aleksic
发明人： Sergiu Goma , Milivoje Aleksic
IPC分类号： H03M13/03
CPC分类号： H04L1/0057 , H03M13/19 , H03M13/27 , H04L1/0083
摘要： To derive a Hamming code to manage data errors a set of at least four parity bit positions is selected for parity bits which will protect a set of data bits (where each data bit has a data bit position in the data bit set). A syndrome is determined for each data bit position. This involves selecting a unique sub-set of at least three parity bit positions. The unique sub-set shares at least one parity bit position with at least one other unique sub-set of at least three parity bit positions. A parity bit value may then be calculated for each parity bit position based on the determined syndromes. The header of a packet may be provided with a word which defines the length of the packet and an error management code generated utilizing this word so that errors in the word may be detected and, possibly, corrected.
摘要翻译：为了导出用于管理数据错误的汉明码，为奇偶校验位选择一组至少四个奇偶校验位位置，这将保护一组数据位（其中每个数据位在数据位集合中具有数据位位置）。确定每个数据位位置的综合征。这涉及选择至少三个奇偶校验位位置的唯一子集。唯一子集与至少一个其他唯一的至少三个奇偶校验位位置的子集共享至少一个奇偶校验位位置。然后可以基于所确定的校正子针对每个奇偶校验位位置计算奇偶校验位值。分组的报头可以被提供有定义分组的长度的单词和使用该单词生成的错误管理代码，从而可以检测单词中的错误并且可能被校正。

10. 发明授权

US07596743B2 Method and apparatus for error management 有权
标题翻译：错误管理方法和装置
公开(公告)号：US07596743B2
公开(公告)日：2009-09-29
申请号：US11236921
申请日：2005-09-28
申请人： Sergiu Goma , Milivoje Aleksic
发明人： Sergiu Goma , Milivoje Aleksic
IPC分类号： H03M13/00
CPC分类号： H04L1/0057 , H03M13/19 , H03M13/27 , H04L1/0083
摘要： To derive a Hamming code to manage data errors a set of at least four parity bit positions is selected for parity bits which will protect a set of data bits (where each data bit has a data bit position in the data bit set). A syndrome is determined for each data bit position. This involves selecting a unique sub-set of at least three parity bit positions. The unique sub-set shares at least one parity bit position with at least one other unique sub-set of at least three parity bit positions. A parity bit value may then be calculated for each parity bit position based on the determined syndromes. The header of a packet may be provided with a word which defines the length of the packet and an error management code generated utilizing this word so that errors in the word may be detected and, possibly, corrected.
摘要翻译：为了导出用于管理数据错误的汉明码，为奇偶校验位选择一组至少四个奇偶校验位位置，这将保护一组数据位（其中每个数据位在数据位集合中具有数据位位置）。确定每个数据位位置的综合征。这涉及选择至少三个奇偶校验位位置的唯一子集。唯一子集与至少一个其他唯一的至少三个奇偶校验位位置的子集共享至少一个奇偶校验位位置。然后可以基于所确定的校正子针对每个奇偶校验位位置计算奇偶校验位值。分组的报头可以被提供有定义分组的长度的单词和使用该单词生成的错误管理代码，从而可以检测单词中的错误并且可能被校正。

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