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1. 发明授权

US07017070B1 Apparatus for synchronization of double data rate signaling 有权
标题翻译：双数据速率信令同步的装置
公开(公告)号：US07017070B1
公开(公告)日：2006-03-21
申请号：US09687858
申请日：2000-10-13
申请人： Chak Cheung Edward Ho , Oleg Drapkin , Carl Mizuyabu , Ray Chau , Gordon Caruk
发明人： Chak Cheung Edward Ho , Oleg Drapkin , Carl Mizuyabu , Ray Chau , Gordon Caruk
IPC分类号： G06F1/12 , G06F1/04
CPC分类号： G06F13/4243 , G11C7/1066 , G11C7/22 , G11C7/222
摘要： A signal phase shifting circuit shifts the phase of an input signal, such as a STROBE signal, based on a reference signal, such as a CLOCK signal, to facilitate, for example, receiving of double data rate data. The signal phase shifting circuit includes a reference signal period dividing circuit having a feedback delay matching array operatively coupled to one of a plurality of voltage control delay lines. This signal phase shifting circuit also includes a variable delay circuit that provides a phase shifted output signal, such as a phase shifted STROBE signal, that includes a delay stage in a phase shifted output signal drive buffer coupled to the delay stage, such as a voltage control delay line. The feedback delay matching array includes a plurality of serially coupled buffer stages operatively coupled to compensate for delay variations associated with the phase shifted output signal drive buffer in the variable delay circuit.
摘要翻译：信号移相电路基于诸如CLOCK信号的参考信号来移动诸如STROBE信号的输入信号的相位，以便于例如接收双倍数据速率数据。信号移相电路包括具有可操作地耦合到多个电压控制延迟线之一的反馈延迟匹配阵列的参考信号周期分频电路。该信号移相电路还包括可变延迟电路，其提供相移输出信号，例如相移的STROBE信号，该相移输出信号包括耦合到延迟级的相移输出信号驱动缓冲器中的延迟级，例如电压控制延时线。反馈延迟匹配阵列包括可操作地耦合以补偿与可变延迟电路中的相移输出信号驱动缓冲器相关联的延迟变化的多个串联耦合缓冲器级。

2. 发明授权

US07017053B2 System for reduced power consumption by monitoring video content and method thereof 有权
公开(公告)号：US07017053B2
公开(公告)日：2006-03-21
申请号：US10083917
申请日：2002-02-27
申请人： Carl Mizuyabu , Charles Leung , Milivoje Aleksic
发明人： Carl Mizuyabu , Charles Leung , Milivoje Aleksic
IPC分类号： G06F1/32
CPC分类号： G09G5/006 , G06F1/3203 , G06F1/3218 , G06F1/3225 , G06F1/3237 , G06F1/3265 , G09G5/00 , G09G2330/021 , Y02D10/128 , Y02D10/153
摘要： A system and method are provided for reducing power consumption within a video processing portion of a system based on display content. Display content is monitored to determine whether the display content is changing. New display content is compared to old display content to determine if the display content is changing. If the display content has not changed, a frame rate used to output display data is reduced. A color depth associated with the display data is also reduced. Power consumption can be reduced when it is determined that display content is not changing.

3. 发明授权

US06643756B1 System and method for accessing video data using a translation client 有权
标题翻译：使用翻译客户端访问视频数据的系统和方法
公开(公告)号：US06643756B1
公开(公告)日：2003-11-04
申请号：US09438308
申请日：1999-11-11
申请人： Milivoje Aleksic , Nader Akhlaghi-Tavasoli , Jason Chan , Carl Mizuyabu , Antonio Asaro
发明人： Milivoje Aleksic , Nader Akhlaghi-Tavasoli , Jason Chan , Carl Mizuyabu , Antonio Asaro
IPC分类号： G06F1200
CPC分类号： G06F3/14 , G06F12/1027 , G06F12/1081
摘要： A request for video or graphics data is made to a memory controller. When the memory controller determines a translation of the data must first be made, a request is made to a translator. The translator either translates the address or requests translation information from the memory controller. The memory controller accesses memory based upon the translator request. If the request is for translation data the results are tagged for the translator. If the translator request is for the translated address, the results are tagged for the original request.
摘要翻译：对存储器控制器进行视频或图形数据的请求。当存储器控制器确定首先需要进行数据的转换时，向翻译器发出请求。翻译器翻译来自存储器控制器的地址或请求翻译信息。存储器控制器根据翻译器请求访问存储器。如果请求用于翻译数据，则结果将被标记为翻译器。如果翻译请求是用于翻译的地址，结果将被标记为原始请求。

4. 发明授权

US07650552B2 Apparatus and method for detecting and recovering errors caused by electrostatic discharge 有权
标题翻译：用于检测和恢复由静电放电引起的误差的装置和方法
公开(公告)号：US07650552B2
公开(公告)日：2010-01-19
申请号：US11278199
申请日：2006-03-31
申请人： Fariborz Pourbigharaz , Milivoje Aleksic , Carl Mizuyabu , Aris Balatsos , Zeeshan Syed
发明人： Fariborz Pourbigharaz , Milivoje Aleksic , Carl Mizuyabu , Aris Balatsos , Zeeshan Syed
IPC分类号： G01R31/28
CPC分类号： G06F11/0751 , G06F11/0742
摘要： A method and apparatus for detecting an error compares a hardwired reference value to a corresponding predetermined value and generates an error indication in response to a change in the predetermined value. In one embodiment, the predetermined value is set to be the same as the hardwired reference value and in response to an electrostatic discharge event or any other suitable cause of error, the predetermined value changes so that a comparison indicates that an error has occurred. An error indication is then generated which may be, for example, an interrupt to recovery logic that generates recovery control information to reset a functional block that was corrupted or to perform in an entire chip reset if desired.
摘要翻译：用于检测错误的方法和装置将硬连线参考值与对应的预定值进行比较，并响应于预定值的变化而产生错误指示。在一个实施例中，将预定值设置为与硬连线参考值相同，并且响应于静电放电事件或任何其它合适的错误原因，预定值改变，使得比较指示发生错误。然后产生错误指示，其可以是例如产生恢复控制信息的恢复逻辑的中断，以恢复被破坏的功能块或者如果需要在整个芯片复位中执行。

5. 发明申请

US20070250750A1 ERROR DETECTION APPARATUS AND METHOD 有权
标题翻译：错误检测装置和方法
公开(公告)号：US20070250750A1
公开(公告)日：2007-10-25
申请号：US11278199
申请日：2006-03-31
申请人： Fariborz Pourbigharaz , Milivoje Aleksic , Carl Mizuyabu , Aris Balatsos , Zeeshan Syed
发明人： Fariborz Pourbigharaz , Milivoje Aleksic , Carl Mizuyabu , Aris Balatsos , Zeeshan Syed
IPC分类号： H04L1/00 , H03M13/00 , G08C25/00 , G06F11/00 , G06F11/30
CPC分类号： G06F11/0751 , G06F11/0742
摘要： A method and apparatus for detecting an error compares a hardwired reference value to a corresponding predetermined value and generates an error indication in response to a change in the predetermined value. In one embodiment, the predetermined value is set to be the same as the hardwired reference value and in response to an electrostatic discharge event or any other suitable cause of error, the predetermined value changes so that a comparison indicates that an error has occurred. An error indication is then generated which may be, for example, an interrupt to recovery logic that generates recovery control information to reset a functional block that was corrupted or to perform in an entire chip reset if desired.
摘要翻译：用于检测错误的方法和装置将硬连线参考值与对应的预定值进行比较，并响应于预定值的变化而产生错误指示。在一个实施例中，将预定值设置为与硬连线参考值相同，并且响应于静电放电事件或任何其它合适的错误原因，预定值改变，使得比较指示发生错误。然后产生错误指示，其可以是例如产生恢复控制信息的恢复逻辑的中断，以恢复被破坏的功能块或者如果需要在整个芯片复位中执行。

6. 发明授权

US07114086B2 System for reduced power consumption by monitoring instruction buffer and method thereof 有权
公开(公告)号：US07114086B2
公开(公告)日：2006-09-26
申请号：US10083875
申请日：2002-02-27
申请人： Carl Mizuyabu , Mark Sternberg , Milivoje Aleksic
发明人： Carl Mizuyabu , Mark Sternberg , Milivoje Aleksic
IPC分类号： G06F1/32
CPC分类号： G09G5/008 , G06F1/3203 , G06F1/3218 , G06F1/3225 , G06F1/3237 , G06F1/3265 , G06F9/3802 , G06F9/3814 , G09G5/006 , G09G2330/021 , Y02D10/128 , Y02D10/153
摘要： A system and method are provided for reducing power consumption within a video processing portion of a system. Activity associated with an instruction buffer is monitored to determine whether power consumption modes can be initiated within a system. If a number of pending instructions within an instruction buffer is greater than a particular threshold value, a normal mode of operation is initiated. If the number of pending instructions is less than the threshold value, the system is put in a reduced mode of operation. In the reduced mode of operation, processing is reduced to lower power consumption within the system. Accordingly, power consumption is altered to match a level of activity within the instruction buffer.

7. 发明授权

US07929648B2 Clock error detection apparatus and method 有权
标题翻译：时钟误差检测装置及方法
公开(公告)号：US07929648B2
公开(公告)日：2011-04-19
申请号：US11278221
申请日：2006-03-31
申请人： Fariborz Pourbigharaz , Milivoje Aleksic , Carl Mizuyabu , Aris Balatsos
发明人： Fariborz Pourbigharaz , Milivoje Aleksic , Carl Mizuyabu , Aris Balatsos
IPC分类号： H04L27/06
CPC分类号： H04L7/0083
摘要： An error detection apparatus and method compares a first hardwired value such as a first clock threshold, and a second hardwired value such as a second clock threshold, and generates an indication that there is an error in a clock signal based on a comparison of the first hardwired value and the second hardwired value to the clock signal. If an error is detected, the error detection apparatus will, for example, interrupt clock recovery logic to take proper action for recovery of a clock generation circuit that generated the clock signal. The clock signal may be generated based on, for example, a reference clock signal that may be provided by an external source clock, or any other suitable source.
摘要翻译：错误检测装置和方法比较第一硬连线值（例如第一时钟阈值）和第二硬连线值（例如第二时钟阈值），并且基于第一时钟阈值的比较生成时钟信号中存在错误的指示硬连线值和第二个硬连线值到时钟信号。如果检测到错误，则错误检测装置将例如中断时钟恢复逻辑以采取适当的动作来恢复生成时钟信号的时钟产生电路。时钟信号可以基于例如可由外部源时钟提供的参考时钟信号或任何其它合适的源来产生。

8. 发明申请

US20070230647A1 CLOCK ERROR DETECTION APPARATUS AND METHOD 有权
标题翻译：时钟错误检测装置和方法
公开(公告)号：US20070230647A1
公开(公告)日：2007-10-04
申请号：US11278221
申请日：2006-03-31
申请人： Fariborz Pourbigharaz , Milivoje Aleksic , Carl Mizuyabu , Aris Balatsos
发明人： Fariborz Pourbigharaz , Milivoje Aleksic , Carl Mizuyabu , Aris Balatsos
IPC分类号： H04L7/00
CPC分类号： H04L7/0083
摘要： An error detection apparatus and method compares a first hardwired value such as a first clock threshold, and a second hardwired value such as a second clock threshold, and generates an indication that there is an error in a clock signal based on a comparison of the first hardwired value and the second hardwired value to the clock signal. If an error is detected, the error detection apparatus will, for example, interrupt clock recovery logic to take proper action for recovery of a clock generation circuit that generated the clock signal. The clock signal may be generated based on, for example, a reference clock signal that may be provided by an external source clock, or any other suitable source.
摘要翻译：错误检测装置和方法比较第一硬连线值（例如第一时钟阈值）和第二硬连线值（例如第二时钟阈值），并且基于第一时钟阈值的比较生成时钟信号中存在错误的指示硬连线值和第二个硬连线值到时钟信号。如果检测到错误，则错误检测装置将例如中断时钟恢复逻辑以采取适当的动作来恢复生成时钟信号的时钟产生电路。时钟信号可以基于例如可由外部源时钟提供的参考时钟信号或任何其它合适的源来产生。

9. 发明授权

US06532525B1 Method and apparatus for accessing memory 有权
标题翻译：访问存储器的方法和装置
公开(公告)号：US06532525B1
公开(公告)日：2003-03-11
申请号：US09675368
申请日：2000-09-29
申请人： Milivoje Aleksic , Grigory Temkine , Oleg Drapkin , Carl Mizuyabu , Adrian Hartog
发明人： Milivoje Aleksic , Grigory Temkine , Oleg Drapkin , Carl Mizuyabu , Adrian Hartog
IPC分类号： G06F1200
CPC分类号： G06F13/1689 , G09G5/39 , Y02D10/14
摘要： A specific embodiment is disclosed for a method and apparatus for processing data access requests from a requesting device, such as a graphics processor device. Data access commands are provided at a first rate, for example 200M commands per second, to a memory bridge. In response to receiving the access requests the memory bridge will provide its own access requests to a plurality of memories at approximately the first rate. In response to the memory bridge requests, the plurality of memories will access a plurality of data at a second data rate. When the data access between the memory bridge and the memories is a read request, data is returned to the requesting device at a third data rate which is greater than the first data rate by approximately four-times or more. Noise and power reduction techniques can be used on the data bus between the accessing device and the data bridge.
摘要翻译：公开了一种用于处理来自请求设备（诸如图形处理器设备）的数据访问请求的方法和设备的具体实施例。数据访问命令以第一速率（例如每秒200M命令）提供给存储器桥。响应于接收到访问请求，存储器桥将以大约第一速率向多个存储器提供其自己的访问请求。响应于存储器桥请求，多个存储器将以第二数据速率访问多个数据。当存储器桥和存储器之间的数据访问是读取请求时，数据以大于第一数据速率的大约四倍或更多的第三数据速率返回给请求设备。噪声和功率降低技术可以在接入设备和数据桥之间的数据总线上使用。

10. 发明授权

US06502173B1 System for accessing memory and method therefore 有权
标题翻译：因此，访问内存和方法的系统
公开(公告)号：US06502173B1
公开(公告)日：2002-12-31
申请号：US09675293
申请日：2000-09-29
申请人： Milivoje Aleksic , Grigory Temkine , Oleg Drapkin , Carl Mizuyabu , Adrian Hartog
发明人： Milivoje Aleksic , Grigory Temkine , Oleg Drapkin , Carl Mizuyabu , Adrian Hartog
IPC分类号： G06F1200
CPC分类号： G06F13/1689 , G06F13/1605 , Y02D10/14
摘要： A specific embodiment is disclosed for a method and apparatus for processing data access requests from a requesting device, such as a graphics processor device. Data access commands are provided at a first rate, for example 200M command per second, to a memory bridge. In response to receiving the access requests the memory bridge will provide its own access requests to a plurality of memories at approximately the first rate. In response to the memory bridge requests, the plurality of memories will access a plurality of data a second data rate. When the data access between the memory bridge and the memories is a read request, data is returned to the requesting device at a third data rate which is greater than the first data rate by approximately four times or more. Noise and power reduction techniques can be used on the data bus between the accessing device and the data bridge.
摘要翻译：公开了一种用于处理来自请求设备（诸如图形处理器设备）的数据访问请求的方法和设备的具体实施例。数据访问命令以第一速率（例如每秒200M命令）提供给存储器桥。响应于接收到访问请求，存储器桥将以大约第一速率向多个存储器提供其自己的访问请求。响应于存储器桥请求，多个存储器将访问多个数据第二数据速率。当存储器桥和存储器之间的数据访问是读取请求时，数据以大于第一数据速率的大约四倍或更多的第三数据速率返回给请求设备。噪声和功率降低技术可以在接入设备和数据桥之间的数据总线上使用。

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