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1. 发明专利

JPH03104492A TIME DIVISION EXCHANGE SWITCH 失效
公开(公告)号：JPH03104492A
公开(公告)日：1991-05-01
申请号：JP24267889
申请日：1989-09-19
申请人： FUJITSU LTD , FUJITSU DAIICHI TSUSHIN SOFT
发明人： FUKUMOTO KOICHIRO , HIDAKA TOSHIO
IPC分类号： H04Q3/52 , H04Q11/04
摘要： PURPOSE:To detect the fault of a speech memory without impairing profitability by writing input data alternately at every frame without performing conversion, and collating both output data outputted from two pairs of speech memories sending the data alternately and read out from the same address of each speech memory. CONSTITUTION:When the normalcy of the speech memories 11aa and 11bb are inspected, the same test data T is written on the same addresses of both speech memories 11aa and 11bb. Then, output data doa and dob read out from the correspondent addresses of both speech memories 11aa and 11bb are collated with an output collation means 100. When coincidence is obtained, it is judged that normal write and readout on the corresponding addresses of both speech memories 11aa and 11bb can be performed. Therefore, it is possible to dispense with a parity generation circuit and a parity inspection circuit only by preparing the output collation means in the time division exchange switch, and also, only the input data can be written on both speech memories, and no write of the input data with parity is required.

2. 发明专利

JPS57136892A CABLE CONNECTING METHOD IN EXCHANGE SYSTEM 失效
公开(公告)号：JPS57136892A
公开(公告)日：1982-08-24
申请号：JP2151981
申请日：1981-02-18
申请人： HITACHI LTD , NIPPON TELEGRAPH & TELEPHONE , OKI ELECTRIC IND CO LTD , NIPPON ELECTRIC CO , FUJITSU LTD
发明人： HOSHI TOORU , OGAWA YOUICHI , KUROIWA KUNIO , SUEHIRO FUMITAKA , SHIBUYA TADASHI , HIDAKA TOSHIO
IPC分类号： H04N9/68 , H04Q1/06
摘要： PURPOSE:To achieve continuity test of cables easily even with unmounted devices, by forming cables incorporated with a future output side cable, without cutting off an input cable to a planned unmounted device. CONSTITUTION:In an exchange system of unit type, an input side cable and an output side cable are installed to a frame 3 having unmounted devices. In this case, the length of a cable 5 under work connected to an input side terminal 2 is a total length of the input and output side, and another end of the cable 5 is directly connected to an output side terminal 2'. At the mounting of a unit 4, the cable 5 is cut off and connected to input and output terminals of the unit 4. Thus, the continuity test of the cable 5 can easily be done between the input terminals 2 and output terminals 2'.

3. 发明专利

JPS5516562A CONSTITUTING METHOD FOR SWITCH MATRIX 失效
公开(公告)号：JPS5516562A
公开(公告)日：1980-02-05
申请号：JP8942978
申请日：1978-07-24
申请人： HITACHI LTD , NIPPON TELEGRAPH & TELEPHONE , OKI ELECTRIC IND CO LTD , NIPPON ELECTRIC CO , FUJITSU LTD
发明人： KOMATSU AYAFUMI , ENDOU YUUJI , ISHIKAWA KIYOKAZU , SHIBUYA TADASHI , HIDAKA TOSHIO
IPC分类号： H04Q3/68 , H04Q3/00
摘要： PURPOSE:To reduce multicontact sealed elements, to rationalize the number of manufacturing processes, and to reduce control processes in number using a couple of contacts of the multicontact seal-in elements multi-connected internally as cut-off contacts. CONSTITUTION:The internal multiple connection 5 of eight multicontact-sealed elements 3-a arrayed horizontally is connected to subscriber's terminals (H0A, H0B)...(C7A, H7B) and respective couples of contacts 2 are connected to cut-off contacts to scanner terminals (CO0A, CO0B)...(CO7A, CO7B). Eight couples of contacts 4 connected through internal multiple connection 5 are connected corresponding to subscriber's terminals (H0A, H0B)...(H7A, H7B) through external connection 7, so that one multicontact-sealed element 3-b used vertically will be extended to the cross point contact matrixes of 8 by 7 and of 8 by 8.

4. 发明专利

JPH04218793A SETTING SYSTEM OF TIME INFORMATION 失效
公开(公告)号：JPH04218793A
公开(公告)日：1992-08-10
申请号：JP40395790
申请日：1990-12-19
申请人： FUJITSU LTD
发明人： HIDAKA TOSHIO
IPC分类号： G04C9/04 , G04G5/00 , G04G7/00 , G06F1/14 , H04M3/22 , H04M15/00
摘要： PURPOSE:To set automatically the time of an internal clock of a switchboard at the time of recovery from an abnormal state, when the abnormal state hindering the service occurs in the switchboard, regarding a setting system of time information of the internal clock of the switchboard. CONSTITUTION:In a communication network wherein a switchboard l having an internal clock 3 indicating the current time is connected to a common channel signaling network 2, a time information delivering means 4 which delivers periodically time information on the current time to the aforesaid common channel signaling network is provided, and a time information receiving means 5 which receives the aforesaid time information from the common channel signaling network, a detecting means 6 of recovery from abnormality which outputs information on recovery from abnormality when an abnormal state occurs and settles in the switchboard, and an internal clock control means 7 which sets on the internal clock the time information received by the time information receiving means, when the aforesaid information on recovery from abnormality is outputted, are provided in the aforesaid switchboard.

5. 发明专利

JPS57136893A LOCK SIGNAL TRANSMISSION SYSTEM IN RADIO REMOTE MONITOR CONTROL SYSTEM 失效
公开(公告)号：JPS57136893A
公开(公告)日：1982-08-24
申请号：JP2252081
申请日：1981-02-18
申请人： FUJITSU LTD
发明人： OGIYAMA HIDEYUKI , OGAWA YOUICHI , KUROIWA KUNIO , SUEHIRO FUMITAKA , SHIBUYA TADASHI , HIDAKA TOSHIO
IPC分类号： H04Q9/00
摘要： PURPOSE:To achieve smooth observtion or control without interference during the obseravtion or control, by providing a function which gives a response signal unless the station itself is busy, with a processor of a monitor controller of a master station. CONSTITUTION:In a radio remote monitor control system consisting of two master stations and a plurality of slave stations in which the transmission frequency and the reception frequency are the same, when one master station makes monitor or control of a slave station, the tansmission of another master station is inhibited. In this case, when one master station makes monitor or control of the slave station by a monitor controller 1, a lock signal is transmitted for a short time by using the clock of a clock section 2 in advance and it is confirmed that another master station is not during transmission with the presence of the response signal from another master station and the transmission is inhibited to another master station.

6. 发明专利

JPS5510244A COMMON SIGNAL BUS SYSTEM 失效
公开(公告)号：JPS5510244A
公开(公告)日：1980-01-24
申请号：JP8288378
申请日：1978-07-10
申请人： FUJITSU LTD , NIPPON TELEGRAPH & TELEPHONE , OKI ELECTRIC IND CO LTD , NIPPON ELECTRIC CO , HITACHI LTD
发明人： HIDAKA TOSHIO , KAMEI KIMIAKI , MUNAKATA KOUICHI , YAMAZAKI AKIO , FUKUSHIMA YUTAKA
IPC分类号： H04Q3/545 , G06F13/38 , G06F13/42 , H04L12/40
摘要： PURPOSE:To attain accurate signal transmission and reception among devices with different interfaces without increasing buses in number, by providing common signal buses of the common controller of an electronic switchboard with a method of setting synchronous bits of each bus interface. CONSTITUTION:Between signal transmitter 2 and signal transmitter 1 differing in bus information array, time-division signal transmission and reception are executed sharing synchronous bit buses S1 to Sn and data bit buses (d1) to (dn) as signal buses. Synchronous-bit transmitting bus driver 11 and synchronous-bit receiving bus receiver 21, provided to transmitter 1 and receiver 2, are provided synchronous bits for respective bus information array kinds as many as the kinds, and a synchronous bit is selected corresponding to the kind of a bus information array. Then, the selected synchronous bits are sent out to buses S1 to Sn to actuate only a group of devices with the same bus information array, so that signal transmission and reception among devices with different interfaces will be made accurate with the number of buses reduced.

7. 发明专利

JPS551711A COMMUNICATION PATH DRIVE SYSTEM OF 4 WIRE TYPE 失效
公开(公告)号：JPS551711A
公开(公告)日：1980-01-08
申请号：JP7375678
申请日：1978-06-20
申请人： OKI ELECTRIC IND CO LTD , NIPPON TELEGRAPH & TELEPHONE , NIPPON ELECTRIC CO , HITACHI LTD , FUJITSU LTD
发明人： MUNAKATA KOUICHI , KIYOHARA SHINJI , MORISHITA TERUO , OKUDA SABUROU , HIDAKA TOSHIO
IPC分类号： H04Q3/64 , H04Q3/00 , H04Q3/68
摘要： PURPOSE:To remarkably simplify the 4 wire type comminication drive unit, by closing and opening the communication path every 2 wire type communication path switch group, through the operation of the drive level selection circuit in time sharing and the drive of the X and Y drive line every operation. CONSTITUTION:The drive bus selection circuits 5, 6 selecting respectively one of the X drive line 8, Y drive line 9, and the first and second communication path switch grid 7, the first or second communication path grid group 7 are connected to the switch drive circuits 1, 2 provided in common with the grid group 7 via the drive level selection circuits 3 and 4 individually selected. Further, the circuits 3 and 4 are in time sharing operated as that the open and close of the communication path can be made every 2 wire type communication path switch grid group through the drive of the circuits 1 and 2 every operation of the circuits 3 and 4. Thus, the 4 wire type communication path drive unit can remarkably be simplified.

8. 发明专利

JPS64850A CONTINUITY TEST LINE SETTING SYSTEM 失效
公开(公告)号：JPS64850A
公开(公告)日：1989-01-05
申请号：JP15598587
申请日：1987-06-23
申请人： FUJITSU LTD , NIPPON TELEGRAPH & TELEPHONE
发明人： HIDAKA TOSHIO , KOGURE KOJI
IPC分类号： H04M3/26 , H04J3/14 , H04Q1/24
摘要： PURPOSE:To detect trouble which occurs in a double buffer type time division switch, by setting a time slot for pilot signal extract ion as prescribed. CONSTITUTION:An address generating means 600 sets the write time and the read time of data memories 100 and 200 so that the time of a time slot TSr where a pilot signal P is extracted from a double buffer type time division switch 300 is equal to or behind the time of a time slot TSw where the signal P is stored in the switch 300. Thus, in case of a frame under which one data memory is operated in the same manner as single buffer type because of the occurrence of trouble in the switch 300, the signal P stored in the time slot TSw is extracted in the time slot TSr in the same frame F, and the inter-frame continuity between this signal extraction and extraction of the signal P which is stored in the time slot TSw in the just preceding frame F in the other data memory cannot be held. Thus, trouble of the double buffer type time division switch 300 is detected as the result of continuity test.

9. 发明专利

JPS58129566A OVERLAYING SYSTEM 失效
公开(公告)号：JPS58129566A
公开(公告)日：1983-08-02
申请号：JP1018782
申请日：1982-01-27
申请人： FUJITSU LTD
发明人： KOUDA YOSHIFUMI , HIDAKA TOSHIO , MAENO SHINICHI
IPC分类号： G06F15/16 , G06F9/445 , G06F15/163 , G11C29/00
摘要： PURPOSE:To make a doubling or stand-by system small-sized, and to improve its service, by storing a program which is not strict as to real time processing, or a program data which is not used frequently, in a main storage device of a stand-by side, and shifting it to a main storage device of an act side as necessary. CONSTITUTION:Main storage devices 11a, 11b, central control devices 12a, 12b and inter-system communicating devices 13a, 13b are completely doubled, one is made an act system, the other is made a stand-by system, and the system is operated. To this system, a magnetic tape 15a, cassette magnetic tape 15b, a floppy disk 15c, etc. are connected through an input/output device 14. On the main storage device 13a of this act system, an overlay area 25 as well as various progams is provided, and in the stand-by system, various program data 27 are stored in advance. In this state, when a fault has occurred in the act system, said program data 27 are shifted to the area 25 of the act system, its program data 27 are executed, and the system is made small-sized, and the service is diversified.

10. 发明专利

JPS56149893A NETWORK EXTENSION SYSTEM 失效
公开(公告)号：JPS56149893A
公开(公告)日：1981-11-19
申请号：JP5288480
申请日：1980-04-23
申请人： HITACHI LTD , NIPPON TELEGRAPH & TELEPHONE , OKI ELECTRIC IND CO LTD , NIPPON ELECTRIC CO , FUJITSU LTD
发明人： HOSHI TOORU , NAKAMURA MASANORI , YAMAKOSHI SETSUO , SHIBUYA TADASHI , HIDAKA TOSHIO
IPC分类号： H04Q3/68
摘要： PURPOSE:To execute an extension test without reducing the processing capacity of a network, by constituting so that the pre-extension junctors and the post-extension junctors can be installed together. CONSTITUTION:In case of extension of the network LIN1 and TLN1, at first, the junctor subgroups J2, J3, J4 are connected before blocking the junctor subgroup J1. In the LLN0 and the TLN0, since connectors C4, C5 are connected in parallel with connectors C2, C3, the extension junctor subgroups J2, J3 can be connected without removing the junctor subgroup J1. Even when the extension junctors J2-J4 have been connected, the channel is set by LLN0, J0 or J1 and TLN0 as usual, by leaving said junctors blocked against a general call. When the test has been completed, the processing logic is changed so that the connection processing is executed by the post-extension network constitution against a general call. And, after the processing logic has been changed, the junctor subgroup J1 is detached.

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