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    • 7. 发明专利
    • Clock supply control system
    • 时钟供应控制系统
    • JPS59132023A
    • 1984-07-30
    • JP585183
    • 1983-01-19
    • Fujitsu LtdHitachi LtdNec CorpNippon Telegr & Teleph Corp Oki Electric Ind Co Ltd
    • HONDA KENICHIKAMEI KIMIAKIONOZUKA TOMOJISAKAMOTO SHIGETOSHITACHIKA SHINJI
    • G06F1/04
    • G06F1/04
    • PURPOSE:To operate stably an information processing device even if it is not initialized from the external, by determining certainly only one clock source, which supplies clocks to each information processing device, independently of the characteristic at the power-on time of an electronic circuit used as a clock self-FF. CONSTITUTION:When a power source for clock supply of a 0-side information processing device #0 is turned on at a time t0, the first clock self-FF f is set at a time t1 thereafter. This signal 29 is inputted to one input of an AND gate 2, and a clock supply output determining signal 92 of an AND gate 82 of a 1-side information processing device #1 is inverted from ''1'' and is inputted as ''0''. When a power source for clock supply of the 1-side information processing device # is turned on at a time t2 after the time t0 and the time t1, one input of the AND gate 82 becomes already ''0'' attained by inversion of the clock supply output determinating signal 92, and AND between a signal 91 and one input of the AND gate 82 is operated at a time t3 to attain output ''0''.
    • 目的:为了稳定地操作信息处理设备,即使没有从外部进行初始化,通过仅确定一个时钟源,每个时钟源向每个信息处理设备提供时钟,独立于电子电路的通电时的特性 用作时钟自动FF。 构成:在时刻t0使0侧信息处理装置#0的时钟供给用电源接通的情况下,在其后的时刻t1设定第1时钟自FF f f。 该信号29被输入到与门2的一个输入端,并且1侧信息处理装置#1的与门82的时钟供给输出确定信号92从“1”反转并被输入为“ '0'”。 当在时刻t0和时间t1之后的时间t2,当用于1侧信息处理装置#的时钟供给的电源被接通时,与门82的一个输入端已经变为“0” 时钟供给输出确定信号92和AND门82的一个输入端之间的AND被操作在时间t3以获得输出“0”。
    • 8. 发明专利
    • Clock switching control system
    • 时钟切换控制系统
    • JPS59133622A
    • 1984-08-01
    • JP735283
    • 1983-01-21
    • Fujitsu LtdHitachi LtdNec CorpNippon Telegr & Teleph Corp Oki Electric Ind Co Ltd
    • HONDA KENICHIKAMEI KIMIAKIONOZUKA TOMOJISAKAMOTO SHIGETOSHITACHIKA SHINJI
    • G06F1/04
    • G06F1/04
    • PURPOSE:To switch clocks without controlling clocks at all, by ensuring phases of clocks to switch clocks during the operation of a device when clock sources are switched. CONSTITUTION:If switching of clock sources occurs when an FF 21 is set to ''1'', FFs 41-43 are reset through a circuit 29 which supplies a reset signal with an output waveform C of a clock self-FF20, and the clock supply of a #0-side clock supply circuit 27 is made ineffective by an output waveform (d) of the FF 21 at a time t1, and the clock supply from the #1 side is made effective by an output waveform (e) of an FF 22 at a time t3. An output waveform (j) of the FF41 becomes ''1'' at a time t2, and an output waveform (l) of the FF43 becomes ''1'' at a time t6, and an output waveform (h) supplied from a clock supply circuit 47 is made effective at the time t6, and clocks are supplied to the #1 side, and clocks are supplied to the #0 side from an OR gate 28. Thus, the clock supply waveform to the #0 side and the #1 side becomes as shown by (m).
    • 目的:在切换时钟源时,通过确保在器件运行期间切换时钟的时钟,可以切换时钟,而不需要控制时钟。 构成:当FF21设为“1”时,如果切换时钟源,则通过电路29复位FF41-43,电路29将复位信号与时钟自FF20的输出波形C提供, #0侧时钟供给电路27的时钟供给在时刻t1由FF21的输出波形(d)无效,并且通过输出波形(e)使来自#1侧的时钟电源生效, 在时间t3的FF 22。 FF41的输出波形(j)在时间t2变为“1”,在时刻t6,FF43的输出波形(1)变为“1”,输出波形(h)从 时钟供给电路47在时刻t6生效,时钟被提供给#1侧,时钟从或门28提供给#0侧。因此,向#0侧提供时钟供给波形, #1侧变为(m)所示。
    • 9. 发明专利
    • Revising system of line name of magnetic bubble
    • 磁性气泡线名称修正系统
    • JPS59132488A
    • 1984-07-30
    • JP796183
    • 1983-01-20
    • Fujitsu LtdHitachi LtdNec CorpNippon Telegr & Teleph Corp Oki Electric Ind Co Ltd
    • TACHIKA SHINJIKAMEI KIMIAKISAKATA HIRONOBUKITAZAWA MITSURUNOGUCHI OSAMU
    • G11C11/14
    • G11C11/14
    • PURPOSE:To reduce time required for the processing of write and revision of line name by disconnecting a magnetic bubble storage device and a magnetic bubble storage device controller from other devices, especially a central controller to attain the test of the normality of the devices and to attain write and revision of line name. CONSTITUTION:When a magnetic bubble storage device controller MBCH receives a magnetic bubble storage device controller number from the central controller CC via a line CHN and an instruction from a line ODR, and when the said number is coincident with the own number, the MBCH is operated by the said instruction. The address of a main storage device MM storing the required data is calculated and fed to a line MAD-BUS (memory address bus), a required data is read from the main storage device MM and the MBCH performs prescribed operations such as write of designated data to a designated address of a magnetic bubble storage device MBU, read of data from the designated address and transfer of it to the main storage device by reading the required data transmitted from the main storage device MM based on the data transmitted via gates 2, 51 from the line DATA-BUS.
    • 目的:通过将磁性气泡存储装置和磁性气泡存储装置控制器与其他装置,特别是中央控制器断开连接,以减少对线路名称的写入和修改所需的时间,以实现对装置的正常性的测试,以及 达到线路名称的修改和修改。 构成:当磁性气泡存储装置控制器MBCH经由线路CHN从中央控制器CC接收到磁性气泡存储装置控制器号码和来自线路ODR的指令时,并且当所述数量与自身号码一致时,MBCH为 由该指令操作。 计算存储所需数据的主存储装置MM的地址并将其馈送到线路MAD-BUS(存储器地址总线),从主存储装置MM读取所需的数据,并且MBCH执行诸如指定的写入的规定操作 数据到磁性气泡存储装置MBU的指定地址,从指定地址读取数据并通过从主存储装置MM发送的数据读取从主存储装置MM发送的所需数据,将其传送给主存储装置, 51线从DATA-BUS线。
    • 10. 发明专利
    • MAGNETIC BUBBLE STORAGE DEVICE
    • JPS60226088A
    • 1985-11-11
    • JP8185984
    • 1984-04-25
    • HITACHI LTDNIPPON TELEGRAPH & TELEPHONE
    • SHIDA KOUJIKAMEI KIMIAKI
    • G11C11/14
    • PURPOSE:To execute an automatic release when an address check circuit detects an error by executing autonomously when one system is at fault of address mismatching, and also executing autonomously the transfer of a data from a normal system. CONSTITUTION:When an address checking circuit 33 in a magnetic bubble control part 3 detects an error and returns a signal to a device selection controlling circuit 5, an error processing circuit 52 sends a signal to a data switching circuit 51, and supplies an instruction so that it is switched to a data line of the side B from a data line of the side A. In such a way, the connection is switched to the normal B side device from the faulty A side device. Also, the error processing circuit 52 starts an initializing circuit 34 of the faulty device, erases information of a magnetic bubble storage part 1, and simultaneously, initialize the inside of the magnetic bubble controlling circuit 3. Thereafter, address information is written in the magnetic bubble storage part 1, a data of a magnetic bubble storage part 2 of the side B is transferred through the data switching circuit 51, the same contents are copied, the device goes to a standby state, and the recovering is completed.