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1. 发明授权

US06682994B2 Methods for transistor gate formation using gate sidewall implantation 有权
标题翻译：使用栅极侧壁注入的晶体管栅极形成方法
公开(公告)号：US06682994B2
公开(公告)日：2004-01-27
申请号：US10123686
申请日：2002-04-16
申请人： F. Scott Johnson , Tad Grider , Benjamin P. Mckee
发明人： F. Scott Johnson , Tad Grider , Benjamin P. Mckee
IPC分类号： H01L213205
CPC分类号： H01L21/28035 , H01L21/26513 , H01L21/324 , H01L29/4916 , H01L29/6659
摘要： Methods are disclosed for semiconductor device fabrication in which MOS transistor gates are to be formed. Polysilicon gate structures and sidewall spacers are formed, with upper portions of the gate sidewalls exposed. Angled implantation processing is employed to impart dopants to the top and exposed sidewall portions of the gate structure to mitigate poly depletion.
摘要翻译：公开了将要形成MOS晶体管栅极的半导体器件制造的方法。形成多晶硅栅极结构和侧壁间隔物，露出栅极侧壁的上部。使用角度注入处理以将掺杂剂赋予栅极结构的顶部和暴露的侧壁部分以减轻多余的损耗。

2. 发明授权

US07572693B2 Methods for transistor formation using selective gate implantation 有权
标题翻译：使用选择性栅极注入的晶体管形成方法
公开(公告)号：US07572693B2
公开(公告)日：2009-08-11
申请号：US11462541
申请日：2006-08-04
申请人： F. Scott Johnson , Tad Grider , Benjamin P. McKee
发明人： F. Scott Johnson , Tad Grider , Benjamin P. McKee
IPC分类号： H01L21/8238 , H01L21/336 , H01L21/8234 , H01L21/04
CPC分类号： H01L21/28035 , H01L29/66545 , H01L29/6656 , H01L29/6659 , H01L29/7833
摘要： Methods are disclosed for semiconductor device fabrication in which dopants are selectively implanted into transistor gate structures to counteract or compensate for dopant depletion during subsequent fabrication processing. A patterned implant mask is formed over a semiconductor device, which exposes at least a portion of the gate structure and covers the remaining upper surfaces of the device. Thereafter, dopants are selectively implanted in to the exposed gate structure.
摘要翻译：公开了用于半导体器件制造的方法，其中将掺杂剂选择性地注入到晶体管栅极结构中以抵消或补偿在随后的制造处理期间的掺杂剂耗尽。图案化的注入掩模形成在半导体器件上，其暴露栅极结构的至少一部分并且覆盖器件的剩余上表面。此后，将掺杂剂选择性地植入到暴露的栅极结构中。

3. 发明授权

US07098098B2 Methods for transistors formation using selective gate implantation 有权
公开(公告)号：US07098098B2
公开(公告)日：2006-08-29
申请号：US10226536
申请日：2002-08-23
申请人： F. Scott Johnson , Tad Grider , Benjamin P. Mckee
发明人： F. Scott Johnson , Tad Grider , Benjamin P. Mckee
IPC分类号： H01L21/8238 , H01L21/336 , H01L21/8234 , H01L21/04
CPC分类号： H01L29/66545 , H01L21/26513 , H01L21/28035 , H01L21/324 , H01L29/4916 , H01L29/6656 , H01L29/6659 , H01L29/7833
摘要： Methods are disclosed for semiconductor device fabrication in which dopants are selectively implanted into transistor gate structures to counteract or compensate for dopant depletion during subsequent fabrication processing. A patterned implant mask is formed over a semiconductor device, which exposes at least a portion of the gate structure and covers the remaining upper surfaces of the device. Thereafter, dopants are selectively implanted into the exposed gate structure.

4. 发明申请

US20060270140A1 Methods for Transistor Formation Using Selective Gate Implantation 有权
标题翻译：使用选择性栅植入的晶体管形成方法
公开(公告)号：US20060270140A1
公开(公告)日：2006-11-30
申请号：US11462541
申请日：2006-08-04
申请人： F. Scott Johnson , Tad Grider , Benjamin McKee
发明人： F. Scott Johnson , Tad Grider , Benjamin McKee
IPC分类号： H01L21/8238
CPC分类号： H01L21/28035 , H01L29/66545 , H01L29/6656 , H01L29/6659 , H01L29/7833
摘要： Methods are disclosed for semiconductor device fabrication in which dopants are selectively implanted into transistor gate structures to counteract or compensate for dopant depletion during subsequent fabrication processing. A patterned implant mask is formed over a semiconductor device, which exposes at least a portion of the gate structure and covers the remaining upper surfaces of the device. Thereafter, dopants are selectively implanted in to the exposed gate structure.
摘要翻译：公开了用于半导体器件制造的方法，其中将掺杂剂选择性地注入到晶体管栅极结构中以抵消或补偿在随后的制造处理期间的掺杂剂耗尽。图案化的注入掩模形成在半导体器件上，其暴露栅极结构的至少一部分并且覆盖器件的剩余上表面。此后，将掺杂剂选择性地植入到暴露的栅极结构中。

5. 发明申请

US20060270139A1 Methods for Transistor Formation Using Selective Gate Implantation 审中-公开
标题翻译：使用选择性栅植入的晶体管形成方法
公开(公告)号：US20060270139A1
公开(公告)日：2006-11-30
申请号：US11462528
申请日：2006-08-04
申请人： F. Scott Johnson , Tad Grider , Benjamin McKee
发明人： F. Scott Johnson , Tad Grider , Benjamin McKee
IPC分类号： H01L21/8238
CPC分类号： H01L21/26513 , H01L21/28035 , H01L21/324 , H01L29/4916 , H01L29/66545 , H01L29/6656 , H01L29/6659 , H01L29/7833
摘要： Methods are disclosed for semiconductor device fabrication in which dopants are selectively implanted into transistor gate structures to counteract or compensate for dopant depletion during subsequent fabrication processing. A patterned implant mask is formed over a semiconductor device, which exposes at least a portion of the gate structure and covers the remaining upper surfaces of the device. Thereafter, dopants are selectively implanted into the exposed gate structure.
摘要翻译：公开了用于半导体器件制造的方法，其中将掺杂剂选择性地注入到晶体管栅极结构中以抵消或补偿在随后的制造处理期间的掺杂剂耗尽。图案化的注入掩模形成在半导体器件上，其暴露栅极结构的至少一部分并且覆盖器件的剩余上表面。此后，将掺杂剂选择性地注入到暴露的栅极结构中。

6. 发明授权

US06380609B1 Silicided undoped polysilicon for capacitor bottom plate 有权
标题翻译：用于电容器底板的硅化无掺杂多晶硅
公开(公告)号：US06380609B1
公开(公告)日：2002-04-30
申请号：US09661717
申请日：2000-09-14
申请人： Douglas A. Prinslow , F. Scott Johnson
发明人： Douglas A. Prinslow , F. Scott Johnson
IPC分类号： H01L2900
CPC分类号： H01L28/75 , H01L21/28518 , H01L21/32055 , H01L21/321 , H01L28/60
摘要： A capacitor (110) having a bottom plate (104) that comprises undoped polysilicon (106) which has been silicided (108). An advantage of the invention is providing a capacitor (110) having reduced parasitic capacitance to the substrate (100) and reduced sheet resistance of the bottom plate (104).
摘要翻译：具有底板（104）的电容器（110）包括已被硅化的未掺杂多晶硅（106）（108）。本发明的一个优点是提供一种具有减小的对基板（100）的寄生电容并降低底板（104）的薄层电阻的电容器（110）。

7. 发明授权

US6030874A Doped polysilicon to retard boron diffusion into and through thin gate dielectrics 失效
标题翻译：掺杂的多晶硅以阻止硼扩散进入并通过薄栅极电介质
公开(公告)号：US6030874A
公开(公告)日：2000-02-29
申请号：US7060
申请日：1998-01-13
申请人： Douglas T. Grider , Stanton P. Ashburn , Katherine E. Violette , F. Scott Johnson
发明人： Douglas T. Grider , Stanton P. Ashburn , Katherine E. Violette , F. Scott Johnson
IPC分类号： H01L29/78 , H01L21/28 , H01L21/8238 , H01L29/49 , H01L29/51 , H01L21/336
CPC分类号： H01L21/26506 , H01L21/28035 , H01L21/2807 , H01L21/28176 , H01L21/32155 , H01L21/823842 , H01L29/4916 , H01L29/4966 , H01L21/28194 , H01L21/28202 , H01L29/518
摘要： An embodiment of the instant invention is a method of fabricating a semiconductor device which includes a dielectric layer situated between a conductive structure and a semiconductor substrate, the method comprising the steps of: forming the dielectric layer (layer 14) on the semiconductor substrate (substrate 12); forming the conductive structure (structure 18) on the dielectric layer; doping the conductive structure with boron; and doping the conductive structure with a dopant which inhibits the diffusion of boron. The semiconductor device may be a PMOS transistor or a capacitor. Preferably, the conductive structure is a gate structure. The dielectric layer is, preferably, comprised of a material selected from the group consisting of: an oxide, an oxide/oxide stack, an oxide/nitride stack, and an oxynitride. Preferably, the dopant which inhibits the diffusion of boron comprises at least one group III or group IV element. More specifically, it is preferably comprised of: carbon, germanium, and any combination thereof. Preferably, the steps of doping the conductive structure with boron and doping the conductive structure with a dopant which inhibits the diffusion of boron are accomplished substantially simultaneously, or the step of doping the conductive structure with boron is preformed prior to the step of doping the conductive structure with a dopant which inhibits the diffusion of boron are accomplished substantially simultaneously.
摘要翻译：本发明的实施例是一种制造半导体器件的方法，该半导体器件包括位于导电结构和半导体衬底之间的电介质层，该方法包括以下步骤：在半导体衬底（衬底）上形成介电层（层14） 12）; 在电介质层上形成导电结构（结构18）; 用硼掺杂导电结构; 并用抑制硼扩散的掺杂剂掺杂导电结构。半导体器件可以是PMOS晶体管或电容器。优选地，导电结构是栅极结构。电介质层优选由选自氧化物，氧化物/氧化物堆，氧化物/氮化物叠层和氧氮化物的材料组成。优选地，抑制硼扩散的掺杂剂包含至少一个III族或IV族元素。更具体地，其优选包括：碳，锗及其任何组合。优选地，用硼掺杂导电结构并用抑制硼的扩散的掺杂剂掺杂导电结构的步骤基本上同时实现，或者在掺杂导电的步骤之前预先形成用硼掺杂导电结构的步骤具有抑制硼扩散的掺杂剂的结构基本上同时完成。

8. 发明授权

US06620700B2 Silicided undoped polysilicon for capacitor bottom plate 有权
标题翻译：用于电容器底板的硅化无掺杂多晶硅
公开(公告)号：US06620700B2
公开(公告)日：2003-09-16
申请号：US10102416
申请日：2002-03-20
申请人： Douglas A. Prinslow , F. Scott Johnson
发明人： Douglas A. Prinslow , F. Scott Johnson
IPC分类号： H01L218242
CPC分类号： H01L28/75 , H01L21/28518 , H01L21/32055 , H01L21/321 , H01L28/60
摘要： A capacitor (110) having a bottom plate (104) that includes undoped polysilicon (106) which has been silicided (108). An advantage of the invention is providing a capacitor (110) having reduced parasitic capacitance to the substrate (100) and reduced sheet resistance of the bottom plate (104).
摘要翻译：具有底板（104）的电容器（110）包括已被硅化的未掺杂多晶硅（106）（108）。本发明的一个优点是提供一种具有减小的对基板（100）的寄生电容并降低底板（104）的薄层电阻的电容器（110）。

9. 发明授权

US06441715B1 Method of fabricating a miniaturized integrated circuit inductor and transformer fabrication 有权
公开(公告)号：US06441715B1
公开(公告)日：2002-08-27
申请号：US09505051
申请日：2000-02-16
申请人： F. Scott Johnson
发明人： F. Scott Johnson
IPC分类号： H01F500
CPC分类号： H01L28/10 , H01F17/0006 , H01F17/0013 , H01F17/0033 , H01F41/046 , H01L27/08 , Y10T29/4902 , Y10T29/49073
摘要： A method for fabricating inductors and transformers on integrated circuits. A magnetic material is formed on the semiconductor substrate. The magnetic material comprises a suspension of magnetic material in an insulator. A metal film is formed that forms at least one coil around the magnetic material forming an inductor structure. Two adjacent coils can be linked with the magnetic material to form a transformer.

10. 发明授权

US6028345A Reduced resistance base contact for single polysilicon bipolar transistors using extrinsic base diffusion from a diffusion source dielectric layer 失效
标题翻译：使用来自扩散源电介质层的外部基极扩散来降低单晶硅双极晶体管的电阻基极接触
公开(公告)号：US6028345A
公开(公告)日：2000-02-22
申请号：US486910
申请日：1995-06-07
申请人： F. Scott Johnson
发明人： F. Scott Johnson
IPC分类号： H01L29/73 , H01L21/331 , H01L29/10 , H01L29/732 , H01L29/00 , H01L27/082
CPC分类号： H01L29/66272 , H01L29/1004 , Y10S148/01
摘要： A bipolar transistor (100) and a method for forming the same. A diffusion source dielectric layer (118) is deposited over a semiconductor body (101). An emitter window (116) is then etched through the diffusion source dielectric layer (118). An extrinsic base region (110) is diffused from the diffusion source dielectric layer (118). The intrinsic base region (108) is then implanted. Base-emitter spacers (120) are then formed followed by the emitter electrode (124) and emitter region (126). The extrinsic base region (110) is self-aligned to the emitter eliminating the alignment tolerances for the lateral diffusion of the extrinsic base implant and an extrinsic base implant.
摘要翻译：双极晶体管（100）及其形成方法。扩散源电介质层（118）沉积在半导体本体（101）上。然后通过扩散源电介质层（118）蚀刻发射器窗口（116）。外部基极区域（110）从扩散源电介质层（118）扩散。然后植入本征基区（108）。然后形成基极 - 发射极间隔物（120），随后是发射极（124）和发射极区（126）。外部基极区域（110）与发射极自对准，消除了外部基极植入物和外部基极植入物的横向扩散的对准公差。

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