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1. 发明申请

US20060270139A1 Methods for Transistor Formation Using Selective Gate Implantation 审中-公开
标题翻译：使用选择性栅植入的晶体管形成方法
公开(公告)号：US20060270139A1
公开(公告)日：2006-11-30
申请号：US11462528
申请日：2006-08-04
申请人： F. Scott Johnson , Tad Grider , Benjamin McKee
发明人： F. Scott Johnson , Tad Grider , Benjamin McKee
IPC分类号： H01L21/8238
CPC分类号： H01L21/26513 , H01L21/28035 , H01L21/324 , H01L29/4916 , H01L29/66545 , H01L29/6656 , H01L29/6659 , H01L29/7833
摘要： Methods are disclosed for semiconductor device fabrication in which dopants are selectively implanted into transistor gate structures to counteract or compensate for dopant depletion during subsequent fabrication processing. A patterned implant mask is formed over a semiconductor device, which exposes at least a portion of the gate structure and covers the remaining upper surfaces of the device. Thereafter, dopants are selectively implanted into the exposed gate structure.
摘要翻译：公开了用于半导体器件制造的方法，其中将掺杂剂选择性地注入到晶体管栅极结构中以抵消或补偿在随后的制造处理期间的掺杂剂耗尽。图案化的注入掩模形成在半导体器件上，其暴露栅极结构的至少一部分并且覆盖器件的剩余上表面。此后，将掺杂剂选择性地注入到暴露的栅极结构中。

2. 发明授权

US07098098B2 Methods for transistors formation using selective gate implantation 有权
公开(公告)号：US07098098B2
公开(公告)日：2006-08-29
申请号：US10226536
申请日：2002-08-23
申请人： F. Scott Johnson , Tad Grider , Benjamin P. Mckee
发明人： F. Scott Johnson , Tad Grider , Benjamin P. Mckee
IPC分类号： H01L21/8238 , H01L21/336 , H01L21/8234 , H01L21/04
CPC分类号： H01L29/66545 , H01L21/26513 , H01L21/28035 , H01L21/324 , H01L29/4916 , H01L29/6656 , H01L29/6659 , H01L29/7833
摘要： Methods are disclosed for semiconductor device fabrication in which dopants are selectively implanted into transistor gate structures to counteract or compensate for dopant depletion during subsequent fabrication processing. A patterned implant mask is formed over a semiconductor device, which exposes at least a portion of the gate structure and covers the remaining upper surfaces of the device. Thereafter, dopants are selectively implanted into the exposed gate structure.

3. 发明授权

US06501152B1 Advanced lateral PNP by implant negation 有权
标题翻译：先进的横向PNP通过植入物否定
公开(公告)号：US06501152B1
公开(公告)日：2002-12-31
申请号：US09371645
申请日：1999-08-10
申请人： F. Scott Johnson
发明人： F. Scott Johnson
IPC分类号： H01L2900
CPC分类号： H01L29/6625 , H01L21/8249 , H01L27/0623 , H01L29/735
摘要： A lateral NPN transistor (LPNP) (102) having the lightly doped drain extension implant blocked from the emitter region (118) but not the collector region (120). Accordingly, the emitter region (118) has a more abrupt junction for high emitter injection efficiency while the collector region (120) has a lightly doped region for reduced base depletion.
摘要翻译：具有轻掺杂漏极延伸注入的横向NPN晶体管（LPNP）（102）从发射极区域（118）而不是集电极区域（120）阻挡。因此，发射极区域（118）具有更高的发射极注入效率的突变结，而集电极区域（120）具有用于减少碱基耗尽的轻掺杂区域。

4. 发明授权

US06194280B1 Method for forming a self-aligned BJT emitter contact 有权
标题翻译：形成自对准BJT发射极触点的方法
公开(公告)号：US06194280B1
公开(公告)日：2001-02-27
申请号：US09262389
申请日：1999-03-04
申请人： F. Scott Johnson
发明人： F. Scott Johnson
IPC分类号： H01L21331
CPC分类号： H01L29/66272
摘要： A bipolar transistor includes a collector region, an intrinsic base region within the collector region, an extrinsic base region within the collector region, and a base link-up region within the collector region between the intrinsic base region and the extrinsic base region. An emitter region is positioned within the intrinsic base region. A base electrode overlays and is in electrical communication with a portion of the extrinsic base region and the base link-up region, and a doped inter-polysilicon dielectric layer overlays a portion of the base electrode. A capping layer is positioned above the inter-polysilicon dielectric layer; and an emitter electrode overlays the inter-polysilicon dielectric layer and the emitter region. The doped inter-polysilicon dielectric layer is the dopant source for forming the extrinsic base region and the base link-up region.
摘要翻译：双极晶体管包括集电极区域，集电极区域内的本征基极区域，集电极区域内的非本征基极区域，以及在本征基极区域和外部基极区域之间的集电极区域内的基极连接区域。发射极区域位于本征基区内。基极覆盖并与外部基极区域和基极连接区域的一部分电连通，并且掺杂的多晶硅间介电层覆盖基极的一部分。覆盖层位于多晶硅间介质层的上方; 并且发射极电极覆盖多晶硅间介质层和发射极区域。掺杂的多晶硅间介质层是用于形成外部基极区域和基极连接区域的掺杂剂源。

5. 发明授权

US5616508A High speed bipolar transistor using a patterned etch stop and diffusion source 失效
标题翻译：使用图案化蚀刻停止和扩散源的高速双极晶体管
公开(公告)号：US5616508A
公开(公告)日：1997-04-01
申请号：US370137
申请日：1995-01-09
申请人： F. Scott Johnson
发明人： F. Scott Johnson
IPC分类号： H01L29/73 , H01L21/331 , H01L21/8249 , H01L27/06 , H01L29/732 , H01L21/265
CPC分类号： H01L29/66272 , H01L29/7322
摘要： A bipolar transistor (100) and a method for forming the same. A base-link diffusion source layer (118) is formed over a portion of the collector region (102). The base-link diffusion source layer (118) comprises a material that is capable of being used as a dopant source and is capable of being etched selectively with respect to silicon. A base electrode (114) is formed over at least one end portion of the base-link diffusion source layer (118) and the exposed portions of the base-link diffusion source layer (118) are removed. An extrinsic base region (110) is diffused from the base electrode (114) and a base link-up region (112) is diffused from the base-link diffusion source layer (118). Processing may then continue to form an intrinsic base region (108), emitter region (126), and emitter electrode (124).
摘要翻译：双极晶体管（100）及其形成方法。在集电极区域（102）的一部分上形成基极 - 链路扩散源层（118）。基极 - 链路扩散源层（118）包括能够用作掺杂剂源并且能够相对于硅选择性蚀刻的材料。基极电极（114）形成在基极 - 链路扩散源层（118）的至少一个端部上，并且去除基极 - 链路扩散源层（118）的暴露部分。外部基极区域（110）从基极（114）扩散，基极连接区域（112）从基极扩散源层（118）扩散。然后，处理可以继续形成本征基极区域（108），发射极区域（126）和发射极电极（124）。

6. 发明授权

US5593905A Method of forming stacked barrier-diffusion source and etch stop for double polysilicon BJT with patterned base link 失效
标题翻译：形成层叠阻挡扩散源的方法和具有图案化基极连接的双重多晶硅BJT的蚀刻停止
公开(公告)号：US5593905A
公开(公告)日：1997-01-14
申请号：US392597
申请日：1995-02-23
申请人： F. Scott Johnson , Kelly Taylor
发明人： F. Scott Johnson , Kelly Taylor
IPC分类号： H01L29/73 , H01L21/331 , H01L21/8249 , H01L27/06 , H01L29/10 , H01L29/732 , H01L21/265
CPC分类号： H01L29/66272 , H01L29/1004 , Y10S148/01 , Y10S148/011
摘要： A bipolar transistor (100) and a method for forming the same. A base-link diffusion source layer (118) is formed over a portion of the collector region (102). The base-link diffusion source layer (118) comprises a material that is capable of being used as a dopant source and is capable of being etched selectively with respect to silicon. A barrier layer (119) is formed over the base-link diffusion source layer (118).A base electrode (114) is formed over at least one end portion of the barrier layer (119) and base-link diffusion source layer (118) and the exposed portions of the barrier layer (119) and underlying base-link diffusion source layer (118) are removed. An extrinsic base region (110) is diffused from the base electrode (114) and a base link-up region (112) is diffused from the base-link diffusion source layer (118). Processing may then continue to fore an intrinsic base region (108), emitter region (126), and emitter electrode (124).
摘要翻译：双极晶体管（100）及其形成方法。在集电极区域（102）的一部分上形成基极 - 链路扩散源层（118）。基极 - 链路扩散源层（118）包括能够用作掺杂剂源并且能够相对于硅选择性蚀刻的材料。在该基极连接扩散源层（118）的上方形成阻挡层（119）。在阻挡层（119）的至少一个端部与基极扩散源层（118）的至少一个端部形成有基极）并且去除了阻挡层（119）和下面的基底 - 链路扩散源层（118）的暴露部分。外部基极区域（110）从基极（114）扩散，基极连接区域（112）从基极扩散源层（118）扩散。然后处理可以继续在本征基区（108），发射极区（126）和发射极（124）之前。

7. 发明授权

US5592017A Self-aligned double poly BJT using sige spacers as extrinsic base contacts 失效
标题翻译：自对准双聚BJT使用精密间隔物作为外在基接触
公开(公告)号：US5592017A
公开(公告)日：1997-01-07
申请号：US473415
申请日：1995-06-07
申请人： F. Scott Johnson
发明人： F. Scott Johnson
IPC分类号： H01L29/73 , H01L21/331 , H01L29/732 , H01L29/737
CPC分类号： H01L29/66272
摘要： A bipolar transistor (100) and a method for forming the same. A base electrode (114) is separated from the collector region (102) by an insulator layer (110). A doped conductive spacer (115) is formed laterally adjacent the base electrode (114). The conductive spacer (115) comprises a conductive material that is capable of serving as a dopant source for n and p-type dopants and is able to be selectively etched with respect to silicon (e.g., silicon-germanium). Base link-up region (112) is diffused from conductive spacer (115) into the collector region (102). Processing then continues to form an intrinsic base region (108), emitter region (126), and emitter electrode (124).
摘要翻译：双极晶体管（100）及其形成方法。基极（114）通过绝缘体层（110）与集电极区域（102）分离。掺杂的导电间隔物（115）横向邻近基极（114）形成。导电间隔物（115）包括能够用作n型和p型掺杂剂的掺杂剂源并且能够相对于硅（例如，硅 - 锗）选择性地蚀刻的导电材料。基极连接区域（112）从导电间隔物（115）扩散到集电极区域（102）中。然后处理继续形成本征基极区域（108），发射极区域（126）和发射极电极（124）。

8. 发明授权

US5541121A Reduced resistance base contact method for single polysilicon bipolar transistors using extrinsic base diffusion from a diffusion source dielectric layer 失效
标题翻译：使用来自扩散源电介质层的外部基极扩散的单晶硅双极晶体管的降低的电阻基极接触方法
公开(公告)号：US5541121A
公开(公告)日：1996-07-30
申请号：US380906
申请日：1995-01-30
申请人： F. Scott Johnson
发明人： F. Scott Johnson
IPC分类号： H01L29/73 , H01L21/331 , H01L29/10 , H01L29/732 , H01L21/265
CPC分类号： H01L29/66272 , H01L29/1004 , Y10S148/01
摘要： A bipolar transistor (100) and a method for forming the same. A diffusion source dielectric layer (118) is deposited over a semiconductor body (101). An emitter window (116) is then etched through the diffusion source dielectric layer (118). An extrinsic base region (110) is diffused from the diffusion source dielectric layer (118). The intrinsic base region (108) is then implanted. Base-emitter spacers (120) are then formed followed by the emitter electrode (124) and emitter region (126). The extrinsic base region (110) is self-aligned to the emitter eliminating the alignment tolerances for the lateral diffusion of the extrinsic base implant and an extrinsic base implant.
摘要翻译：双极晶体管（100）及其形成方法。扩散源电介质层（118）沉积在半导体本体（101）上。然后通过扩散源电介质层（118）蚀刻发射器窗口（116）。外部基极区域（110）从扩散源电介质层（118）扩散。然后植入本征基区（108）。然后形成基极 - 发射极间隔物（120），随后是发射极（124）和发射极区（126）。外部基极区域（110）与发射极自对准，消除了外部基极植入物和外部基极植入物的横向扩散的对准公差。

9. 发明授权

US07572693B2 Methods for transistor formation using selective gate implantation 有权
标题翻译：使用选择性栅极注入的晶体管形成方法
公开(公告)号：US07572693B2
公开(公告)日：2009-08-11
申请号：US11462541
申请日：2006-08-04
申请人： F. Scott Johnson , Tad Grider , Benjamin P. McKee
发明人： F. Scott Johnson , Tad Grider , Benjamin P. McKee
IPC分类号： H01L21/8238 , H01L21/336 , H01L21/8234 , H01L21/04
CPC分类号： H01L21/28035 , H01L29/66545 , H01L29/6656 , H01L29/6659 , H01L29/7833
摘要： Methods are disclosed for semiconductor device fabrication in which dopants are selectively implanted into transistor gate structures to counteract or compensate for dopant depletion during subsequent fabrication processing. A patterned implant mask is formed over a semiconductor device, which exposes at least a portion of the gate structure and covers the remaining upper surfaces of the device. Thereafter, dopants are selectively implanted in to the exposed gate structure.
摘要翻译：公开了用于半导体器件制造的方法，其中将掺杂剂选择性地注入到晶体管栅极结构中以抵消或补偿在随后的制造处理期间的掺杂剂耗尽。图案化的注入掩模形成在半导体器件上，其暴露栅极结构的至少一部分并且覆盖器件的剩余上表面。此后，将掺杂剂选择性地植入到暴露的栅极结构中。

10. 发明申请

US20080233695A1 Integration method of inversion oxide (TOXinv) thickness reduction in CMOS flow without added pattern 审中-公开
标题翻译： CMOS流程中反向氧化（TOXinv）厚度减小的积分方法，无添加图案
公开(公告)号：US20080233695A1
公开(公告)日：2008-09-25
申请号：US11725417
申请日：2007-03-19
申请人： Shashank S. Ekbote , F. Scott Johnson
发明人： Shashank S. Ekbote , F. Scott Johnson
IPC分类号： H01L21/8238
CPC分类号： H01L21/823807
摘要： A method of manufacturing a CMOS semiconductor comprising, forming shallow trench isolation regions in a workpiece, depositing a gate oxide layer on top of the workpiece, depositing a polysilicon layer on top of the gate oxide, performing VTN patterning, performing first series of adjusted implantations, performing post implantation cleaning, performing VTP patterning, performing a second series of adjusted implantations, performing the post implantation cleaning, performing a well implant damage anneal; patterning gate, etching gate, and performing back end of line processing.
摘要翻译：一种制造CMOS半导体的方法，包括：在工件中形成浅沟槽隔离区域，在工件的顶部上沉积栅极氧化物层，在栅极氧化物的顶部上沉积多晶硅层，执行VT N N 图案化，执行第一系列调整的植入，执行植入后清洁，执行VT图案化，执行第二系列调整的植入，执行植入后清洁，执行井注入损伤退火; 图案化栅极，蚀刻栅极，以及执行线路处理的后端。

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