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1. 发明授权

US06462141B1 Diene copolymer substituted by alkoxy silane, and organic and inorganic hybrid composition comprising the same 失效
标题翻译：由烷氧基硅烷取代的二烯共聚物和包含它们的有机和无机杂化组合物
公开(公告)号：US06462141B1
公开(公告)日：2002-10-08
申请号：US09460643
申请日：1999-12-15
申请人： Eun-Kyoung Kim , Hyung-Suk Cho , Young-Pil Kim
发明人： Eun-Kyoung Kim , Hyung-Suk Cho , Young-Pil Kim
IPC分类号： C08F800
CPC分类号： C08F8/42 , C08C19/25
摘要： The present invention relates to alkoxysilane-substituted diene copolymers, organic and inorganic hybrid complex compositions comprising the same and a process for the preparation of the same. The alkoxysilane-substituted diene copolymers are prepared by reacting a diene copolymer substituted by epoxy or hydroxy groups with a silane compound. Thus prepared alkoxysilane-substituted diene copolymer is characterized by the facts that it is in organic solvents and it is capable of being cured at low temperatures. The present invention also relates to a composition prepared by mixing the said copolymer with inorganic fillers and/or coupling agents. The copolymer of the formula (1) has high reactivity with coupling agents since it possesses reactive silane groups and thus provides the diene polymer composition as having improved compatibility with inorganic fillers. In addition, when the copolymer of the formula (1) is added to a sol-gel reactant, a substitution reaction proceeds smoothly even under mild reaction conditions and thus it is possible to introduce the third functional group to copolymer blocks.
摘要翻译：本发明涉及烷氧基硅烷取代的二烯共聚物，包含它们的有机和无机杂化复合组合物及其制备方法。烷氧基硅烷取代的二烯共聚物通过使被环氧基或羟基取代的二烯共聚物与硅烷化合物反应来制备。由此制备的烷氧基硅烷取代的二烯共聚物的特征在于它在有机溶剂中并且能够在低温下固化。本发明还涉及通过将所述共聚物与无机填料和/或偶联剂混合而制备的组合物。式（1）的共聚物与偶联剂具有高反应性，因为它具有反应性硅烷基团，因此提供二烯聚合物组合物具有改善的与无机填料的相容性。此外，当将式（1）的共聚物加入到溶胶 - 凝胶反应物中时，即使在温和的反应条件下，取代反应也能顺利进行，因此可以将第三官能团引入共聚物嵌段。

2. 发明授权

US08853010B2 Semiconductor device and method of fabricating the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US08853010B2
公开(公告)日：2014-10-07
申请号：US13368584
申请日：2012-02-08
申请人： Heung-Kyu Park , Woo-Bin Song , Nam-Kyu Kim , Su-Jin Jung , Byeong-Chan Lee , Young-Pil Kim , Sun-Ghil Lee
发明人： Heung-Kyu Park , Woo-Bin Song , Nam-Kyu Kim , Su-Jin Jung , Byeong-Chan Lee , Young-Pil Kim , Sun-Ghil Lee
IPC分类号： H01L21/00 , H01L21/84 , H01L21/336 , H01L21/337 , H01L21/338 , H01L21/339 , H01L29/165 , H01L29/78 , H01L29/66 , H01L21/8238
CPC分类号： H01L29/7848 , H01L21/823807 , H01L21/823814 , H01L29/1608 , H01L29/165 , H01L29/66545 , H01L29/66621 , H01L29/66651 , H01L29/78
摘要： A semiconductor device comprises a substrate and first and second stress-generating epitaxial regions on the substrate and spaced apart from each other. A channel region is on the substrate and positioned between the first and second stress-generating epitaxial regions. A gate electrode is on the channel region. The channel region is an epitaxial layer, and the first and second stress-generating epitaxial regions impart a stress on the channel region.
摘要翻译：半导体器件包括衬底和在衬底上彼此间隔开的第一和第二应力产生外延区域。沟道区位于衬底上并位于第一和第二应力产生外延区之间。栅电极在沟道区上。沟道区域是外延层，并且第一和第二应力产生外延区域对沟道区域施加应力。

3. 发明申请

US20070131159A1 Method for epitaxial growth with selectivity 审中-公开
标题翻译：用选择性外延生长的方法
公开(公告)号：US20070131159A1
公开(公告)日：2007-06-14
申请号：US11638373
申请日：2006-12-14
申请人： Young-Pil Kim , Jin Kim , Min-Gu Kang , Yu-Gyun Shin , Jong-Wook Lee
发明人： Young-Pil Kim , Jin Kim , Min-Gu Kang , Yu-Gyun Shin , Jong-Wook Lee
IPC分类号： C30B13/00 , C30B19/00 , C30B28/08 , C30B23/00
CPC分类号： C30B25/18 , C30B29/06 , C30B29/08 , C30B33/12
摘要： A method for growing an epitaxial layer includes obtaining a semiconductor substrate having a plurality of insulating and conductive surfaces, adsorbing a first source gas into the plurality of conductive surfaces to grow a first epitaxial layer thereon, such that the first epitaxial layer has lateral portions overhanging the insulating surfaces, etching the first epitaxial layer to form an etched epitaxial layer, such that the etched epitaxial layer has curved surfaces, and supplying a second source gas to trigger additional epitaxial growth in the etched epitaxial layer.
摘要翻译：一种用于生长外延层的方法包括获得具有多个绝缘和导电表面的半导体衬底，将第一源气体吸附到多个导电表面中以在其上生长第一外延层，使得第一外延层具有悬垂的侧向部分蚀刻第一外延层以形成蚀刻的外延层，使得蚀刻的外延层具有弯曲表面，并且提供第二源气体以触发蚀刻的外延层中的另外的外延生长。

4. 发明授权

US07176533B2 Semiconductor devices having contact plugs including polysilicon doped with an impurity having a lesser diffusion coefficient than phosphorus 有权
标题翻译：具有接触插塞的半导体器件包括掺杂有比磷少的扩散系数的杂质的多晶硅
公开(公告)号：US07176533B2
公开(公告)日：2007-02-13
申请号：US10982113
申请日：2004-11-04
申请人： Eun-Ae Chung , Myoung-Bum Lee , Young-Pil Kim , Jin-Gyun Kim , Bean-Jun Jin
发明人： Eun-Ae Chung , Myoung-Bum Lee , Young-Pil Kim , Jin-Gyun Kim , Bean-Jun Jin
IPC分类号： H01L29/76
CPC分类号： H01L21/76877 , H01L21/2257 , H01L21/28525 , H01L23/485 , H01L2924/0002 , H01L2924/00
摘要： Forming a semiconductor device can include forming an insulating layer on a semiconductor substrate including a conductive region thereof, wherein the insulating layer has a contact hole therein exposing a portion of the conductive region. A polysilicon contact plug can be formed in the contact hole wherein at least a portion of the polysilicon contact plug is doped with an element having a diffusion coeffient that is less than a diffusion coefficient of phosphorus (P). Related structures are also discussed.
摘要翻译：形成半导体器件可以包括在包括其导电区域的半导体衬底上形成绝缘层，其中绝缘层具有暴露导电区域的一部分的接触孔。可以在接触孔中形成多晶硅接触插塞，其中多晶硅接触插塞的至少一部分掺杂有具有小于磷（P）的扩散系数的扩散系数的元件。还讨论了相关结构。

5. 发明申请

US20060283380A1 Semiconductor device and method of manufacturing the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US20060283380A1
公开(公告)日：2006-12-21
申请号：US11398118
申请日：2006-04-05
申请人： Sun-Ghil Lee , Young-Pil Kim , Yu-Gyun Shin , Jong-Wook Lee , Young-Eun Lee
发明人： Sun-Ghil Lee , Young-Pil Kim , Yu-Gyun Shin , Jong-Wook Lee , Young-Eun Lee
IPC分类号： C30B23/00 , C30B25/00 , C30B28/12 , C30B28/14
CPC分类号： C30B29/06 , C30B15/00
摘要： A semiconductor device formed on a strained silicon layer and a method of manufacturing such a semiconductor device are disclosed. In accordance with this invention, a first silicon germanium layer is formed on a single crystalline silicon substrate; a second silicon germanium layer is formed on the first silicon germanium layer, the second silicon germanium layer having a concentration of germanium in a range of about 1 percent by weight to about 15 percent by weight based on the total weight of the second silicon germanium layer; a strained silicon layer is formed on the second silicon germanium layer; an isolation layer is formed at a first portion of the strained silicon layer; a gate structure is formed on the strained silicon layer; and, source/drain regions are formed at second portions of the strained silicon layer adjacent to the gate structure to form a transistor.
摘要翻译：公开了一种形成在应变硅层上的半导体器件及其制造方法。根据本发明，在单晶硅衬底上形成第一硅锗层; 第二硅锗层形成在第一硅锗层上，第二硅锗层的锗浓度在约1重量％至约15重量％的范围内，基于第二硅锗层的总重量 ; 在第二硅锗层上形成应变硅层; 在应变硅层的第一部分处形成隔离层; 在应变硅层上形成栅极结构; 并且源极/漏极区域形成在与栅极结构相邻的应变硅层的第二部分处以形成晶体管。

6. 发明申请

US20060079056A1 Semiconductor structures having a strained silicon layer on a silicon-germanium layer and related fabrication methods 审中-公开
标题翻译：在硅锗层上具有应变硅层的半导体结构和相关的制造方法
公开(公告)号：US20060079056A1
公开(公告)日：2006-04-13
申请号：US11247412
申请日：2005-10-11
申请人： Young-Pil Kim , Sun-Ghil Lee , Yu-Gyun Shin , Jong-Wook Lee , In-Soo Jung
发明人： Young-Pil Kim , Sun-Ghil Lee , Yu-Gyun Shin , Jong-Wook Lee , In-Soo Jung
IPC分类号： H01L21/336
CPC分类号： H01L29/1054 , H01L21/02381 , H01L21/0245 , H01L21/0251 , H01L21/02532 , H01L21/02579 , H01L21/02639 , H01L29/78
摘要： A semiconductor structure including a SiGe layer and a method of fabricating the same are provided. The structure includes a silicon layer heavily doped with impurities. A SiGe layer is disposed on the silicon layer. A strained silicon layer is disposed on the SiGe layer. The impurities may be boron. The boron in the silicon layer may have a concentration of 1016 to 1020/cm3. Boron in the SiGe layer, diffused from the silicon substrate or directly doped, may suppress movement of misfit dislocation occurring in the SiGe layer toward the surface, thereby reducing a threading dislocation density near the surface of the strained silicon layer.
摘要翻译：提供了包括SiGe层的半导体结构及其制造方法。该结构包括重掺杂杂质的硅层。 SiGe层设置在硅层上。应变硅层设置在SiGe层上。杂质可以是硼。硅层中的硼可以具有10 16至10 20 / cm 3的浓度。在SiGe层中从硅衬底扩散或直接掺杂的硼可以抑制SiGe层中发生的失配位错的移动朝向表面，由此降低应变硅层表面附近的穿透位错密度。

7. 发明授权

US08119486B2 Methods of manufacturing semiconductor devices having a recessed-channel 有权
标题翻译：制造具有凹槽的半导体器件的方法
公开(公告)号：US08119486B2
公开(公告)日：2012-02-21
申请号：US12984176
申请日：2011-01-04
申请人： Young-Pil Kim , Eun-Ae Chung , Gab-Jin Nam , Hee-Don Hwang , Ji-Young Min
发明人： Young-Pil Kim , Eun-Ae Chung , Gab-Jin Nam , Hee-Don Hwang , Ji-Young Min
IPC分类号： H01L21/336
CPC分类号： H01L27/10876 , H01L29/66628
摘要： A method according to example embodiments includes forming isolation regions in a substrate, the isolation regions defining active regions. Desired regions of the active regions and the isolation regions are removed, thereby forming recess channel trenches to a desired depth. The recess channel trenches are fog to have a first region in contact with the active regions and a second region in contact with the isolation regions. A width of a bottom surface of the recess channel trenches is less than that of a top surface thereof. The active regions and the isolation regions are annealed to uplift the bottom surface of the recess channel trenches. An area of the bottom surface of the first region is increased. A depth of the bottom surface of the first region is reduced.
摘要翻译：根据示例实施例的方法包括在衬底中形成隔离区域，所述隔离区限定活性区域。去除有源区域和隔离区域的期望区域，从而形成凹槽沟槽到期望的深度。凹槽沟槽是雾化的，以具有与活性区域接触的第一区域和与隔离区域接触的第二区域。凹槽沟槽的底面的宽度小于其顶面的宽度。有源区域和隔离区域被退火以提高凹槽通道沟槽的底面。第一区域的底面的面积增加。第一区域的底面的深度减小。

8. 发明授权

US07867865B2 Methods of fabricating semiconductor devices including elevated source and drain regions 有权
标题翻译：制造包括升高的源极和漏极区域的半导体器件的方法
公开(公告)号：US07867865B2
公开(公告)日：2011-01-11
申请号：US12166575
申请日：2008-07-02
申请人： Jin-Bum Kim , Young-Pil Kim , Jung-Yun Won , Hion-Suck Baik , Jun-Ho Lee
发明人： Jin-Bum Kim , Young-Pil Kim , Jung-Yun Won , Hion-Suck Baik , Jun-Ho Lee
IPC分类号： H01L21/336
CPC分类号： H01L21/823456 , H01L21/823418 , H01L27/1052 , H01L27/10876 , H01L27/10894 , H01L29/4236 , H01L29/66621
摘要： Methods of fabricating semiconductor devices are provided. A substrate having active patterns and isolating layer patterns is prepared. Each of the isolating layer patterns has an upper surface higher than that of each of the active patterns. A spacer layer having a uniform thickness is formed on the substrate. The spacer layer is etched to form a spacer on a sidewall of each of the isolating layer patterns. A gate structure is formed on each of the active patterns. A selective epitaxial growth (SEG) process is performed on the active patterns having the gate structure to form isolated epitaxial layers that have upper surfaces higher than those of the isolating layer patterns, on the active patterns. Related semiconductor devices are also provided.
摘要翻译：提供制造半导体器件的方法。制备具有活性图案和隔离层图案的基板。每个隔离层图案的上表面高于每个活动图案的上表面。在基板上形成具有均匀厚度的间隔层。蚀刻间隔层以在每个隔离层图案的侧壁上形成间隔物。在每个有源图案上形成栅极结构。对具有栅极结构的有源图案进行选择性外延生长（SEG）处理，以在活性图案上形成具有高于绝缘层图案的上表面的隔离的外延层。还提供了相关的半导体器件。

9. 发明申请

US20090239348A1 SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US20090239348A1
公开(公告)日：2009-09-24
申请号：US12478345
申请日：2009-06-04
申请人： Sun-Ghil Lee , Young-Pil Kim , Yu-Gyun Shin , Jong-Wook Lee , Young-Eun Lee
发明人： Sun-Ghil Lee , Young-Pil Kim , Yu-Gyun Shin , Jong-Wook Lee , Young-Eun Lee
IPC分类号： H01L21/336
CPC分类号： C30B29/06 , C30B15/00
摘要： A semiconductor device formed on a strained silicon layer and a method of manufacturing such a semiconductor device are disclosed. In accordance with this invention, a first silicon germanium layer is formed on a single crystalline silicon substrate; a second silicon germanium layer is formed on the first silicon germanium layer, the second silicon germanium layer having a concentration of germanium in a range of about 1 percent by weight to about 15 percent by weight based on the total weight of the second silicon germanium layer; a strained silicon layer is formed on the second silicon germanium layer; an isolation layer is formed at a first portion of the strained silicon layer; a gate structure is formed on the strained silicon layer; and, source/drain regions are formed at second portions of the strained silicon layer adjacent to the gate structure to form a transistor.
摘要翻译：公开了一种形成在应变硅层上的半导体器件及其制造方法。根据本发明，在单晶硅衬底上形成第一硅锗层; 第二硅锗层形成在第一硅锗层上，第二硅锗层的锗浓度在约1重量％至约15重量％的范围内，基于第二硅锗层的总重量 ; 在第二硅锗层上形成应变硅层; 在应变硅层的第一部分处形成隔离层; 在应变硅层上形成栅极结构; 并且源极/漏极区域形成在与栅极结构相邻的应变硅层的第二部分处以形成晶体管。

10. 发明申请

US20090008717A1 Semiconductor Devices Including Elevated Source and Drain Regions and Methods of Fabricating the Same 有权
标题翻译：包括提升源和排水区的半导体器件及其制造方法
公开(公告)号：US20090008717A1
公开(公告)日：2009-01-08
申请号：US12166575
申请日：2008-07-02
申请人： Jin-Bum Kim , Young-Pil Kim , Jung-Yun Won , Hion-Suck Baik , Jun-Ho Lee
发明人： Jin-Bum Kim , Young-Pil Kim , Jung-Yun Won , Hion-Suck Baik , Jun-Ho Lee
IPC分类号： H01L21/336 , H01L27/088
CPC分类号： H01L21/823456 , H01L21/823418 , H01L27/1052 , H01L27/10876 , H01L27/10894 , H01L29/4236 , H01L29/66621
摘要： Methods of fabricating semiconductor devices are provided. A substrate having active patterns and isolating layer patterns is prepared. Each of the isolating layer patterns has an upper surface higher than that of each of the active patterns. A spacer layer having a uniform thickness is formed on the substrate. The spacer layer is etched to form a spacer on a sidewall of each of the isolating layer patterns. A gate structure is formed on each of the active patterns. A selective epitaxial growth (SEG) process is performed on the active patterns having the gate structure to form isolated epitaxial layers that have upper surfaces higher than those of the isolating layer patterns, on the active patterns. Related semiconductor devices are also provided.
摘要翻译：提供制造半导体器件的方法。制备具有活性图案和隔离层图案的基板。每个隔离层图案的上表面高于每个活动图案的上表面。在基板上形成具有均匀厚度的间隔层。蚀刻间隔层以在每个隔离层图案的侧壁上形成间隔物。在每个有源图案上形成栅极结构。对具有栅极结构的有源图案进行选择性外延生长（SEG）处理，以在活性图案上形成具有高于绝缘层图案的上表面的隔离的外延层。还提供了相关的半导体器件。

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