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1. 发明授权

US08853010B2 Semiconductor device and method of fabricating the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US08853010B2
公开(公告)日：2014-10-07
申请号：US13368584
申请日：2012-02-08
申请人： Heung-Kyu Park , Woo-Bin Song , Nam-Kyu Kim , Su-Jin Jung , Byeong-Chan Lee , Young-Pil Kim , Sun-Ghil Lee
发明人： Heung-Kyu Park , Woo-Bin Song , Nam-Kyu Kim , Su-Jin Jung , Byeong-Chan Lee , Young-Pil Kim , Sun-Ghil Lee
IPC分类号： H01L21/00 , H01L21/84 , H01L21/336 , H01L21/337 , H01L21/338 , H01L21/339 , H01L29/165 , H01L29/78 , H01L29/66 , H01L21/8238
CPC分类号： H01L29/7848 , H01L21/823807 , H01L21/823814 , H01L29/1608 , H01L29/165 , H01L29/66545 , H01L29/66621 , H01L29/66651 , H01L29/78
摘要： A semiconductor device comprises a substrate and first and second stress-generating epitaxial regions on the substrate and spaced apart from each other. A channel region is on the substrate and positioned between the first and second stress-generating epitaxial regions. A gate electrode is on the channel region. The channel region is an epitaxial layer, and the first and second stress-generating epitaxial regions impart a stress on the channel region.
摘要翻译：半导体器件包括衬底和在衬底上彼此间隔开的第一和第二应力产生外延区域。沟道区位于衬底上并位于第一和第二应力产生外延区之间。栅电极在沟道区上。沟道区域是外延层，并且第一和第二应力产生外延区域对沟道区域施加应力。

2. 发明申请

US20150008452A1 SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME 审中-公开
标题翻译：半导体器件及其制造方法
公开(公告)号：US20150008452A1
公开(公告)日：2015-01-08
申请号：US14492628
申请日：2014-09-22
申请人： Heung-Kyu Park , Woo-Bin Song , Nam-Kyu Kim , Su-Jin Jung , Byeong-Chan Lee , Young-Pil Kim , Sun-Ghil Lee
发明人： Heung-Kyu Park , Woo-Bin Song , Nam-Kyu Kim , Su-Jin Jung , Byeong-Chan Lee , Young-Pil Kim , Sun-Ghil Lee
IPC分类号： H01L29/78 , H01L29/16 , H01L29/165
CPC分类号： H01L29/7848 , H01L21/823807 , H01L21/823814 , H01L29/1608 , H01L29/165 , H01L29/66545 , H01L29/66621 , H01L29/66651 , H01L29/78
摘要： A semiconductor device comprises a substrate and first and second stress-generating epitaxial regions on the substrate and spaced apart from each other. A channel region is on the substrate and positioned between the first and second stress-generating epitaxial regions. A gate electrode is on the channel region. The channel region is an epitaxial layer, and the first and second stress-generating epitaxial regions impart a stress on the channel region.
摘要翻译：半导体器件包括衬底和在衬底上彼此间隔开的第一和第二应力产生外延区域。沟道区位于衬底上并位于第一和第二应力产生外延区之间。栅电极在沟道区上。沟道区域是外延层，并且第一和第二应力产生外延区域对沟道区域施加应力。

3. 发明申请

US20130005096A1 SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME 有权
公开(公告)号：US20130005096A1
公开(公告)日：2013-01-03
申请号：US13368584
申请日：2012-02-08
申请人： Heung-Kyu Park , Woo-Bin Song , Nam-Kyu Kim , Su-Jin Jung , Byeong-Chan Lee , Young-Pil Kim , Sun-Ghil Lee
发明人： Heung-Kyu Park , Woo-Bin Song , Nam-Kyu Kim , Su-Jin Jung , Byeong-Chan Lee , Young-Pil Kim , Sun-Ghil Lee
IPC分类号： H01L21/8238 , H01L21/336
CPC分类号： H01L29/7848 , H01L21/823807 , H01L21/823814 , H01L29/1608 , H01L29/165 , H01L29/66545 , H01L29/66621 , H01L29/66651 , H01L29/78
摘要： A semiconductor device comprises a substrate and first and second stress-generating epitaxial regions on the substrate and spaced apart from each other. A channel region is on the substrate and positioned between the first and second stress-generating epitaxial regions. A gate electrode is on the channel region. The channel region is an epitaxial layer, and the first and second stress-generating epitaxial regions impart a stress on the channel region.

4. 发明申请

US20060283380A1 Semiconductor device and method of manufacturing the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US20060283380A1
公开(公告)日：2006-12-21
申请号：US11398118
申请日：2006-04-05
申请人： Sun-Ghil Lee , Young-Pil Kim , Yu-Gyun Shin , Jong-Wook Lee , Young-Eun Lee
发明人： Sun-Ghil Lee , Young-Pil Kim , Yu-Gyun Shin , Jong-Wook Lee , Young-Eun Lee
IPC分类号： C30B23/00 , C30B25/00 , C30B28/12 , C30B28/14
CPC分类号： C30B29/06 , C30B15/00
摘要： A semiconductor device formed on a strained silicon layer and a method of manufacturing such a semiconductor device are disclosed. In accordance with this invention, a first silicon germanium layer is formed on a single crystalline silicon substrate; a second silicon germanium layer is formed on the first silicon germanium layer, the second silicon germanium layer having a concentration of germanium in a range of about 1 percent by weight to about 15 percent by weight based on the total weight of the second silicon germanium layer; a strained silicon layer is formed on the second silicon germanium layer; an isolation layer is formed at a first portion of the strained silicon layer; a gate structure is formed on the strained silicon layer; and, source/drain regions are formed at second portions of the strained silicon layer adjacent to the gate structure to form a transistor.
摘要翻译：公开了一种形成在应变硅层上的半导体器件及其制造方法。根据本发明，在单晶硅衬底上形成第一硅锗层; 第二硅锗层形成在第一硅锗层上，第二硅锗层的锗浓度在约1重量％至约15重量％的范围内，基于第二硅锗层的总重量 ; 在第二硅锗层上形成应变硅层; 在应变硅层的第一部分处形成隔离层; 在应变硅层上形成栅极结构; 并且源极/漏极区域形成在与栅极结构相邻的应变硅层的第二部分处以形成晶体管。

5. 发明申请

US20060079056A1 Semiconductor structures having a strained silicon layer on a silicon-germanium layer and related fabrication methods 审中-公开
标题翻译：在硅锗层上具有应变硅层的半导体结构和相关的制造方法
公开(公告)号：US20060079056A1
公开(公告)日：2006-04-13
申请号：US11247412
申请日：2005-10-11
申请人： Young-Pil Kim , Sun-Ghil Lee , Yu-Gyun Shin , Jong-Wook Lee , In-Soo Jung
发明人： Young-Pil Kim , Sun-Ghil Lee , Yu-Gyun Shin , Jong-Wook Lee , In-Soo Jung
IPC分类号： H01L21/336
CPC分类号： H01L29/1054 , H01L21/02381 , H01L21/0245 , H01L21/0251 , H01L21/02532 , H01L21/02579 , H01L21/02639 , H01L29/78
摘要： A semiconductor structure including a SiGe layer and a method of fabricating the same are provided. The structure includes a silicon layer heavily doped with impurities. A SiGe layer is disposed on the silicon layer. A strained silicon layer is disposed on the SiGe layer. The impurities may be boron. The boron in the silicon layer may have a concentration of 1016 to 1020/cm3. Boron in the SiGe layer, diffused from the silicon substrate or directly doped, may suppress movement of misfit dislocation occurring in the SiGe layer toward the surface, thereby reducing a threading dislocation density near the surface of the strained silicon layer.
摘要翻译：提供了包括SiGe层的半导体结构及其制造方法。该结构包括重掺杂杂质的硅层。 SiGe层设置在硅层上。应变硅层设置在SiGe层上。杂质可以是硼。硅层中的硼可以具有10 16至10 20 / cm 3的浓度。在SiGe层中从硅衬底扩散或直接掺杂的硼可以抑制SiGe层中发生的失配位错的移动朝向表面，由此降低应变硅层表面附近的穿透位错密度。

6. 发明申请

US20090239348A1 SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US20090239348A1
公开(公告)日：2009-09-24
申请号：US12478345
申请日：2009-06-04
申请人： Sun-Ghil Lee , Young-Pil Kim , Yu-Gyun Shin , Jong-Wook Lee , Young-Eun Lee
发明人： Sun-Ghil Lee , Young-Pil Kim , Yu-Gyun Shin , Jong-Wook Lee , Young-Eun Lee
IPC分类号： H01L21/336
CPC分类号： C30B29/06 , C30B15/00
摘要： A semiconductor device formed on a strained silicon layer and a method of manufacturing such a semiconductor device are disclosed. In accordance with this invention, a first silicon germanium layer is formed on a single crystalline silicon substrate; a second silicon germanium layer is formed on the first silicon germanium layer, the second silicon germanium layer having a concentration of germanium in a range of about 1 percent by weight to about 15 percent by weight based on the total weight of the second silicon germanium layer; a strained silicon layer is formed on the second silicon germanium layer; an isolation layer is formed at a first portion of the strained silicon layer; a gate structure is formed on the strained silicon layer; and, source/drain regions are formed at second portions of the strained silicon layer adjacent to the gate structure to form a transistor.
摘要翻译：公开了一种形成在应变硅层上的半导体器件及其制造方法。根据本发明，在单晶硅衬底上形成第一硅锗层; 第二硅锗层形成在第一硅锗层上，第二硅锗层的锗浓度在约1重量％至约15重量％的范围内，基于第二硅锗层的总重量 ; 在第二硅锗层上形成应变硅层; 在应变硅层的第一部分处形成隔离层; 在应变硅层上形成栅极结构; 并且源极/漏极区域形成在与栅极结构相邻的应变硅层的第二部分处以形成晶体管。

7. 发明授权

US07323710B2 Fin field effect transistors having multi-layer fin patterns 失效
标题翻译：鳍场效应晶体管具有多层翅片图案
公开(公告)号：US07323710B2
公开(公告)日：2008-01-29
申请号：US10870743
申请日：2004-06-17
申请人： Young-Pil Kim , Sun-Ghil Lee , Si-Young Choi
发明人： Young-Pil Kim , Sun-Ghil Lee , Si-Young Choi
IPC分类号： H01L29/06 , H01L31/00
CPC分类号： H01L29/785 , H01L29/66795 , H01L29/78687
摘要： A fin field effect transistor has a fin pattern protruding from a semiconductor substrate. The fin pattern includes first semiconductor patterns and second semiconductor patterns which are stacked. The first and second semiconductor patterns have lattice widths that are greater than a lattice width of the substrate in at least one direction. In addition, the first and second semiconductor patterns may be alternately stacked to increase the height of the fin pattern, such that one of the first and second patterns can reduce stress from the other of the first and second patterns. The first and second semiconductor patterns may be formed of strained silicon and silicon-germanium, where the silicon-germanium patterns can reduce stress from the strained silicon patterns. Therefore, both the number of carriers and the mobility of carriers in the transistor channel may be increased, improving performance of the fin field effect transistor. Related methods are also discussed.
摘要翻译：鳍状场效应晶体管具有从半导体衬底突出的鳍状图案。鳍状图案包括堆叠的第一半导体图案和第二半导体图案。第一和第二半导体图案具有在至少一个方向上大于衬底的晶格宽度的晶格宽度。此外，第一和第二半导体图案可以交替堆叠以增加鳍片图案的高度，使得第一和第二图案中的一个可以减小来自第一和第二图案中的另一个的应力。第一和第二半导体图案可以由应变硅和硅 - 锗形成，其中硅 - 锗图案可以减小应变硅图案的应力。因此，可以增加晶体管沟道中的载流子数和载流子的迁移率，从而提高鳍式场效应晶体管的性能。还讨论了相关方法。

8. 发明申请

US20050184316A1 Fin field effect transistors having multi-layer fin patterns and methods of forming the same 失效
标题翻译：具有多层翅片图案的鳍式场效应晶体管及其形成方法
公开(公告)号：US20050184316A1
公开(公告)日：2005-08-25
申请号：US10870743
申请日：2004-06-17
申请人： Young-Pil Kim , Sun-Ghil Lee , Si-Young Choi
发明人： Young-Pil Kim , Sun-Ghil Lee , Si-Young Choi
IPC分类号： H01L21/336 , H01L29/745 , H01L29/76 , H01L29/78 , H01L29/786
CPC分类号： H01L29/785 , H01L29/66795 , H01L29/78687
摘要： A fin field effect transistor has a fin pattern protruding from a semiconductor substrate. The fin pattern includes first semiconductor patterns and second semiconductor patterns which are stacked. The first and second semiconductor patterns have lattice widths that are greater than a lattice width of the substrate in at least one direction. In addition, the first and second semiconductor patterns may be alternately stacked to increase the height of the fin pattern, such that one of the first and second patterns can reduce stress from the other of the first and second patterns. The first and second semiconductor patterns may be formed of strained silicon and silicon-germanium, where the silicon-germanium patterns can reduce stress from the strained silicon patterns. Therefore, both the number of carriers and the mobility of carriers in the transistor channel may be increased, improving performance of the fin field effect transistor. Related methods are also discussed.
摘要翻译：鳍状场效应晶体管具有从半导体衬底突出的鳍状图案。鳍状图案包括堆叠的第一半导体图案和第二半导体图案。第一和第二半导体图案具有在至少一个方向上大于衬底的晶格宽度的晶格宽度。此外，第一和第二半导体图案可以交替堆叠以增加鳍片图案的高度，使得第一和第二图案中的一个可以减小来自第一和第二图案中的另一个的应力。第一和第二半导体图案可以由应变硅和硅 - 锗形成，其中硅 - 锗图案可以减小应变硅图案的应力。因此，可以增加晶体管沟道中的载流子数和载流子的迁移率，从而提高鳍式场效应晶体管的性能。还讨论了相关方法。

9. 发明授权

US08877583B2 Method of manufacturing a semiconductor device 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US08877583B2
公开(公告)日：2014-11-04
申请号：US13728622
申请日：2012-12-27
申请人： Jin-Bum Kim , Young-Pil Kim , Kwan-Heum Lee , Sun-Ghil Lee
发明人： Jin-Bum Kim , Young-Pil Kim , Kwan-Heum Lee , Sun-Ghil Lee
IPC分类号： H01L21/8242 , H01L27/108 , H01L21/285 , H01L21/768 , H01L49/02
CPC分类号： H01L21/285 , H01L21/76843 , H01L21/76849 , H01L21/76889 , H01L27/10855 , H01L28/91
摘要： In a method of forming an ohmic layer of a DRAM device, the metal silicide layer between the storage node contact plug and the lower electrode of a capacitor is formed as the ohmic layer by a first heat treatment under a first temperature and an instantaneous second heat treatment under a second temperature higher than the first temperature. Thus, the metal silicide layer has a thermo-stable crystal structure and little or no agglomeration occurs on the metal silicide layer in the high temperature process. Accordingly, the sheet resistance of the ohmic layer may not increase in spite of the subsequent high temperature process.
摘要翻译：在形成DRAM器件的欧姆层的方法中，通过在第一温度和瞬时第二次加热下的第一次热处理将存储节点接触插塞和电容器的下部电极之间的金属硅化物层形成为欧姆层在比第一温度高的第二温度下进行处理。因此，金属硅化物层具有热稳定的晶体结构，并且在高温工艺中在金属硅化物层上几乎或不发生聚集。因此，尽管随后的高温处理，欧姆层的薄层电阻也可能不增加。

10. 发明授权

US07557388B2 MOSFET formed on a strained silicon layer 有权
标题翻译：形成在应变硅层上的MOSFET
公开(公告)号：US07557388B2
公开(公告)日：2009-07-07
申请号：US11398118
申请日：2006-04-05
申请人： Sun-Ghil Lee , Young-Pil Kim , Yu-Gyun Shin , Jong-Wook Lee , Young-Eun Lee
发明人： Sun-Ghil Lee , Young-Pil Kim , Yu-Gyun Shin , Jong-Wook Lee , Young-Eun Lee
IPC分类号： H01L31/00 , H01L35/26 , H01L31/117
CPC分类号： C30B29/06 , C30B15/00
摘要： A semiconductor device formed on a strained silicon layer and a method of manufacturing such a semiconductor device are disclosed. In accordance with this invention, a first silicon germanium layer is formed on a single crystalline silicon substrate; a second silicon germanium layer is formed on the first silicon germanium layer, the second silicon germanium layer having a concentration of germanium in a range of about 1 percent by weight to about 15 percent by weight based on the total weight of the second silicon germanium layer; a strained silicon layer is formed on the second silicon germanium layer; an isolation layer is formed at a first portion of the strained silicon layer; a gate structure is formed on the strained silicon layer; and, source/drain regions are formed at second portions of the strained silicon layer adjacent to the gate structure to form a transistor.
摘要翻译：公开了一种形成在应变硅层上的半导体器件及其制造方法。根据本发明，在单晶硅衬底上形成第一硅锗层; 第二硅锗层形成在第一硅锗层上，第二硅锗层的锗浓度在约1重量％至约15重量％的范围内，基于第二硅锗层的总重量 ; 在第二硅锗层上形成应变硅层; 在应变硅层的第一部分处形成隔离层; 在应变硅层上形成栅极结构; 并且源极/漏极区域形成在与栅极结构相邻的应变硅层的第二部分处以形成晶体管。

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