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1. 发明授权

US06787864B2 Mosfets incorporating nickel germanosilicided gate and methods for their formation 有权
公开(公告)号：US06787864B2
公开(公告)日：2004-09-07
申请号：US10335492
申请日：2002-12-31
申请人： Eric N. Paton , Qi Xiang , Paul R. Besser , Ming-Ren Lin , Minh V. Ngo , Haihong Wang
发明人： Eric N. Paton , Qi Xiang , Paul R. Besser , Ming-Ren Lin , Minh V. Ngo , Haihong Wang
IPC分类号： H01L2972
CPC分类号： H01L29/4933 , H01L21/28052 , H01L29/1054 , H01L29/4908 , H01L29/66477 , H01L29/665 , H01L29/66795 , H01L2029/7858
摘要： A MOSFET gate or a MOSFET source or drain region comprises silicon germanium or polycrystalline silicon germanium. Silicidation with nickel is performed to form a nickel germanosilicide that preferably comprises the monosilicide phase of nickel silicide. The inclusion of germanium in the silicide provides a wider temperature range within which the monosilicide phase may be formed, while essentially preserving the superior sheet resistance exhibited by nickel monosilicide. As a result, the nickel germanosilicide is capable of withstanding greater temperatures during subsequent processing than nickel monosilicide, yet provides approximately the same sheet resistance and other beneficial properties as nickel monosilicide.

2. 发明授权

US06858503B1 Depletion to avoid cross contamination 失效
标题翻译：消耗以避免交叉污染
公开(公告)号：US06858503B1
公开(公告)日：2005-02-22
申请号：US10358484
申请日：2003-02-05
申请人： Minh V. Ngo , Ming-Ren Lin , Paul R. Besser , Qi Xiang , Eric N. Paton , Jung-Suk Goo
发明人： Minh V. Ngo , Ming-Ren Lin , Paul R. Besser , Qi Xiang , Eric N. Paton , Jung-Suk Goo
IPC分类号： H01L21/306 , H01L29/10 , H01L21/336
CPC分类号： H01L21/02046 , H01L29/1054
摘要： A fabrication system utilizes a protocol for removing germanium from a top surface of a wafer. An exposure to a gas, such as a gas containing the hydrochloric acid can remove germanium from the top surface. The protocol can allow shared equipment to be used in both Flash product fabrication lines and strained silicon (SMOS) fabrication lines. The protocol allows better silicidation in SMOS devices.
摘要翻译：制造系统利用从晶片顶表面去除锗的方案。暴露于气体，如含有盐酸的气体，可以从上表面除去锗。该协议可以允许在Flash产品制造线和应变硅（SMOS）生产线中使用共享设备。该协议允许在SMOS器件中更好的硅化。

3. 发明授权

US06924182B1 Strained silicon MOSFET having reduced leakage and method of its formation 有权
标题翻译：应变硅MOSFET具有减少的泄漏和其形成方法
公开(公告)号：US06924182B1
公开(公告)日：2005-08-02
申请号：US10642375
申请日：2003-08-15
申请人： Qi Xiang , Ming Ren Lin , Minh V. Ngo , Eric N. Paton , Haihong Wang
发明人： Qi Xiang , Ming Ren Lin , Minh V. Ngo , Eric N. Paton , Haihong Wang
IPC分类号： H01L21/762 , H01L21/8238 , H01L21/8234 , H01L21/76
CPC分类号： H01L21/823878 , H01L21/76237 , H01L21/823807
摘要： The formation of shallow trench isolations in a strained silicon MOSFET includes performing ion implantation in the strained silicon layer in the regions to be etched to form the trenches of the shallow trench isolations. The dosage of the implanted ions and the energy of implantation are chosen so as to damage the crystal lattice of the strained silicon throughout the thickness of the strained silicon layer in the shallow trench isolation regions to such a degree that the etch rate of the strained silicon in those regions is increased to approximately the same as or greater than the etch rate of the underlying undamaged silicon germanium. Subsequent etching yields trenches with significantly reduced or eliminated undercutting of the silicon germanium relative to the strained silicon. This in turn substantially prevents the formation of fully depleted silicon on insulator regions under the ends of the gate, thus improving the MOSFET leakage current.
摘要翻译：应变硅MOSFET中的浅沟槽隔离的形成包括在被蚀刻的区域中的应变硅层中执行离子注入以形成浅沟槽隔离的沟槽。选择注入离子的剂量和注入能量，以便在浅沟槽隔离区域中的应变硅层的整个厚度上损坏应变硅的晶格，使得应变硅的蚀刻速率在这些区域中增加到大致等于或大于底层未损坏的硅锗的蚀刻速率。随后的蚀刻产生相对于应变硅显着减少或消除硅锗底切的沟槽。这又大大防止了在栅极端部的绝缘体区域上形成完全耗尽的硅，从而改善MOSFET漏电流。

4. 发明授权

US06730576B1 Method of forming a thick strained silicon layer and semiconductor structures incorporating a thick strained silicon layer 有权
标题翻译：形成厚应变硅层的方法和掺入厚应变硅层的半导体结构
公开(公告)号：US06730576B1
公开(公告)日：2004-05-04
申请号：US10335447
申请日：2002-12-31
申请人： Haihong Wang , Paul R. Besser , Jung-Suk Goo , Minh V. Ngo , Eric N. Paton , Qi Xiang
发明人： Haihong Wang , Paul R. Besser , Jung-Suk Goo , Minh V. Ngo , Eric N. Paton , Qi Xiang
IPC分类号： H01L21762
CPC分类号： H01L29/7833 , H01L21/02381 , H01L21/0245 , H01L21/0251 , H01L21/02532 , H01L21/0262 , H01L21/02639 , H01L21/76224 , H01L29/1054 , H01L29/665 , H01L29/6656 , H01L29/6659
摘要： A strained silicon layer is grown on a layer of silicon germanium and a layer of silicon germanium is grown on the strained silicon in a single continuous in situ deposition process with the strained silicon. Shallow trench isolations are formed in the lower layer of silicon germanium prior to formation of the strained silicon layer. The two silicon germanium layers effectively provide dual substrates at both surfaces of the strained silicon layer that serve to maintain the tensile strain of the strained silicon layer and resist the formation of misfit dislocations that might otherwise result from temperature changes during processing. Consequently the critical thickness of strained silicon that can be grown without significant misfit dislocations during later processing is effectively doubled for a given germanium content of the silicon germanium layers. The formation of shallow trench isolations prior to formation of the strained silicon layer avoids subjecting the strained silicon layer to extreme thermal stresses and further reduces the formation of misfit dislocations.
摘要翻译：应变硅层在硅锗层上生长，并且在应变硅上生长硅锗层，并在应变硅中进行单次连续原位沉积工艺。在形成应变硅层之前，在硅锗的下层形成浅沟槽隔离。两个硅锗层有效地在应变硅层的两个表面上提供双重衬底，其用于维持应变硅层的拉伸应变，并抵抗由加工过程中的温度变化引起的失配位错的形成。因此，对于硅锗层的给定锗含量，可以在后续处理期间可以生长而不显着失配位错的应变硅的临界厚度被有效地加倍。在形成应变硅层之前形成浅沟槽隔离避免使应变硅层受到极端的热应力，并进一步减少失配位错的形成。

5. 发明授权

US07713834B2 Method of forming isolation regions for integrated circuits 有权
标题翻译：形成集成电路隔离区的方法
公开(公告)号：US07713834B2
公开(公告)日：2010-05-11
申请号：US12205361
申请日：2008-09-05
申请人： Haihong Wang , Minh-Van Ngo , Qi Xiang , Paul R. Besser , Eric N. Paton , Ming-Ren Lin
发明人： Haihong Wang , Minh-Van Ngo , Qi Xiang , Paul R. Besser , Eric N. Paton , Ming-Ren Lin
IPC分类号： H01L21/76
CPC分类号： H01L21/76224 , H01L21/823481 , H01L29/1054
摘要： A method of manufacturing an integrated circuit (IC) utilizes a shallow trench isolation (STI) technique. The shallow trench isolation technique is used in strained silicon (SMOS) process. The liner for the trench is formed from a semiconductor or metal layer which is deposited in a low temperature process which reduces germanium outgassing. The low temperature process can be a ALD process.
摘要翻译：集成电路（IC）的制造方法利用浅沟槽隔离（STI）技术。浅沟槽隔离技术用于应变硅（SMOS）工艺。用于沟槽的衬垫由半导体或金属层形成，该半导体或金属层在低温过程中沉积，这降低了锗除气。低温过程可以是ALD过程。

6. 发明申请

US20090047770A1 METHOD OF FORMING ISOLATION REGIONS FOR INTEGRATED CIRCUITS 有权
标题翻译：形成集成电路隔离区的方法
公开(公告)号：US20090047770A1
公开(公告)日：2009-02-19
申请号：US12205361
申请日：2008-09-05
申请人： Haihong Wang , Minh-Van Ngo , Qi Xiang , Paul R. Besser , Eric N. Paton , Ming-Ren Lin
发明人： Haihong Wang , Minh-Van Ngo , Qi Xiang , Paul R. Besser , Eric N. Paton , Ming-Ren Lin
IPC分类号： H01L21/76
CPC分类号： H01L21/76224 , H01L21/823481 , H01L29/1054
摘要： A method of manufacturing an integrated circuit (IC) utilizes a shallow trench isolation (STI) technique. The shallow trench isolation technique is used in strained silicon (SMOS) process. The liner for the trench is formed from a semiconductor or metal layer which is deposited in a low temperature process which reduces germanium outgassing. The low temperature process can be a ALD process.
摘要翻译：集成电路（IC）的制造方法利用浅沟槽隔离（STI）技术。浅沟槽隔离技术用于应变硅（SMOS）工艺。用于沟槽的衬垫由半导体或金属层形成，该半导体或金属层在低温过程中沉积，这降低了锗除气。低温过程可以是ALD过程。

7. 发明授权

US07422961B2 Method of forming isolation regions for integrated circuits 有权
标题翻译：形成集成电路隔离区的方法
公开(公告)号：US07422961B2
公开(公告)日：2008-09-09
申请号：US10389456
申请日：2003-03-14
申请人： Haihong Wang , Minh-Van Ngo , Qi Xiang , Paul R. Besser , Eric N. Paton , Ming-Ren Lin
发明人： Haihong Wang , Minh-Van Ngo , Qi Xiang , Paul R. Besser , Eric N. Paton , Ming-Ren Lin
IPC分类号： H01L21/762
CPC分类号： H01L21/76224 , H01L21/823481 , H01L29/1054
摘要： A method of manufacturing an integrated circuit (IC) utilizes a shallow trench isolation (STI) technique. The shallow trench isolation technique is used in strained silicon (SMOS) process. The liner for the trench is formed from a semiconductor or metal layer which is deposited in a low temperature process which reduces germanium outgassing. The low temperature process can be a CVD process.
摘要翻译：集成电路（IC）的制造方法利用浅沟槽隔离（STI）技术。浅沟槽隔离技术用于应变硅（SMOS）工艺。用于沟槽的衬垫由半导体或金属层形成，该半导体或金属层在低温过程中沉积，这降低了锗除气。低温工艺可以是CVD工艺。

8. 发明授权

US06878592B1 Selective epitaxy to improve silicidation 失效
标题翻译：选择性外延以改善硅化
公开(公告)号：US06878592B1
公开(公告)日：2005-04-12
申请号：US10341772
申请日：2003-01-14
申请人： Paul R. Besser , Minh V. Ngo , Qi Xiang , Eric N. Paton
发明人： Paul R. Besser , Minh V. Ngo , Qi Xiang , Eric N. Paton
IPC分类号： H01L21/20 , H01L21/285 , H01L21/336 , H01L29/51 , H01L21/3205 , H01L21/44
CPC分类号： H01L21/28052 , H01L21/02381 , H01L21/0245 , H01L21/02532 , H01L21/0262 , H01L21/02639 , H01L21/28518 , H01L21/28525 , H01L21/28562 , H01L29/51 , H01L29/518 , H01L29/665 , H01L29/66636 , H01L29/7845
摘要： A transistor architecture utilizes a raised source and drain region to reduce the adverse affects of germanium on silicide regions. Epitaxial growth can form a silicide region above the source and drain. The protocol can utilize any number of silicidation processes. The protocol allows better silicidation in SMOS devices.
摘要翻译：晶体管架构利用升高的源极和漏极区域来减少锗对硅化物区域的不利影响。外延生长可以在源极和漏极之上形成硅化物区域。该协议可以利用任何数量的硅化工艺。该协议允许在SMOS器件中更好的硅化。

9. 发明授权

US06797614B1 Nickel alloy for SMOS process silicidation 有权
标题翻译：用于SMOS工艺硅化的镍合金
公开(公告)号：US06797614B1
公开(公告)日：2004-09-28
申请号：US10440847
申请日：2003-05-19
申请人： Eric N. Paton , Paul R. Besser , Minh V. Ngo , Qi Xiang
发明人： Eric N. Paton , Paul R. Besser , Minh V. Ngo , Qi Xiang
IPC分类号： H01L2144
CPC分类号： H01L29/1054 , H01L21/28518 , H01L29/665
摘要： A process of siliciding uses alloys to reduce the adverse affects of germanium on silicide regions. The alloy can include nickel and at least one of vanadium, tantalum, and tungsten. The process can utilize one or two annealing steps. The process allows better silicidation in SMOS devices. The silicided regions can be provided above a silicon/germanium substrate.
摘要翻译：硅化过程使用合金来减少锗对硅化物区域的不利影响。该合金可以包括镍和钒，钽和钨中的至少一种。该方法可以利用一个或两个退火步骤。该过程允许在SMOS器件中更好的硅化。硅化物区域可以设置在硅/锗衬底之上。

10. 发明授权

US06562718B1 Process for forming fully silicided gates 有权
标题翻译：完全硅化物门的制作工艺
公开(公告)号：US06562718B1
公开(公告)日：2003-05-13
申请号：US09729700
申请日：2000-12-06
申请人： Qi Xiang , Ercan Adem , Jacques J. Bertrand , Paul R. Besser , Matthew S. Buynoski , John C. Foster , Paul L. King , George J. Kluth , Minh V. Ngo , Eric N. Paton , Christy Mei-Chu Woo
发明人： Qi Xiang , Ercan Adem , Jacques J. Bertrand , Paul R. Besser , Matthew S. Buynoski , John C. Foster , Paul L. King , George J. Kluth , Minh V. Ngo , Eric N. Paton , Christy Mei-Chu Woo
IPC分类号： H01L2144
CPC分类号： H01L29/66507 , H01L21/28097
摘要： A method of forming a fully silicidized gate of a semiconductor device includes forming silicide in active regions and a portion of a gate. A shield layer is blanket deposited over the device. The top surface of the gate electrode is then exposed. A refractory metal layer is deposited and annealing is performed to cause the metal to react with the gate and fully silicidize the gate, with the shield layer protecting the active regions of the device from further silicidization to thereby prevent spiking and current leakage in the active regions.
摘要翻译：形成半导体器件的完全硅化栅极的方法包括在有源区和门的一部分中形成硅化物。屏蔽层被覆盖在该器件上。然后露出栅电极的顶表面。沉积难熔金属层并进行退火以使金属与栅极反应并使栅极完全硅化，屏蔽层保护器件的有源区不受另外的硅化，从而防止有源区中的峰值和电流泄漏。

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