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1. 发明申请

US20110271141A1 Non-Volatile Memory Based Reliability and Availability Mechanisms for a Computing Device 有权
标题翻译：用于计算设备的非易失性存储器的可靠性和可用性机制
公开(公告)号：US20110271141A1
公开(公告)日：2011-11-03
申请号：US12771293
申请日：2010-04-30
申请人： Eren Kursun , Philip G. Emma , Stephen M. Gates
发明人： Eren Kursun , Philip G. Emma , Stephen M. Gates
IPC分类号： G06F11/16 , G06F11/00
CPC分类号： G06F11/008 , G06F11/0724 , G06F11/0787 , G06F11/0793
摘要： Mechanisms are provided for use with a microprocessor chip, for storing selected reliability information in an on-chip non-volatile storage device. An on-chip reliability controller coupled to one or more on-chip resources of the microprocessor chip, collects raw reliability information from the one or more on-chip resources of the microprocessor chip. The on-chip reliability controller analyzes the raw reliability information to identify selected reliability information for the one or more resources of the microprocessor chip. The on-chip reliability controller stores the selected reliability information in the on-chip non-volatile storage device. The on-chip non-volatile storage device stores the selected reliability information even in the event of an overall failure of the microprocessor chip in which the microprocessor chip loses power. The on-chip non-volatile storage device has an interface through which the selected reliability information is accessible by an off-chip device even in the event of an overall failure of the microprocessor chip.
摘要翻译：提供了与微处理器芯片一起使用的机制，用于将选定的可靠性信息存储在片上非易失性存储设备中。耦合到微处理器芯片的一个或多个片上资源的片上可靠性控制器从微处理器芯片的一个或多个片上资源收集原始可靠性信息。片上可靠性控制器分析原始可靠性信息，以识别微处理器芯片的一个或多个资源的选定可靠性信息。片上可靠性控制器将所选择的可靠性信息存储在片上非易失性存储装置中。即使在微处理器芯片失去电力的微处理器芯片的整体故障的情况下，片上非易失性存储设备也存储所选择的可靠性信息。片上非易失性存储设备具有接口，即使在微处理器芯片的整体故障的情况下，所选择的可靠性信息也可通过片外设备访问。

2. 发明授权

US08386859B2 On-chip non-volatile storage of a test-time profile for efficiency and performance control 有权
标题翻译：用于效率和性能控制的片上非易失性存储测试时间配置文件
公开(公告)号：US08386859B2
公开(公告)日：2013-02-26
申请号：US12771387
申请日：2010-04-30
申请人： Eren Kursun , Philip G. Emma , Stephen M. Gates
发明人： Eren Kursun , Philip G. Emma , Stephen M. Gates
IPC分类号： G11C29/00 , G11C7/00 , G01R31/28 , G01R27/28 , G01R31/00 , G01R31/14 , G06F11/00
CPC分类号： G06F11/3062 , G06F11/24 , G06F11/3024 , G06F11/3089
摘要： Mechanisms for controlling an operation of one or more cores on an integrated circuit chip are provided. The mechanisms retrieve, from an on-chip non-volatile memory of the integrated circuit chip, baseline chip characteristics data representing operational characteristics of the one or more cores prior to the integrated circuit chip being operational in the data processing system. Current operational characteristics data of the one or more cores are compared with the baseline chip characteristics data. Deviations of the current operational characteristics data from the baseline chip characteristics data are determined and used to determine modifications to an operation of the one or more cores. Control signals are sent to one or more on-chip management units based on the determined modifications to cause the operation of the one or more cores to be modified.
摘要翻译：提供了用于控制集成电路芯片上的一个或多个芯的操作的机构。该机制从集成电路芯片的片上非易失性存储器中检索表示集成电路芯片在数据处理系统中操作之前的一个或多个核的操作特性的基准芯片特性数据。将一个或多个核的当前操作特征数据与基线芯片特性数据进行比较。确定当前操作特性数据与基线芯片特性数据的偏差并用于确定对一个或多个芯的操作的修改。基于所确定的修改，控制信号被发送到一个或多个片上管理单元，以使得修改一个或多个核的操作。

3. 发明授权

US08276018B2 Non-volatile memory based reliability and availability mechanisms for a computing device 有权
标题翻译：用于计算设备的基于非易失性存储器的可靠性和可用性机制
公开(公告)号：US08276018B2
公开(公告)日：2012-09-25
申请号：US12771293
申请日：2010-04-30
申请人： Eren Kursun , Philip G. Emma , Stephen M. Gates
发明人： Eren Kursun , Philip G. Emma , Stephen M. Gates
IPC分类号： G06F11/00
CPC分类号： G06F11/008 , G06F11/0724 , G06F11/0787 , G06F11/0793
摘要： Mechanisms are provided for use with a microprocessor chip, for storing selected reliability information in an on-chip non-volatile storage device. An on-chip reliability controller coupled to one or more on-chip resources of the microprocessor chip, collects raw reliability information from the one or more on-chip resources of the microprocessor chip. The on-chip reliability controller analyzes the raw reliability information to identify selected reliability information for the one or more resources of the microprocessor chip. The on-chip reliability controller stores the selected reliability information in the on-chip non-volatile storage device. The on-chip non-volatile storage device stores the selected reliability information even in the event of an overall failure of the microprocessor chip in which the microprocessor chip loses power. The on-chip non-volatile storage device has an interface through which the selected reliability information is accessible by an off-chip device even in the event of an overall failure of the microprocessor chip.
摘要翻译：提供了与微处理器芯片一起使用的机制，用于将选定的可靠性信息存储在片上非易失性存储设备中。耦合到微处理器芯片的一个或多个片上资源的片上可靠性控制器从微处理器芯片的一个或多个片上资源收集原始可靠性信息。片上可靠性控制器分析原始可靠性信息，以识别微处理器芯片的一个或多个资源的选定可靠性信息。片上可靠性控制器将所选择的可靠性信息存储在片上非易失性存储装置中。即使在微处理器芯片失去电力的微处理器芯片的整体故障的情况下，片上非易失性存储设备也存储所选择的可靠性信息。片上非易失性存储设备具有接口，即使在微处理器芯片的整体故障的情况下，所选择的可靠性信息也可通过片外设备访问。

4. 发明申请

US20110271161A1 On-Chip Non-Volatile Storage of a Test-Time Profile for Efficiency and Performance Control 有权
标题翻译：用于效率和性能控制的测试时间配置文件的片上非易失性存储
公开(公告)号：US20110271161A1
公开(公告)日：2011-11-03
申请号：US12771387
申请日：2010-04-30
申请人： Eren Kursun , Philip G. Emma , Stephen M. Gates
发明人： Eren Kursun , Philip G. Emma , Stephen M. Gates
IPC分类号： G06F11/07
CPC分类号： G06F11/3062 , G06F11/24 , G06F11/3024 , G06F11/3089
摘要： Mechanisms for controlling an operation of one or more cores on an integrated circuit chip are provided. The mechanisms retrieve, from an on-chip non-volatile memory of the integrated circuit chip, baseline chip characteristics data representing operational characteristics of the one or more cores prior to the integrated circuit chip being operational in the data processing system. Current operational characteristics data of the one or more cores are compared with the baseline chip characteristics data. Deviations of the current operational characteristics data from the baseline chip characteristics data are determined and used to determine modifications to an operation of the one or more cores. Control signals are sent to one or more on-chip management units based on the determined modifications to cause the operation of the one or more cores to be modified.
摘要翻译：提供了用于控制集成电路芯片上的一个或多个芯的操作的机构。该机制从集成电路芯片的片上非易失性存储器中检索表示集成电路芯片在数据处理系统中操作之前的一个或多个核的操作特性的基准芯片特性数据。将一个或多个核的当前操作特征数据与基线芯片特性数据进行比较。确定当前操作特性数据与基线芯片特性数据的偏差并用于确定对一个或多个芯的操作的修改。基于所确定的修改，控制信号被发送到一个或多个片上管理单元，以使得修改一个或多个核的操作。

5. 发明授权

US08624323B2 BEOL structures incorporating active devices and mechanical strength 有权
标题翻译：包含有源器件和机械强度的BEOL结构
公开(公告)号：US08624323B2
公开(公告)日：2014-01-07
申请号：US13149797
申请日：2011-05-31
申请人： Stephen M. Gates , Daniel C. Edelstein , Satyanarayana V. Nitta
发明人： Stephen M. Gates , Daniel C. Edelstein , Satyanarayana V. Nitta
IPC分类号： H01L29/76 , H01L29/94 , H01L23/34 , H01L23/48 , H01L29/40
CPC分类号： H01L23/481 , H01L21/02667 , H01L23/5223 , H01L23/5226 , H01L23/5227 , H01L23/5228 , H01L23/53238 , H01L24/80 , H01L25/18 , H01L25/50 , H01L27/016 , H01L27/0688 , H01L29/66984 , H01L29/861 , H01L29/872 , H01L2924/12032 , H01L2924/12042 , H01L2924/1305 , H01L2924/1306 , H01L2924/00
摘要： A monolithic integrated circuit and method includes a substrate, a plurality of semiconductor device layers monolithically integrated on the substrate, and a metal wiring layer with vias interconnecting the plurality of semiconductor device layers. The semiconductor device layers are devoid of bonding or joining interface with the substrate. A method of fabricating a monolithic integrated circuit using a single substrate, includes fabricating semiconductor devices on a substrate, fabricating at least one metal wiring layer on the semiconductor devices, forming at least one dielectric layer in integral contact with the at least one metal wiring layer, forming contact openings through the at least one dielectric layer to expose regions of the at least one metal wiring layer, integrally forming, from the substrate, a second semiconductor layer on the dielectric layer, and in contact with the at least one metal wiring layer through the contact openings, and forming a plurality of non-linear semiconductor devices in said second semiconductor layer.
摘要翻译：单片集成电路和方法包括基板，单片集成在基板上的多个半导体器件层以及具有互连多个半导体器件层的通孔的金属布线层。半导体器件层没有与衬底接合或结合界面。使用单个衬底制造单片集成电路的方法包括在衬底上制造半导体器件，在半导体器件上制造至少一个金属布线层，形成与至少一个金属布线层一体接触的至少一个电介质层形成通过所述至少一个电介质层的接触开口以暴露所述至少一个金属布线层的区域，从所述基板一体地形成所述电介质层上的第二半导体层，并与所述至少一个金属布线层通过所述接触开口，以及在所述第二半导体层中形成多个非线性半导体器件。

6. 发明申请

US20120329287A1 LOW k POROUS SiCOH DIELECTRIC AND INTEGRATION WITH POST FILM FORMATION TREATMENT 有权
标题翻译：低k多孔SiCOH电介质和后期成膜处理的整合
公开(公告)号：US20120329287A1
公开(公告)日：2012-12-27
申请号：US13603008
申请日：2012-09-04
申请人： Stephen M. Gates , Alfred Grill , Son Nguyen , Satyanarayana V. Nitta , Thomas M. Shaw
发明人： Stephen M. Gates , Alfred Grill , Son Nguyen , Satyanarayana V. Nitta , Thomas M. Shaw
IPC分类号： H01L21/312
CPC分类号： H01L23/5329 , C23C16/401 , C23C16/505 , C23C16/511 , C23C16/56 , H01J2237/336 , H01J2237/338 , H01J2237/3382 , H01L21/02126 , H01L21/02203 , H01L21/02205 , H01L21/02216 , H01L21/02274 , H01L21/0234 , H01L21/02345 , H01L21/02348 , H01L21/02351 , H01L21/31633 , H01L21/31695 , H01L21/76825 , H01L21/76826 , H01L21/76828 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： A porous SiCOH dielectric film in which the stress change caused by increased tetrahedral strain is minimized by post treatment in unsaturated Hydrocarbon ambient. The p-SiCOH dielectric film has more —(CHx) and less Si—O—H and Si—H bonding moieties. Moreover, a stable pSiOCH dielectric film is provided in which the amount of Si—OH (silanol) and Si—H groups at least within the pores has been reduced by about 90% or less by the post treatment. A p-SiCOH dielectric film is produced that is flexible since the pores include stabilized crosslinking —(CHx)— chains wherein x is 1, 2 or 3 therein. The dielectric film is produced utilizing an annealing step subsequent deposition that includes a gaseous ambient that includes at least one C—C double bond and/or at least one C—C triple bond.
摘要翻译：通过在不饱和烃环境中后处理，使四面体应变增加引起的应力变化最小化的多孔SiCOH介电膜。 p-SiCOH电介质膜具有更多的（（CH x））和更少的Si-O-H和Si-H键合部分。此外，提供稳定的pSiOCH电介质膜，其中至少在孔内的Si-OH（硅烷醇）和Si-H基团的量通过后处理减少约90％以下。由于气孔包括其中x为1,2或3的稳定的交联 - （CH x） - 链，因此制备柔性的p-SiCOH介电膜。介电膜是利用包括至少一个C-C双键和/或至少一个C-C三键的气态环境的退火步骤进行的。

7. 发明申请

US20120261793A1 ELECTRICAL FUSE AND METHOD OF MAKING THE SAME 有权
标题翻译：电保险丝及其制造方法
公开(公告)号：US20120261793A1
公开(公告)日：2012-10-18
申请号：US13085568
申请日：2011-04-13
申请人： Chih-Chao Yang , Stephen M. Gates , Baozhen Li , Daniel C. Edelstein
发明人： Chih-Chao Yang , Stephen M. Gates , Baozhen Li , Daniel C. Edelstein
IPC分类号： H01L23/525 , H01L21/768
CPC分类号： H01L23/5256 , H01L2924/0002 , H01L2924/00
摘要： An improved electrical-fuse (e-fuse) device including a dielectric layer having a first top surface, two conductive features embedded in the dielectric layer and a fuse element. Each conductive feature has a second top surface and a metal cap directly on the second top surface. Each metal cap has a third top surface that is above the first top surface of the dielectric layer. The fuse element is on the third top surface of each metal cap and on the first top surface of the dielectric layer. A method of forming the e-fuse device is also provided.
摘要翻译：一种改进的电熔丝（e-fuse）装置，包括具有第一顶表面的电介质层，嵌入介质层中的两个导电特征和熔丝元件。每个导电特征具有第二顶表面和直接在第二顶表面上的金属帽。每个金属盖具有在介电层的第一顶表面之上的第三顶表面。熔丝元件位于每个金属盖的第三顶表面上，并位于介质层的第一顶表面上。还提供了形成电熔丝装置的方法。

8. 发明授权

US07955968B2 Pseudo hybrid structure for low K interconnect integration 有权
标题翻译：用于低K互连集成的伪混合结构
公开(公告)号：US07955968B2
公开(公告)日：2011-06-07
申请号：US12399372
申请日：2009-03-06
申请人： Pak K. Leung , Terry G. Sparks , David V. Horak , Stephen M. Gates
发明人： Pak K. Leung , Terry G. Sparks , David V. Horak , Stephen M. Gates
IPC分类号： H01L21/4763
CPC分类号： H01L21/76828 , H01L21/76808 , H01L21/76814 , H01L21/76825 , H01L21/76835 , H01L2221/1036 , Y10T29/49224
摘要： A method and apparatus are described for fabricating an ultra low-k interconnect structure by depositing and curing a first via layer (43) of ultra low dielectric constant (ULK) material, depositing a second uncured trench layer (51) of the same ULK material, selectively etching a via opening (62) and trench opening (72) with a dual damascene etch process which uses a trench etch end point signal from the chemical differences between uncured trench layer (51) and the underlying cured via layer (43), and then curing the second trench layer (83) before forming an interconnect structure (91) by filling the trench opening (72) and via opening (62) with an interconnection material so that there is no additional interface or higher dielectric constant material left behind.
摘要翻译：描述了通过沉积和固化超低介电常数（ULK）材料的第一通孔层（43）来制造超低k互连结构的方法和装置，沉积相同ULK材料的第二未固化沟槽层（51）通过使用来自未固化沟槽层（51）和下面的固化通孔层（43）之间的化学差异的沟槽蚀刻终点信号的双镶嵌蚀刻工艺来选择性地蚀刻通孔开口（62）和沟槽开口（72）然后在通过用互连材料填充沟槽开口（72）和通孔开口（62）形成互连结构（91）之前固化第二沟槽层（83），使得不存在附加的界面或更高的介电常数材料留下。

9. 发明申请

US20090181178A1 SiCOH DIELECTRIC MATERIAL WITH IMPROVED TOUGHNESS AND IMPROVED Si-C BONDING, SEMICONDUCTOR DEVICE CONTAINING THE SAME, AND METHOD TO MAKE THE SAME 有权
标题翻译：具有改进的韧性和改进的Si-C键合的SiCOH电介质材料，含有它们的半导体器件及其制造方法
公开(公告)号：US20090181178A1
公开(公告)日：2009-07-16
申请号：US12355316
申请日：2009-01-16
申请人： Daniel C. Edelstein , Stephen M. Gates , Alfred Grill , Michael Lane , Qinghuang Lin , Robert D. Miller , Deborah A. Neumayer , Son Van Nguyen
发明人： Daniel C. Edelstein , Stephen M. Gates , Alfred Grill , Michael Lane , Qinghuang Lin , Robert D. Miller , Deborah A. Neumayer , Son Van Nguyen
IPC分类号： C23C16/22
CPC分类号： H01L31/103 , Y10T428/31663
摘要： A low-k dielectric material with increased cohesive strength for use in electronic structures including interconnect and sensing structures is provided that includes atoms of Si, C, O, and H in which a fraction of the C atoms are bonded as Si—CH3 functional groups, and another fraction of the C atoms are bonded as Si—R—Si, wherein R is phenyl, —[CH2]n— where n is greater than or equal to 1, HC═CH, C═CH2, C═C or a [S]n linkage, where n is a defined above.
摘要翻译：提供了一种用于包括互连和感测结构的电子结构中具有增强的内聚强度的低k电介质材料，其包括其中一部分C原子键合为Si-CH 3官能团的Si，C，O和H的原子，另一部分C原子键合为Si-R-Si，其中R为苯基， - [CH2] n-，其中n大于或等于1，HC-CH，C-CH2，CC或[ S] n连接，其中n是上面定义的。

10. 发明授权

US07521377B2 SiCOH film preparation using precursors with built-in porogen functionality 有权
标题翻译：使用具有内置致孔剂功能的前体的SiCOH膜制备
公开(公告)号：US07521377B2
公开(公告)日：2009-04-21
申请号：US11329560
申请日：2006-01-11
申请人： Stephen M. Gates , Alfred Grill , Robert D. Miller , Deborah A. Neumayer , Son Nguyen
发明人： Stephen M. Gates , Alfred Grill , Robert D. Miller , Deborah A. Neumayer , Son Nguyen
IPC分类号： H01L21/31 , H01L21/469
CPC分类号： H01L21/31695 , B05D1/60 , C23C16/30 , C23C16/56 , H01L21/02126 , H01L21/02203 , H01L21/02216 , H01L21/02274 , H01L21/02282 , H01L21/02337 , H01L21/02348 , H01L21/02351
摘要： A method of fabricating a dielectric material that has an ultra low dielectric constant (or ultra low k) using at least one organosilicon precursor is described. The organosilicon precursor employed in the present invention includes a molecule containing both an Si—O structure and a sacrificial organic group, as a leaving group. The use of an organosilicon precursor containing a molecular scale sacrificial leaving group enables control of the pore size at the nanometer scale, control of the compositional and structural uniformity and simplifies the manufacturing process. Moreover, fabrication of a dielectric film from a single precursor enables better control of the final porosity in the film and a narrower pore size distribution resulting in better mechanical properties at the same value of dielectric constant.
摘要翻译：描述了使用至少一种有机硅前体制造具有超低介电常数（或超低k）的介电材料的方法。本发明中使用的有机硅前体包括含有Si-O结构和牺牲有机基团的分子作为离去基团。使用含有分子尺度牺牲离去基团的有机硅前体使得能够控制纳米尺度的孔径，控制组成和结构均匀性并简化制造过程。此外，从单一前体制造电介质膜能够更好地控制膜中的最终孔隙率和较窄的孔径分布，导致在相同的介电常数值下更好的机械性能。

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