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1. 发明授权

US06192450B1 Destage of data for write cache 失效
标题翻译：写入缓存的数据流出
公开(公告)号：US06192450B1
公开(公告)日：2001-02-20
申请号：US09018175
申请日：1998-02-03
申请人： Ellen Marie Bauman , Robert Edward Galbraith , Mark A. Johnson
发明人： Ellen Marie Bauman , Robert Edward Galbraith , Mark A. Johnson
IPC分类号： G06F1200
CPC分类号： G06F12/0804 , G06F12/0866
摘要： Data in a write cache is coalesced together prior to each destage operation. This results in higher performance by destaging a large quantity of data from the cache with each destage operation. A root item of data is located, and then a working set of data is collected by identifying additional data in the cache that will be destaged to locations in the storage device adjacent to the root item of data. The root item of data may be identified by starting at the location of the least recently accessed data in the cache, and then selecting a root item of data at a lower storage device address than the least recently accessed data, or may be chosen from a larger than average group of data items that were stored together into the cache. To speed execution, data items are added to a working set by, where possible, scanning an queue of data items kept in access order to locate data items at adjacent storage locations.
摘要翻译：写入高速缓存中的数据在每次卸载操作之前合并在一起。这将导致通过每次卸载操作从高速缓存中降级大量数据而导致更高的性能。找到一个根数据项，然后通过识别高速缓存中的附加数据来收集一组工作数据，这些附加数据将被转发到与数据根数据相邻的存储设备中的位置。可以通过从高速缓存中最近访问的数据的位置开始，然后在低于最近访问的数据的较低存储设备地址处选择数据的根项来识别数据的根项，或者可以从大于平均存储在缓存中的一组数据项。为了加快执行速度，通过在可能的情况下扫描以访问顺序保持的数据项队列来将数据项添加到工作集中，以在相邻存储位置定位数据项。

2. 发明授权

US6119209A Backup directory for a write cache 失效
标题翻译：写缓存的备份目录
公开(公告)号：US6119209A
公开(公告)日：2000-09-12
申请号：US17830
申请日：1998-02-03
申请人： Ellen Marie Bauman , Robert Edward Galbraith , Mark A. Johnson
发明人： Ellen Marie Bauman , Robert Edward Galbraith , Mark A. Johnson
IPC分类号： G06F13/00
CPC分类号： G06F12/0895
摘要： For error recovery purposes, a backup copy of only a portion of the cache directory is maintained in non-volatile storage. Because only a portion of the cache directory is backup copied, a savings in storage space is realized. The partial copy includes an indication of the storage locations on a storage device for which data is in the cache, and an indication of the state of the data, i.e., whether the data is in process of being read from the cache by the processor, is in process of being written to the cache by the processor, is in the process of being destaged from the cache to the storage device, or none of the above. Only certain changes to the state of the cache cause a backup copy of a portion of the cache directory to be saved; other changes to the state of the cache do not cause the portion of the cache directory to be saved in non-volatile storage. This saves processing time by limiting the number of times that data is copied to the cache.
摘要翻译：出于错误恢复的目的，仅在缓存目录的一部分的备份副本被维护在非易失性存储器中。由于仅缓存目录的一部分被备份复制，所以实现了存储空间的节省。该部分副本包括在高速缓存中的数据的存储设备上的存储位置的指示，以及数据的状态的指示，即数据是否正在被处理器从高速缓存读取，正在由处理器写入缓存的过程中，正在从高速缓存到存储设备的过程中，或者没有上述任何一个。仅对缓存状态进行某些更改会导致缓存目录的一部分的备份副本被保存; 对缓存状态的其他更改不会导致高速缓存目录的部分保存在非易失性存储中。这通过限制数据被复制到缓存的次数来节省处理时间。

3. 发明授权

US06643724B2 Method and apparatus for interrupt routing of PCI adapters via device address mapping 失效
标题翻译：通过设备地址映射中断PCI适配器路由的方法和装置
公开(公告)号：US06643724B2
公开(公告)日：2003-11-04
申请号：US09748980
申请日：2000-12-27
申请人： Ellen Marie Bauman , David Lee Dosch , Daniel Paul Wetzel
发明人： Ellen Marie Bauman , David Lee Dosch , Daniel Paul Wetzel
IPC分类号： G06F1324
CPC分类号： G06F13/24
摘要： A method and apparatus are provided for interrupt routing of peripheral component interconnect (PCI) adapters via device address mapping. A first processor complex includes a multifunction PCI to PCI bridge interface chip. A local PCI bus is coupled between a second processor complex and the multifunction PCI to PCI bridge interface chip. A host PCI bus is coupled between the multifunction PCI to PCI bridge interface chip and a second multifunction PCI to PCI bridge chip. A plurality of local area network (LAN) adapters are coupled to the second multifunction PCI to PCI bridge chip. The multifunction PCI to PCI bridge interface chip of the first processor complex includes interrupt mapping logic for mapping interrupts from the LAN adapters to PCI interrupts on the local PCI bus to the second processor complex. The multifunction PCI to PCI bridge interface chip of the first processor complex includes translation logic for translating a configuration cycle on the local PCI bus from the second processor complex to another configuration cycle on the host PCI bus and for translating a configuration cycle on the host PCI bus from the LAN adapters to another configuration cycle on the local PCI bus to the second processor complex. The multifunction PCI to PCI bridge interface chip of the first processor complex includes a bus number register for specifying a PCI bus number and a device translation register for specifies a translation value for each function of the multifunction PCI to PCI bridge interface chip for determining a device number of each of said plurality of local area network (LAN) adapters.
摘要翻译：提供了一种用于通过设备地址映射来中断路由外围组件互连（PCI）适配器的方法和装置。第一个处理器组合包括一个多功能PCI到PCI桥接口芯片。本地PCI总线耦合在第二处理器复合体和多功能PCI至PCI桥接口芯片之间。主机PCI总线耦合在多功能PCI至PCI桥接口芯片和第二个多功能PCI至PCI桥接芯片之间。多个局域网（LAN）适配器耦合到第二多功能PCI至PCI桥芯片。第一处理器复合体的多功能PCI至PCI桥接器芯片包括用于将局域网适配器的中断映射到本地PCI总线上的PCI中断到第二处理器复合体的中断映射逻辑。第一处理器复合体的多功能PCI至PCI桥接口芯片包括翻译逻辑，用于将本地PCI总线上的配置周期从第二处理器复合转换到主机PCI总线上的另一个配置周期，并用于翻译主机PCI上的配置周期总线从LAN适配器到本地PCI总线上的另一个配置周期到第二个处理器组合。第一处理器复合体的多功能PCI至PCI桥接口芯片包括用于指定PCI总线号的总线号寄存器和用于指定用于确定设备的多功能PCI至PCI桥接器芯片的每个功能的转换值的设备转换寄存器所述多个局域网（LAN）适配器中的每一个的数量。

4. 发明授权

US08028141B2 Partitioning of a multiple logic-unit-number SCSI target 失效
标题翻译：分配多个逻辑单元号SCSI目标
公开(公告)号：US08028141B2
公开(公告)日：2011-09-27
申请号：US12132048
申请日：2008-06-03
申请人： Brian Eric Bakke , Ellen Marie Bauman , Timothy Jerry Schimke , Lee Anton Sendelbach
发明人： Brian Eric Bakke , Ellen Marie Bauman , Timothy Jerry Schimke , Lee Anton Sendelbach
IPC分类号： G06F13/10
CPC分类号： G06F3/0637 , G06F3/0622 , G06F3/067 , G06F21/80
摘要： A method, computer program product and computer system for assigning logic storage entities of a storage device to multiple partitions of a computer system, which includes associating each logic storage entity to one of the partitions that are allowed to access the logic storage entity; configuring a partition supervisor to control accesses of the partitions to the logic storage entities, so that the partitions can share resources when accessing the logic storage entities; and providing an interceptor in the partition supervisor, so that a request or a response between a select logic storage entity and a select partition is intercepted if the select partition is not allowed to access the select storage entity.
摘要翻译：一种用于将存储设备的逻辑存储实体分配给计算机系统的多个分区的方法，计算机程序产品和计算机系统，其包括将每个逻辑存储实体与允许访问逻辑存储实体的分区之一相关联; 配置分区管理程序以控制对逻辑存储实体的分区的访问，使得当访问逻辑存储实体时，分区可以共享资源; 以及在分区管理器中提供拦截器，使得如果不允许选择分区访问选择存储实体，则在选择逻辑存储实体和选择分区之间的请求或响应被拦截。

5. 发明申请

US20090300308A1 Partitioning of a Multiple Logic-Unit-Number SCSI Target 失效
标题翻译：多个逻辑单元号SCSI目标的分区
公开(公告)号：US20090300308A1
公开(公告)日：2009-12-03
申请号：US12132048
申请日：2008-06-03
申请人： Brian Eric Bakke , Ellen Marie Bauman , Timothy Jerry Schimke , Lee Anton Sendelbach
发明人： Brian Eric Bakke , Ellen Marie Bauman , Timothy Jerry Schimke , Lee Anton Sendelbach
IPC分类号： G06F12/14 , G06F12/00 , G06F12/02
CPC分类号： G06F3/0637 , G06F3/0622 , G06F3/067 , G06F21/80
摘要： A method, computer program product and computer system for assigning logic storage entities of a storage device to multiple partitions of a computer system, which includes associating each logic storage entity to one of the partitions that are allowed to access the logic storage entity; configuring a partition supervisor to control accesses of the partitions to the logic storage entities, so that the partitions can share resources when accessing the logic storage entities; and providing an interceptor in the partition supervisor, so that a request or a response between a select logic storage entity and a select partition is intercepted if the select partition is not allowed to access the select storage entity.
摘要翻译：一种用于将存储设备的逻辑存储实体分配给计算机系统的多个分区的方法，计算机程序产品和计算机系统，其包括将每个逻辑存储实体与允许访问逻辑存储实体的分区之一相关联; 配置分区管理程序以控制对逻辑存储实体的分区的访问，使得当访问逻辑存储实体时，分区可以共享资源; 以及在分区管理器中提供拦截器，使得如果不允许选择分区访问选择存储实体，则在选择逻辑存储实体和选择分区之间的请求或响应被拦截。

6. 发明授权

US06721839B1 Method of mapping multiple address spaces into single PCI bus 失效
标题翻译：将多个地址空间映射到单个PCI总线的方法
公开(公告)号：US06721839B1
公开(公告)日：2004-04-13
申请号：US09748983
申请日：2000-12-27
申请人： Ellen Marie Bauman , David Lee Dosch , Charles Scott Graham , Brian Gerard Holthaus , Daniel Robert Lipps , Daniel Frank Moertl , Paul Edward Movall , Daniel Paul Wetzel
发明人： Ellen Marie Bauman , David Lee Dosch , Charles Scott Graham , Brian Gerard Holthaus , Daniel Robert Lipps , Daniel Frank Moertl , Paul Edward Movall , Daniel Paul Wetzel
IPC分类号： G06F1300
CPC分类号： G06F13/404
摘要： A method and apparatus are provided for mapping multiple address spaces into a single bus, such as a single peripheral component interconnect (PCI) bus. The single bus is coupled to a first processor complex and a second processor complex. An original address of a memory access is shifted to a unique address space for each originator/target of an operation. The shifted address is used on the single bus. Then the shifted address is shifted back to the original address for completing the operation on a destination bus. The original address of a memory access is shifted to a unique address space for each originator/target of an operation using a respective predefined value (+X1, +X2, or +X3) for shifting the original address above a predefined boundary for each originator/target of the operation. Shifting back the shifted address to the original address for completing the operation on the destination bus uses a respective predefined value (−X1, −X2, or −X3) for the shifted back address to the original address for completing the operation on the destination bus. Using the shifted address on the single bus utilizes a dual address cycle (DAC) of the single bus for the shifted address. Completing the operation on a destination bus utilizes a single address cycle (SAC) of the destination bus for the shifted back address to the original address.
摘要翻译：提供了一种用于将多个地址空间映射到单个总线（诸如单个外围组件互连（PCI）总线）的方法和装置。单总线耦合到第一处理器复合体和第二处理器复合体。存储器访问的原始地址被移动到操作的每个发起者/目标的唯一地址空间。移位的地址用于单总线。然后将移位的地址移回原始地址，以完成目标总线上的操作。使用相应的预定义值（+ X1，+ X2或+ X3）将存储器访问的原始地址移动到每个发起者/目标的唯一地址空间，用于将原始地址移动到每个发起者的预定边界之上 /目标的操作。将移动的地址移动到原始地址以完成目的地总线上的操作，将移位后地址的相应预定义值（-X1，-X2或-X3）用于原始地址，以完成目标总线上的操作。使用单总线上的移位地址，可以使用单总线的双地址周期（DAC）作为移位地址。在目的地总线上完成操作将目的地总线的单个地址周期（SAC）用于移位后地址到原始地址。

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