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1. 发明授权

US06541327B1 Method to form self-aligned source/drain CMOS device on insulated staircase oxide 失效
标题翻译：在绝缘阶梯氧化物上形成自对准源极/漏极CMOS器件的方法
公开(公告)号：US06541327B1
公开(公告)日：2003-04-01
申请号：US09760123
申请日：2001-01-16
申请人： Lap Chan , Elgin Quek , Ravi Sundaresan , Yang Pan , James Yong Meng Lee , Ying Keung Leung , Yelehanka Ramachandramurthy Pradeep , Jia Zhen Zheng
发明人： Lap Chan , Elgin Quek , Ravi Sundaresan , Yang Pan , James Yong Meng Lee , Ying Keung Leung , Yelehanka Ramachandramurthy Pradeep , Jia Zhen Zheng
IPC分类号： H01L218238
CPC分类号： H01L29/66492 , H01L21/823814 , H01L29/41783 , H01L29/665 , H01L29/66575
摘要： A method to form elevated source/drain (S/D) over staircase shaped openings in insulating layers. A gate structure is formed over a substrate. The gate structure is preferably comprised of a gate dielectric layer, gate electrode, first spacers, and hard mask. A first insulating layer is formed over the substrate and the gate structure. A resist layer is formed having an opening over the gate structure and over a lateral area adjacent to the gate structure. We etch the insulating layer through the opening in the resist layer. The etching removes a first thickness of the insulating layer to form a source/drain (S/D) opening. We remove the first spacers and hardmask to form a source/drain (S/D) contact opening. We implant ions into the substrate through the source/drain (S/D) contact opening to form lightly doped drain regions. We form second spacers on the sidewalls of the gate electrode and the gate dielectric and on the sidewalls of the insulating layer in the source/drain (S/D) contact opening and the source/drain (S/D) opening. A conductive layer is deposited over the gate electrode, the insulating layer. The conductive layer is planarized to exposed the insulating layer to form elevated source/drain (S/D) blocks on a staircase shape insulating layer.
摘要翻译：一种在绝缘层中的阶梯形开口形成升高的源极/漏极（S / D）的方法。栅极结构形成在衬底上。栅极结构优选由栅极电介质层，栅电极，第一间隔物和硬掩模组成。在衬底和栅极结构之上形成第一绝缘层。形成抗蚀剂层，其具有在栅极结构上方的开口以及与栅极结构相邻的横向区域。我们通过抗蚀剂层中的开口蚀刻绝缘层。蚀刻去除绝缘层的第一厚度以形成源极/漏极（S / D）开口。我们移除第一个垫片和硬掩模以形成一个源极/漏极（S / D）接触开口。我们通过源极/漏极（S / D）接触开口将离子注入到衬底中，以形成轻掺杂的漏极区。我们在源极/漏极（S / D）接触开口和源极/漏极（S / D）开口中的栅电极和栅极电介质的侧壁和绝缘层的侧壁上形成第二间隔物。在栅电极，绝缘层上沉积导电层。导电层被平坦化以暴露绝缘层，以在阶梯形绝缘层上形成升高的源极/漏极（S / D）块。

2. 发明授权

US06436770B1 Method to control the channel length of a vertical transistor by first forming channel using selective epi and source/drain using implantation 失效
标题翻译：通过使用选择性外延和使用注入的源极/漏极首先形成沟道来控制垂直晶体管的沟道长度的方法
公开(公告)号：US06436770B1
公开(公告)日：2002-08-20
申请号：US09721720
申请日：2000-11-27
申请人： Ying Keung Leung , Yelehanka Ramachandramurthy Pradeep , Jia Zhen Zheng , Lap Chan , Elgin Quek , Ravi Sundaresan , Yang Pan , James Yong Meng Lee
发明人： Ying Keung Leung , Yelehanka Ramachandramurthy Pradeep , Jia Zhen Zheng , Lap Chan , Elgin Quek , Ravi Sundaresan , Yang Pan , James Yong Meng Lee
IPC分类号： H01L21332
CPC分类号： H01L29/7827 , H01L29/42356 , H01L29/66666
摘要： A method for a vertical MOS transistor whose vertical channel width can be accurately defined and controlled. Isolation regions are formed in a substrate. The isolation regions defining an active area. Then, we form a source region in the active area. A dielectric layer is formed over the active area and the isolation regions. We form a barrier layer over the dielectric layer. We form an opening in the barrier layer. A gate layer is formed in the opening. We form an insulating layer over the conductive layer and the barrier layer. We form a gate opening through the insulating layer, the gate layer and the dielectric layer to expose the source region. Gate dielectric spacers are formed over the sidewalls of the gate layer. Then, we form a conductive plug filling the gate opening. The insulating layer is removed. We form a drain region in top and side portions of the conductive plug and form doped gate regions in the gate layer. The remaining portions of the conductive plug comprise a channel region. A channel length is between the top of the source region and the drain region. We form an interlevel dielectric layer over the barrier layer, the gate layer, and the conductive plug. Contacts are formed through the interlevel dielectric layer to the doped gate regions, the drain region and the source region.
摘要翻译：一种垂直MOS晶体管的方法，其垂直沟道宽度可以被精确地限定和控制。在衬底中形成隔离区。隔离区限定有效区域。然后，我们在活动区域中形成一个源区域。在有源区域和隔离区域上形成介电层。我们在电介质层上形成阻挡层。我们在屏障层形成一个开口。在开口中形成栅极层。我们在导电层和阻挡层上形成绝缘层。我们通过绝缘层，栅极层和电介质层形成栅极开口以暴露源极区域。栅极电介质隔离物形成在栅极层的侧壁上。然后，我们形成一个填充门开口的导电塞。绝缘层被去除。我们在导电插塞的顶部和侧部形成漏极区，并在栅极层中形成掺杂的栅极区。导电插塞的其余部分包括沟道区域。沟道长度在源极区域的顶部和漏极区域之间。我们在阻挡层，栅极层和导电插塞上形成层间电介质层。通过层间介质层与掺杂栅极区，漏极区和源极区形成触点。

3. 发明授权

US06313008B1 Method to form a balloon shaped STI using a micro machining technique to remove heavily doped silicon 失效
标题翻译：使用微加工技术形成气球形STI以去除重掺杂硅的方法
公开(公告)号：US06313008B1
公开(公告)日：2001-11-06
申请号：US09768486
申请日：2001-01-25
申请人： Ying Keung Leung , Yelehanka Ramachandramurthy Pradeep , Jia Zhen Zheng , Lap Chan , Elgin Quek , Ravi Sundaresan , Yang Pan , James Yong Meng Lee
发明人： Ying Keung Leung , Yelehanka Ramachandramurthy Pradeep , Jia Zhen Zheng , Lap Chan , Elgin Quek , Ravi Sundaresan , Yang Pan , James Yong Meng Lee
IPC分类号： H01L2176
CPC分类号： H01L21/76232
摘要： The invention describes three embodiments of methods for forming a balloon shaped STI trench. The first embodiment begins by forming a barrier layer over a substrate. An isolation opening is formed in the barrier layer. Next, ions are implanted into said substrate through said isolation opening to form a Si damaged or doped first region. The first region is selectively etching to form a hole. The hole is filled with an insulating material to form a balloon shaped shallow trench isolation (STI) region. The substrate has active areas between said balloon shaped shallow trench isolation (STI) regions. The second embodiment differs from the first embodiment by forming a trench in the substrate before the implant. The third embodiment forms a liner in the trench before an isotropic etch of the substrate through the trench.
摘要翻译：本发明描述了形成球形STI沟槽的方法的三个实施例。第一实施例开始于在衬底上形成阻挡层。在阻挡层中形成隔离开口。接下来，通过所述隔离开口将离子注入到所述衬底中，以形成Si损伤或掺杂的第一区域。第一区域是选择性蚀刻以形成孔。孔用绝缘材料填充以形成气球形的浅沟槽隔离（STI）区域。衬底在所述球形浅沟槽隔离（STI）区域之间具有有效区域。第二实施例通过在植入物之前在衬底中形成沟槽而与第一实施例不同。在通过沟槽对衬底进行各向同性蚀刻之前，第三实施例在沟槽中形成衬垫。

4. 发明授权

US06468877B1 Method to form an air-gap under the edges of a gate electrode by using disposable spacer/liner 有权
标题翻译：通过使用一次性间隔件/衬垫在栅电极的边缘下形成气隙的方法
公开(公告)号：US06468877B1
公开(公告)日：2002-10-22
申请号：US09907651
申请日：2001-07-19
申请人： Yelehanka Ramachandramurthy Pradeep , Jia Zhen Zheng , Lap Chan , Elgin Quek , Ravi Sundaresan , Yang Pan , James Yong Meng Lee , Ying Keung Leung
发明人： Yelehanka Ramachandramurthy Pradeep , Jia Zhen Zheng , Lap Chan , Elgin Quek , Ravi Sundaresan , Yang Pan , James Yong Meng Lee , Ying Keung Leung
IPC分类号： H01L2176
CPC分类号： H01L21/7682 , H01L21/764 , H01L21/823468 , H01L29/4983
摘要： A method of fabricating an air-gap spacer of a semiconductor device, comprising the following steps. A semiconductor substrate having at least a pair of STIs defining an active region is provided. A gate electrode is formed on the substrate within the active region. The gate electrode having an underlying gate dielectric layer. A liner oxide layer is formed over the structure, covering the sidewalls of the gate dielectric layer, the gate electrode, and over the top surface of the gate electrode. A liner nitride layer is formed over the liner oxide layer. A thick oxide layer is formed over the structure. The thick oxide, liner nitride, and liner oxide layers are planarized level with the top surface of the gate electrode, and exposing the liner oxide layer at either side of the gate electrode. The planarized thick oxide layer is removed with a portion of the liner oxide layer and a portion of the gate dielectric layer under the gate electrode to form a cross-section inverted T-shaped opening on either side of the gate electrode. A gate spacer oxide layer is formed over the structure at least as thick as the gate electrode, wherein the gate spacer oxide layer partially fills the inverted T-shaped opening from the top down and wherein air gap spacers are formed proximate the bottom of the inverted T-shaped opening. The gate spacer oxide, liner nitride, and liner oxide layers are etched to form gate spacers proximate the gate electrode. The gate spacers having an underlying etched liner nitride layer and liner oxide layer.
摘要翻译：一种制造半导体器件的气隙间隔物的方法，包括以下步骤。提供具有至少一对限定有源区域的STI的半导体衬底。在有源区内的基板上形成栅电极。栅电极具有底层栅介电层。在该结构上形成衬里氧化物层，覆盖栅极电介质层的侧壁，栅电极以及栅电极的顶表面。在衬垫氧化物层上形成衬里氮化物层。在结构上形成厚的氧化物层。厚氧化物，衬里氮化物和衬里氧化物层与栅电极的顶表面平坦化，并且在栅电极的任一侧暴露衬里氧化物层。用一部分衬垫氧化物层和栅电介质层的一部分在栅电极下方去除平坦化的厚氧化物层，以在栅电极的任一侧上形成横截面倒置的T形开口。在该结构上形成至少与栅电极一样厚的栅极间隔氧化物层，其中栅极间隔物氧化物层从顶部向下部分地填充倒置的T形开口，并且其中气隙间隔物邻近倒置的底部形成 T形开口。蚀刻栅间隔氧化物，衬里氮化物和衬里氧化物层以在栅电极附近形成栅极间隔。栅极间隔物具有下面的蚀刻衬里氮化物层和衬里氧化物层。

5. 发明授权

US06455377B1 Method to form very high mobility vertical channel transistor by selective deposition of SiGe or multi-quantum wells (MQWs) 失效
标题翻译：通过SiGe或多量子阱（MQW）的选择性沉积形成非常高迁移率的垂直沟道晶体管的方法
公开(公告)号：US06455377B1
公开(公告)日：2002-09-24
申请号：US09765040
申请日：2001-01-19
申请人： Jia Zhen Zheng , Lap Chan , Elgin Quek , Ravi Sundaresan , Yang Pan , James Yong Meng Lee , Ying Keung Leung , Yelehanka Ramachandramurthy Pradeep
发明人： Jia Zhen Zheng , Lap Chan , Elgin Quek , Ravi Sundaresan , Yang Pan , James Yong Meng Lee , Ying Keung Leung , Yelehanka Ramachandramurthy Pradeep
IPC分类号： H01L21336
CPC分类号： H01L29/66666 , H01L29/1054 , H01L29/66916 , H01L29/7827 , H01L29/802
摘要： A method of fabricating a vertical channel transistor, comprising the following steps. A semiconductor substrate having an upper surface is provided. A high doped N-type lower epitaxial silicon layer is formed on the semiconductor substrate. A low doped P-type middle epitaxial silicon layer is formed on the lower epitaxial silicon layer. A high doped N-type upper epitaxial silicon layer is formed on the middle epitaxial silicon layer. The lower, middle, and upper epitaxial silicon layers are etched to form a epitaxial layer stack defined by isolation trenches. Oxide is formed within the isolation trenches. The oxide is etched to form a gate trench within one of the isolation trenches exposing a sidewall of the epitaxial layer stack facing the gate trench. Multi-quantum wells or a stained-layer super lattice is formed on the exposed epitaxial layer stack sidewall. A gate dielectric layer is formed on the multi-quantum wells or the stained-layer super lattice and within the gate trench. A gate conductor layer is formed on the gate dielectric layer, filling the gate trench.
摘要翻译：一种制造垂直沟道晶体管的方法，包括以下步骤。提供具有上表面的半导体衬底。在半导体衬底上形成高掺杂N型下部外延硅层。在下部外延硅层上形成低掺杂P型中间外延硅层。在中间外延硅层上形成高掺杂N型上部外延硅层。蚀刻下部，中间和上部外延硅层以形成由隔离沟槽限定的外延层堆叠。在隔离槽内形成氧化物。氧化物被蚀刻以在一个隔离沟槽内形成栅极沟槽，暴露外延层堆叠面向栅极沟槽的侧壁。在暴露的外延层堆叠侧壁上形成多量子阱或染色层超晶格。在多量子阱或染色层超晶格上并在栅极沟槽内形成栅介质层。栅极导体层形成在栅极电介质层上，填充栅极沟槽。

6. 发明授权

US06440800B1 Method to form a vertical transistor by selective epitaxial growth and delta doped silicon layers 失效
公开(公告)号：US06440800B1
公开(公告)日：2002-08-27
申请号：US09769814
申请日：2001-01-26
申请人： James Yong Meng Lee , Ying Keung Leung , Yelehanka Ramachandramurthy Pradeep , Jia Zhen Zheng , Lap Chan , Elgin Quek , Ravi Sundaresan , Yang Pan
发明人： James Yong Meng Lee , Ying Keung Leung , Yelehanka Ramachandramurthy Pradeep , Jia Zhen Zheng , Lap Chan , Elgin Quek , Ravi Sundaresan , Yang Pan
IPC分类号： H01L21336
CPC分类号： H01L29/66666 , H01L29/365 , H01L29/7827
摘要： A method for a vertical transistor by selective epi deposition to form the conductive source, drain, and channel layers. The conductive source, drain, and channel layers are preferably formed by a selective epi process. Dielectric masks define the conductive layers and make areas to form vertical contacts to the conductive S/D and channel layers.

7. 发明授权

US06417056B1 Method to form low-overlap-capacitance transistors by forming microtrench at the gate edge 失效
标题翻译：通过在栅极边缘形成微动开关来形成低重叠电容晶体管的方法
公开(公告)号：US06417056B1
公开(公告)日：2002-07-09
申请号：US09981439
申请日：2001-10-18
申请人： Elgin Quek , Ravi Sundaresan , Yang Pan , James Yong Meng Lee , Ying Keung Leung , Yelehanka Ramachandramurthy Pradeep , Jia Zhen Zheng , Lap Chan
发明人： Elgin Quek , Ravi Sundaresan , Yang Pan , James Yong Meng Lee , Ying Keung Leung , Yelehanka Ramachandramurthy Pradeep , Jia Zhen Zheng , Lap Chan
IPC分类号： H01L21336
CPC分类号： H01L29/66636 , H01L29/0649 , H01L29/665 , H01L29/66545 , H01L29/7834
摘要： A method for forming a transistor having low overlap capacitance by forming a microtrench at the gate edge to reduce effective dielectric constant is described. A gate electrode is provided overlying a gate dielectric layer on a substrate and having a hard mask layer thereover. An oxide layer is formed overlying the substrate. First spacers are formed on sidewalls of the gate electrode and overlying the oxide layer. Source/drain extensions are implanted. Second spacers are formed on the first spacers. Source/drain regions are implanted. A dielectric layer is deposited overlying the gate electrode and the oxide layer and planarized to the hard mask layer whereby the first and second spacers are exposed. The exposed second spacers and underlying oxide layer are removed. The exposed substrate underlying the second spacers is etched into to form a microtrench undercutting the gate oxide layer at an edge of the gate electrode. The microtrench is filled with an epitaxial oxide layer and planarized to the hard mask layer. The dielectric layer is patterned to form third spacers on the epitaxial oxide layer. The microtrench reduces the effective dielectric constant at the overlap between the gate and the source/drain extensions to complete formation of a transistor having low overlap capacitance.
摘要翻译：描述了通过在栅极边缘处形成微通孔以形成具有低重叠电容的晶体管以降低有效介电常数的方法。栅电极被设置在衬底上的栅介电层上，并且在其上具有硬掩模层。在衬底上形成氧化物层。第一间隔物形成在栅电极的侧壁上并覆盖氧化物层。源/漏扩展被植入。第二间隔件形成在第一间隔件上。源极/漏极区域被植入。沉积覆盖在栅电极和氧化物层上的介电层，并且平坦化到硬掩模层，由此使第一和第二间隔物暴露。去除暴露的第二间隔物和下面的氧化物层。蚀刻第二间隔物下面的暴露的基底以形成在栅电极的边缘处切割栅极氧化物层的微切口。微通孔填充有外延氧化物层并且平坦化到硬掩模层。图案化电介质层以在外延氧化物层上形成第三间隔物。微通道减小栅极和源极/漏极延伸部之间的重叠处的有效介电常数，以完成具有低重叠电容的晶体管的形成。

8. 发明授权

US06406945B1 Method for forming a transistor gate dielectric with high-K and low-K regions 有权
标题翻译：用于形成具有高K和低K区的晶体管栅极电介质的方法
公开(公告)号：US06406945B1
公开(公告)日：2002-06-18
申请号：US09769810
申请日：2001-01-26
申请人： James Yong Meng Lee , Ying Keung Leung , Yelehanka Ramachandramurthy Pradeep , Jia Zhen Zheng , Lap Chan , Elgin Quek , Ravi Sundaresan , Yang Pan
发明人： James Yong Meng Lee , Ying Keung Leung , Yelehanka Ramachandramurthy Pradeep , Jia Zhen Zheng , Lap Chan , Elgin Quek , Ravi Sundaresan , Yang Pan
IPC分类号： H01L21335
CPC分类号： H01L29/517 , H01L21/28167 , H01L21/28194 , H01L29/42376 , H01L29/512 , H01L29/518 , H01L29/66583 , Y10S257/90
摘要： A method for forming a gate dielectric having regions with different dielectric constants. A dummy dielectric layer is formed over a semiconductor structure. The dummy dielectric layer is patterned to form a gate opening. A high-K dielectric layer is formed over the dummy dielectric and in the gate opening. A low-K dielectric layer is formed on the high-K dielectric layer. Spacers are formed on the low-K dielectric layer at the edges of the gate opening. The low-K dielectric layer is removed from the bottom of the gate opening between the spacers. The spacers are removed to form a stepped gate opening. The stepped gate opening has both a high-K dielectric layer and a low-K dielectric layer on the sidewalls and at the edges of the bottom of the gate opening and only a high-k dielectric layer in the center of the bottom of the stepped gate opening. A gate electrode is formed in the stepped gate opening.
摘要翻译：一种形成具有不同介电常数区域的栅极电介质的方法。在半导体结构上形成虚拟电介质层。图案化虚拟介质层以形成栅极开口。在虚拟电介质上和栅极开口中形成高K电介质层。在高K电介质层上形成低K电介质层。在栅极开口边缘的低K电介质层上形成间隔物。低K电介质层从间隔物之间的栅极开口的底部去除。移除间隔件以形成阶梯式门开口。阶梯式门开口在侧壁和栅极开口底部的边缘处具有高K电介质层和低K电介质层，并且仅在台阶底部中心的高k电介质层开门在阶梯式门开口形成栅电极。

9. 发明授权

US06709934B2 Method for forming variable-K gate dielectric 失效
标题翻译：用于形成可变K栅极电介质的方法
公开(公告)号：US06709934B2
公开(公告)日：2004-03-23
申请号：US10196111
申请日：2002-07-16
申请人： James Yong Meng Lee , Ying Keung Leung , Yelehanka Ramachandramurthy Pradeep , Jia Zhen Zheng , Lap Chan , Elgin Quek , Ravi Sundaresan , Yang Pan
发明人： James Yong Meng Lee , Ying Keung Leung , Yelehanka Ramachandramurthy Pradeep , Jia Zhen Zheng , Lap Chan , Elgin Quek , Ravi Sundaresan , Yang Pan
IPC分类号： H01L21336
CPC分类号： H01L21/28194 , H01L29/42376 , H01L29/512 , H01L29/517 , H01L29/518 , H01L29/66583
摘要： A method for forming a gate dielectric having regions with different dielectric constants. A low-K dielectric layer is formed over a semiconductor structure. A dummy dielectric layer is formed over the low-K dielectric layer. The dummy dielectric layer and low-K dielectric layer are patterned to form an opening. The dummy dielectric layer is isontropically etched selectively to the low-K dielectric layer to form a stepped gate opening. A high-K dielectric layer is formed over the dummy dielectric and in the stepped gate opening. A gate electrode is formed on the high-K dielectric layer.
摘要翻译：一种形成具有不同介电常数区域的栅极电介质的方法。在半导体结构上形成低K电介质层。在低K电介质层上形成虚拟电介质层。图案化虚拟介电层和低K电介质层以形成开口。虚拟电介质层被选择性地蚀刻到低K电介质层以形成阶梯式栅极开口。在虚拟电介质和阶梯式门开口中形成高K电介质层。在高K电介质层上形成栅电极。

10. 发明授权

US06511884B1 Method to form and/or isolate vertical transistors 有权
标题翻译：形成和/或隔离垂直晶体管的方法
公开(公告)号：US06511884B1
公开(公告)日：2003-01-28
申请号：US09972503
申请日：2001-10-09
申请人： Elgin Quek , Ravi Sundaresan , Yang Pan , Yong Meng Lee , Ying Keung Leung , Yelehanka Ramachandramurthy Pradeep , Jia Zhen Zheng , Lap Chan
发明人： Elgin Quek , Ravi Sundaresan , Yang Pan , Yong Meng Lee , Ying Keung Leung , Yelehanka Ramachandramurthy Pradeep , Jia Zhen Zheng , Lap Chan
IPC分类号： H01L21336
CPC分类号： H01L29/66666 , H01L29/7827
摘要： A method of fabricating an isolated vertical transistor comprising the following steps. A wafer having a first implanted region selected from the group comprising a source region and a drain region is provided. The wafer further includes STI areas on either side of a center transistor area. The wafer is patterned down to the first implanted region to form a vertical pillar within the center transistor area using a patterned hardmask. The vertical pillar having side walls. A pad dielectric layer is formed over the wafer, lining the vertical pillar. A nitride layer is formed over the pad dielectric layer. The structure is patterned and etched through the nitride layer and the pad dielectric layer; and into the wafer within the STI areas to form STI trenches within the wafer. The STI trenches are filled with insulative material to form STIs within STI trenches. The patterned nitride and pad dielectric layers are removed. The patterned hardmask is removed. Gate oxide is grown over the exposed portions of the wafer and the vertical pillar. Spacer gates are formed over the gate oxide lined side walls of the vertical pillar. Spacer gate implants are formed within the spacer gates, and a second implanted region is formed within the vertical pillar selected from the group consisting of a drain region and a source region that is not the same as the first implanted region to complete formation of the isolated vertical transistor.
摘要翻译：一种制造隔离垂直晶体管的方法，包括以下步骤。提供具有从包括源极区域和漏极区域的组中选择的第一注入区域的晶片。该晶片还包括在中心晶体管区域两侧的STI区域。将晶片图案化到第一注入区域，以使用图案化的硬掩模在中心晶体管区域内形成垂直柱。具有侧壁的立柱。在晶片上形成衬垫介质层，衬在垂直柱上。在焊盘介电层上形成氮化物层。该结构被图案化并蚀刻通过氮化物层和焊盘介电层; 并进入STI区域内的晶片，以在晶片内形成STI沟槽。 STI沟槽填充有绝缘材料，以在STI沟槽内形成STI。图案化的氮化物和焊盘介电层被去除。去除图案化的硬掩模。栅极氧化物生长在晶片和垂直柱的暴露部分上。在垂直柱的栅极氧化物衬里侧壁上形成间隔栅极。间隔栅极内部形成间隔栅极，并且在垂直柱内形成第二注入区，该垂直柱选自由漏极区域和不同于第一注入区域的源极区域组成的组，以完成孤立的垂直晶体管。

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