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1. 发明授权

US06631086B1 On-chip repair of defective address of core flash memory cells 有权
标题翻译：核心闪存单元故障地址的片上修复
公开(公告)号：US06631086B1
公开(公告)日：2003-10-07
申请号：US10200544
申请日：2002-07-22
申请人： Colin Bill , Ken Cheong Cheah , Edward V. Bautista, Jr. , Azrul Halim , Darlene G. Hamilton
发明人： Colin Bill , Ken Cheong Cheah , Edward V. Bautista, Jr. , Azrul Halim , Darlene G. Hamilton
IPC分类号： G11C1606
CPC分类号： G11C29/72 , G11C15/00 , G11C16/04 , G11C29/16 , G11C29/44 , G11C29/48
摘要： In a method and system for repairing defective flash memory cells fabricated on a semiconductor substrate, a repair controller and a plurality of voltage sources are fabricated on the semiconductor substrate. The repair controller controls the voltage sources to apply programming voltages on respective CAM (content addressable memory) flash memory cells in a JUICE state for replacing the defective flash memory cells with a corresponding redundancy element of flash memory cells. In addition, a FAILREP logic is fabricated on the semiconductor substrate for entering a HANG state if no redundancy element of flash memory cells is available or if the defective flash memory cells have been previously repaired.
摘要翻译：在用于修复在半导体衬底上制造的有缺陷的闪速存储器单元的方法和系统中，在半导体衬底上制造修复控制器和多个电压源。修理控制器控制电压源以将编程电压施加在JUICE状态的相应CAM（内容可寻址存储器）闪存单元上，以用闪存单元的相应冗余元件代替有缺陷的闪存单元。此外，如果没有闪存单元的冗余元件可用或者有缺陷的闪速存储器单元已经被修复，则在半导体衬底上制造FAILREP逻辑用于进入HANG状态。

2. 发明授权

US06707718B1 Generation of margining voltage on-chip during testing CAM portion of flash memory device 失效
标题翻译：在闪速存储器件的测试CAM部分期间片上产生裕度电压
公开(公告)号：US06707718B1
公开(公告)日：2004-03-16
申请号：US10200539
申请日：2002-07-22
申请人： Azrul Halim , Colin Bill , Ken Cheong Cheah , Syahrizal Salleh
发明人： Azrul Halim , Colin Bill , Ken Cheong Cheah , Syahrizal Salleh
IPC分类号： G11C1606
CPC分类号： G11C29/44 , G11C16/04 , G11C29/16 , G11C29/48
摘要： For generating a margining voltage for biasing a gate of a CAM (content addressable memory) cell of a flash memory device fabricated on a semiconductor wafer, a high voltage source is provided with a voltage generator fabricated on the semiconductor wafer. A low voltage source is provided from a node coupled to the voltage generator fabricated on the semiconductor wafer. For example, the voltage generator for providing the high voltage source includes a voltage regulator and a charge pump fabricated on the semiconductor wafer, and the low voltage source is the ground node. In addition, a first transistor is coupled to the high voltage source, and a second transistor is coupled to the low voltage source. A first resistor is coupled between the first transistor and an output node, and a second resistor coupled between the second transistor and the output node. The margining voltage is generated at the output node. The first resistor and the second resistor form a resistive voltage divider at the output node between the high voltage source and the low voltage source when the first transistor and the second transistor are turned on. A logic circuit turns on the first transistor and the second transistor when a first set of control signals indicate that program margining of the CAM cell during a BIST (built-in-self-test) mode is invoked. The first transistor, the second transistor, the first resistor, the second resistor, and the logic circuit are fabricated on the semiconductor wafer. In another embodiment of the present invention, the logic circuit turns off the first transistor and turns on the second transistor such that the output node discharges to a voltage of the low voltage source for erase margining of the CAM cell.
摘要翻译：为了产生用于偏置制造在半导体晶片上的闪存器件的CAM（内容可寻址存储器）单元的栅极的裕度电压，高电压源设置有制造在半导体晶片上的电压发生器。从耦合到制造在半导体晶片上的电压发生器的节点提供低电压源。例如，用于提供高电压源的电压发生器包括在半导体晶片上制造的电压调节器和电荷泵，而低电压源是接地节点。此外，第一晶体管耦合到高电压源，第二晶体管耦合到低电压源。第一电阻器耦合在第一晶体管和输出节点之间，第二电阻耦合在第二晶体管和输出节点之间。在输出节点产生裕度电压。当第一晶体管和第二晶体管导通时，第一电阻器和第二电阻器在高电压源和低电压源之间的输出节点处形成电阻分压器。当第一组控制信号指示在BIST（内置自测试）模式期间CAM单元的编程余量被调用时，逻辑电路接通第一晶体管和第二晶体管。在半导体晶片上制造第一晶体管，第二晶体管，第一电阻器，第二电阻器和逻辑电路。在本发明的另一个实施例中，逻辑电路关闭第一晶体管并导通第二晶体管，使得输出节点放电到低电压源的电压以消除CAM单元的擦除裕度。

3. 发明授权

US06587982B1 Method of micro-architectural implementation of interface between bist state machine and tester interface to enable bist cycling 失效
标题翻译：双机状态机与测试仪接口之间的界面的微架构实现方法，以实现双轨循环
公开(公告)号：US06587982B1
公开(公告)日：2003-07-01
申请号：US09654965
申请日：2000-09-05
申请人： Weng F. Lee , Colin S. Bill , Feng Pan , Edward V. Bautista , Azrul Halim
发明人： Weng F. Lee , Colin S. Bill , Feng Pan , Edward V. Bautista , Azrul Halim
IPC分类号： G01R3128
CPC分类号： G01R31/31724 , G01R31/3187 , G11C29/1201 , G11C29/16 , G11C29/48
摘要： There is provided a tester interface circuit for use with a BIST state machine and a method for micro-architectural implementation of the same so as to enable cycling through a BIST test. The tester interface circuit includes a storage device, a logic decoder, a set/clear mechanism, and a polling logic device. The tester interface circuit is implemented with a minimum amount of chip area on a semiconductor IC.
摘要翻译：提供了一种用于BIST状态机的测试器接口电路和用于微结构实现的方法，以便能够通过BIST测试循环。测试器接口电路包括存储设备，逻辑解码器，集合/清除机制和轮询逻辑设备。测试器接口电路在半导体IC上以最小量的芯片面积实现。

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