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1. 发明授权

US07227204B2 Structure for improved diode ideality 有权
标题翻译：改善二极管理想的结构
公开(公告)号：US07227204B2
公开(公告)日：2007-06-05
申请号：US10906366
申请日：2005-02-16
申请人： Edward P. Maciejewski , Sherry A. Womack , Shreesh Narasimha , Christopher D. Sheraw
发明人： Edward P. Maciejewski , Sherry A. Womack , Shreesh Narasimha , Christopher D. Sheraw
IPC分类号： H01L29/76 , H01L31/119 , H01L23/58 , H01L29/861 , H01L29/00
CPC分类号： H01L27/0629 , H01L27/0814 , H01L29/66136 , H01L29/861
摘要： A device is provided which includes a single-crystal semiconductor region disposed in a substrate. The single-crystal region includes a first semiconductor material and a diode disposed in the single-crystal region. The diode includes an anode region including a first alloy region, being an alloy of the first semiconductor material with a second semiconductor material, and a second region which consists essentially of the first semiconductor material, the diode further including a cathode region.
摘要翻译：提供一种器件，其包括设置在衬底中的单晶半导体区域。单晶区域包括设置在单晶区域中的第一半导体材料和二极管。该二极管包括一个阳极区域，该阳极区域包括第一合金区域，该第一合金区域是第一半导体材料与第二半导体材料的合金，以及第二区域，该第二区域基本上由第一半导体材料组成，二极管还包括阴极区域。

2. 发明授权

US08779551B2 Gated diode structure for eliminating RIE damage from cap removal 失效
标题翻译：门二极管结构，用于消除去除盖子的RIE损坏
公开(公告)号：US08779551B2
公开(公告)日：2014-07-15
申请号：US13489537
申请日：2012-06-06
申请人： Anthony I. Chou , Arvind Kumar , Edward P. Maciejewski , Shreesh Narasimha , Dustin K. Slisher
发明人： Anthony I. Chou , Arvind Kumar , Edward P. Maciejewski , Shreesh Narasimha , Dustin K. Slisher
IPC分类号： H01L27/06
CPC分类号： H01L21/8238 , H01L21/265 , H01L21/77 , H01L21/823835 , H01L27/0629 , H01L27/1203 , H01L29/42364 , H01L29/7391 , H01L29/861
摘要： A semiconductor structure provided with a plurality of gated-diodes having a silicided anode (p-doped region) and cathode (n-doped region) and a high-K gate stack made of non-silicided gate material, the gated-diodes being adjacent to FETs, each of which having a silicided source, a silicided drain and a silicided HiK gate stack. The semiconductor structure eliminates a cap removal RIE in a gate first High-K metal gate flow from the region of the gated-diode. The lack of silicide and the presence of a nitride barrier on the gate of the diode are preferably made during the gate first process flow. The absence of the cap removal RIE is beneficial in that diffusions of the diode are not subjected to the cap removal RIE, which avoids damage and allows retaining its highly ideal junction characteristics.
摘要翻译：一种半导体结构，其具有多个具有硅化阳极（p掺杂区域）和阴极（n掺杂区域）的门控二极管和由非硅化栅极材料制成的高K栅极堆叠，该门控二极管相邻其中每一个具有硅化源，硅化物漏极和硅化HiK栅极叠层。半导体结构消除了栅极第一高K金属栅极流从栅极二极管的区域流出的帽去除RIE。优选在栅极第一工艺流程期间，在二极管的栅极上缺少硅化物和存在氮化物阻挡层。没有帽去除RIE是有益的，因为二极管的扩散不经受帽去除RIE，这避免了损伤并且允许保持其高度理想的结特性。

3. 发明申请

US20130328124A1 GATED DIODE STRUCTURE FOR ELIMINATING RIE DAMAGE FROM CAP REMOVAL 失效
标题翻译：用于消除从盖拆卸中的RIE损伤的栅极二极管结构
公开(公告)号：US20130328124A1
公开(公告)日：2013-12-12
申请号：US13489537
申请日：2012-06-06
申请人： Anthony I. Chou , Arvind Kumar , Edward P. Maciejewski , Shreesh Narasimha , Dustin K. Slisher
发明人： Anthony I. Chou , Arvind Kumar , Edward P. Maciejewski , Shreesh Narasimha , Dustin K. Slisher
IPC分类号： H01L27/06 , H01L21/8238
CPC分类号： H01L21/8238 , H01L21/265 , H01L21/77 , H01L21/823835 , H01L27/0629 , H01L27/1203 , H01L29/42364 , H01L29/7391 , H01L29/861
摘要： A semiconductor structure provided with a plurality of gated-diodes having a silicided anode (p-doped region) and cathode (n-doped region) and a high-K gate stack made of non-silicided gate material, the gated-diodes being adjacent to FETs, each of which having a silicided source, a silicided drain and a silicided HiK gate stack. The semiconductor structure eliminates a cap removal RIE in a gate first High-K metal gate flow from the region of the gated-diode. The lack of silicide and the presence of a nitride barrier on the gate of the diode are preferably made during the gate first process flow. The absence of the cap removal RIE is beneficial in that diffusions of the diode are not subjected to the cap removal RIE, which avoids damage and allows retaining its highly ideal junction characteristics.
摘要翻译：一种半导体结构，其具有多个具有硅化阳极（p掺杂区域）和阴极（n掺杂区域）的门控二极管和由非硅化栅极材料制成的高K栅极堆叠，该门控二极管相邻其中每一个具有硅化源，硅化物漏极和硅化HiK栅极叠层。半导体结构消除了栅极第一高K金属栅极流从栅极二极管的区域流出的帽去除RIE。优选在栅极第一工艺流程期间，在二极管的栅极上缺少硅化物和存在氮化物阻挡层。没有帽去除RIE是有益的，因为二极管的扩散不经受帽去除RIE，这避免了损伤并且允许保持其高度理想的结特性。

4. 发明授权

US06991979B2 Method for avoiding oxide undercut during pre-silicide clean for thin spacer FETs 有权
公开(公告)号：US06991979B2
公开(公告)日：2006-01-31
申请号：US10605311
申请日：2003-09-22
申请人： Atul C. Ajmera , Andres Bryant , Percy V. Gilbert , Michael A Gribelyuk , Edward P. Maciejewski , Renee T. Mo , Shreesh Narasimha
发明人： Atul C. Ajmera , Andres Bryant , Percy V. Gilbert , Michael A Gribelyuk , Edward P. Maciejewski , Renee T. Mo , Shreesh Narasimha
IPC分类号： H01L21/8238
CPC分类号： H01L21/02063 , H01L21/31116 , H01L21/823835 , H01L21/823864 , H01L29/665 , H01L29/6653 , H01L29/6656 , H01L2924/0002 , H01L2924/00
摘要： A method for forming a CMOS device in a manner so as to avoid dielectric layer undercut during a pre-silicide cleaning step is described. During formation of CMOS device comprising a gate stack on a semiconductor substrate surface, the patterned gate stack including gate dielectric below a conductor with vertical sidewalls, a dielectric layer is formed thereover and over the substrate surfaces. Respective nitride spacer elements overlying the dielectric layer are formed at each vertical sidewall. The dielectric layer on the substrate surface is removed using an etch process such that a portion of the dielectric layer underlying each spacer remains. Then, a nitride layer is deposited over the entire sample (the gate stack, the spacer elements at each gate sidewall, and substrate surfaces) and subsequently removed by an etch process such that only a portion of said nitride film (the “plug”) remains. The plug seals and encapsulates the dielectric layer underlying each said spacer, thus preventing the dielectric material from being undercut during the subsequent pre-silicide clean process. By preventing undercut, this invention also prevents the etch-stop film (deposited prior to contact formation) from coming into contact with the gate oxide. Thus, the integration of thin-spacer transistor geometries, which are required for improving transistor drive current, is enabled.

5. 发明授权

US07091128B2 Method for avoiding oxide undercut during pre-silicide clean for thin spacer FETs 失效
标题翻译：避免氧化物底切在薄间隔FET预硅化物清洗过程中的方法
公开(公告)号：US07091128B2
公开(公告)日：2006-08-15
申请号：US11266855
申请日：2005-11-04
申请人： Atul C. Ajmera , Andres Bryant , Percy V. Gilbert , Michael A. Gribelyuk , Edward P. Maciejewski , Renee T. Mo , Shreesh Narasimha
发明人： Atul C. Ajmera , Andres Bryant , Percy V. Gilbert , Michael A. Gribelyuk , Edward P. Maciejewski , Renee T. Mo , Shreesh Narasimha
IPC分类号： H01L21/302
CPC分类号： H01L21/02063 , H01L21/31116 , H01L21/823835 , H01L21/823864 , H01L29/665 , H01L29/6653 , H01L29/6656 , H01L2924/0002 , H01L2924/00
摘要： A method for forming a CMOS device in a manner so as to avoid dielectric layer undercut during a pre-silicide cleaning step is described. During formation of CMOS device comprising a gate stack on a semiconductor substrate surface, the patterned gate stack including gate dielectric below a conductor with vertical sidewalls, a dielectric layer is formed thereover and over the substrate surfaces. Respective nitride spacer elements overlying the dielectric layer are formed at each vertical sidewall. The dielectric layer on the substrate surface is removed using an etch process such that a portion of the dielectric layer underlying each spacer remains. Then, a nitride layer is deposited over the entire sample (the gate stack, the spacer elements at each gate sidewall, and substrate surfaces) and subsequently removed by an etch process such that only a portion of said nitride film (the “plug”) remains. The plug seals and encapsulates the dielectric layer underlying each said spacer, thus preventing the dielectric material from being undercut during the subsequent pre-silicide clean process. By preventing undercut, this invention also prevents the etch-stop film (deposited prior to contact formation) from coming into contact with the gate oxide. Thus, the integration of thin-spacer transistor geometries, which are required for improving transistor drive current, is enabled.
摘要翻译：描述了在预硅化物清洁步骤期间以避免电介质层底切的方式形成CMOS器件的方法。在形成包括半导体衬底表面上的栅极堆叠的CMOS器件的情况下，图案化栅极堆叠包括在具有垂直侧壁的导体下方的栅极电介质，在衬底表面之上和之上形成介电层。在每个垂直侧壁处形成覆盖在电介质层上的各种氮化物间隔元件。使用蚀刻工艺去除衬底表面上的电介质层，使得保留每个间隔物下面的介电层的一部分。然后，在整个样品（栅极堆叠，每个栅极侧壁和衬底表面处的间隔元件）上沉积氮化物层，然后通过蚀刻工艺去除，使得仅一部分所述氮化物膜（“插塞”）遗迹。插头密封并封装每个所述间隔件下面的电介质层，从而防止在随后的硅化物前处理过程中电介质材料被切削。通过防止底切，本发明还防止蚀刻停止膜（在接触形成之前沉积）与栅极氧化物接触。因此，能够实现提高晶体管驱动电流所需的薄间隔晶体管几何形状的集成。

6. 发明授权

US09184301B2 Planar and nanowire field effect transistors 有权
标题翻译：平面和纳米线场效应晶体管
公开(公告)号：US09184301B2
公开(公告)日：2015-11-10
申请号：US13600598
申请日：2012-08-31
申请人： Sarunya Bangsaruntip , Guy M. Cohen , Shreesh Narasimha , Jeffrey W. Sleight
发明人： Sarunya Bangsaruntip , Guy M. Cohen , Shreesh Narasimha , Jeffrey W. Sleight
IPC分类号： H01L29/66 , H01L29/786 , B82Y10/00 , B82Y40/00 , H01L21/84 , H01L27/12 , H01L29/06 , H01L29/423
CPC分类号： H01L29/78696 , B82Y10/00 , B82Y40/00 , H01L21/84 , H01L27/1203 , H01L29/0665 , H01L29/0673 , H01L29/42392 , H01L29/66439 , H01L29/66469 , H01L29/66772
摘要： An integrated circuit includes a plurality of gate-all-around (GAA) nanowire field effect transistors (FETs), a plurality of omega-gate nanowire FETs, and a plurality of planar channel FETs, wherein the plurality of GAA FETs, the plurality of omega-gate nanowire FETs, and the plurality of planar channel FETs are disposed on a single wafer.
摘要翻译：集成电路包括多个栅极全能（GAA）纳米线场效应晶体管（FET），多个Ω-栅极纳米线FET和多个平面沟道FET，其中多个GAA FET，多个 ω-门纳米线FET，并且多个平面沟道FET设置在单个晶片上。

7. 发明申请

US20130221328A1 Pad-Less Gate-All Around Semiconductor Nanowire FETs On Bulk Semiconductor Wafers 有权
标题翻译：无衬底栅极 - 全周围半导体纳米线FET在散装半导体晶片上
公开(公告)号：US20130221328A1
公开(公告)日：2013-08-29
申请号：US13405732
申请日：2012-02-27
申请人： Jeffrey W. Sleight , Josephine B. Chang , Isaac Lauer , Shreesh Narasimha
发明人： Jeffrey W. Sleight , Josephine B. Chang , Isaac Lauer , Shreesh Narasimha
IPC分类号： H01L29/775 , H01L21/335
CPC分类号： H01L29/66477 , B82Y10/00 , B82Y40/00 , H01L29/0673 , H01L29/42392 , H01L29/66439 , H01L29/775 , H01L29/78696 , Y10S977/762
摘要： A method for forming a nanowire field effect transistor (FET) device, the method includes forming a suspended nanowire over a semiconductor substrate, forming a gate structure around a portion of the nanowire, forming a protective spacer adjacent to sidewalls of the gate and around portions of nanowire extending from the gate, removing exposed portions of the nanowire left unprotected by the spacer structure, and epitaxially growing a doped semiconductor material on exposed cross sections of the nanowire to form a source region and a drain region.
摘要翻译：一种用于形成纳米线场效应晶体管（FET）器件的方法，该方法包括在半导体衬底上形成悬浮的纳米线，在纳米线的一部分周围形成栅极结构，形成邻近栅极的侧壁和周围部分的保护隔离层的纳米线从栅极延伸，去除未被间隔物结构保护的纳米线的暴露部分，以及在纳米线的暴露的横截面上外延生长掺杂的半导体材料，以形成源极区域和漏极区域。

8. 发明申请

US20120319084A1 PLANAR AND NANOWIRE FIELD EFFECT TRANSISTORS 有权
标题翻译：平面和纳米级场效应晶体管
公开(公告)号：US20120319084A1
公开(公告)日：2012-12-20
申请号：US13600598
申请日：2012-08-31
申请人： Sarunya Bangsaruntip , Guy M. Cohen , Shreesh Narasimha , Jeffrey W. Sleight
发明人： Sarunya Bangsaruntip , Guy M. Cohen , Shreesh Narasimha , Jeffrey W. Sleight
IPC分类号： H01L27/088
CPC分类号： H01L29/78696 , B82Y10/00 , B82Y40/00 , H01L21/84 , H01L27/1203 , H01L29/0665 , H01L29/0673 , H01L29/42392 , H01L29/66439 , H01L29/66469 , H01L29/66772
摘要： An integrated circuit includes a plurality of gate-all-around (GAA) nanowire field effect transistors (FETs), a plurality of omega-gate nanowire FETs, and a plurality of planar channel FETs, wherein the plurality of GAA FETs, the plurality of omega-gate nanowire FETs, and the plurality of planar channel FETs are disposed on a single wafer.
摘要翻译：集成电路包括多个栅极全能（GAA）纳米线场效应晶体管（FET），多个Ω-栅极纳米线FET和多个平面沟道FET，其中多个GAA FET，多个 ω-门纳米线FET，并且多个平面沟道FET设置在单个晶片上。

9. 发明授权

US08232599B2 Bulk substrate FET integrated on CMOS SOI 有权
标题翻译：集成在CMOS SOI上的散装衬底FET
公开(公告)号：US08232599B2
公开(公告)日：2012-07-31
申请号：US12683456
申请日：2010-01-07
申请人： Anthony I. Chou , Arvind Kumar , Shreesh Narasimha , Ning Su , Huiling Shang
发明人： Anthony I. Chou , Arvind Kumar , Shreesh Narasimha , Ning Su , Huiling Shang
IPC分类号： H01L27/12 , H01L21/86
CPC分类号： H01L27/1207 , H01L21/84
摘要： An integrated circuit is provided that integrates an bulk FET and an SOI FET on the same chip, where the bulk FET includes a gate conductor over a gate oxide formed over a bulk substrate, where the gate dielectric of the bulk FET has the same thickness and is substantially coplanar with the buried insulating layer of the SOI FET. In a preferred embodiment, the bulk FET is formed from an SOI wafer by forming bulk contact trenches through the SOI layer and the buried insulating layer of the SOI wafer adjacent an active region of the SOI layer in a designated bulk device region. The active region of the SOI layer adjacent the bulk contact trenches forms the gate conductor of the bulk FET which overlies a portion of the underlying buried insulating layer, which forms the gate dielectric of the bulk FET.
摘要翻译：提供了一种集成电路，其将同一芯片上的体FET和SOI FET集成在一起，其中，本体FET包括在大块衬底上形成的栅极氧化物上的栅极导体，其中本体FET的栅极电介质具有相同的厚度，与SOI FET的掩埋绝缘层基本共面。在优选实施例中，通过在指定的大容量器件区域中与SOI层的有源区相邻的SOI层和SOI晶片的掩埋绝缘层形成体接触沟槽，从SOI晶片形成本体FET。邻近体接触沟槽的SOI层的有源区域形成体FET的栅极导体，其覆盖形成本体FET的栅极电介质的下层掩埋绝缘层的一部分。

10. 发明申请

US20120187492A1 BULK SUBSTRATE FET INTEGRATED ON CMOS SOI 有权
标题翻译：集成在CMOS SOI上的基极FET
公开(公告)号：US20120187492A1
公开(公告)日：2012-07-26
申请号：US13425681
申请日：2012-03-21
申请人： Anthony I. Chou , Arvind Kumar , Shreesh Narasimha , Ning Su , Huiling Shang
发明人： Anthony I. Chou , Arvind Kumar , Shreesh Narasimha , Ning Su , Huiling Shang
IPC分类号： H01L27/088
CPC分类号： H01L27/1207 , H01L21/84
摘要： An integrated circuit is provided that integrates an bulk FET and an SOI FET on the same chip, where the bulk FET includes a gate conductor over a gate oxide formed over a bulk substrate, where the gate dielectric of the bulk FET has the same thickness and is substantially coplanar with the buried insulating layer of the SOI FET. In a preferred embodiment, the bulk FET is formed from an SOI wafer by forming bulk contact trenches through the SOI layer and the buried insulating layer of the SOI wafer adjacent an active region of the SOI layer in a designated bulk device region. The active region of the SOI layer adjacent the bulk contact trenches forms the gate conductor of the bulk FET which overlies a portion of the underlying buried insulating layer, which forms the gate dielectric of the bulk FET.
摘要翻译：提供了一种集成电路，其将同一芯片上的体FET和SOI FET集成在一起，其中，本体FET包括在大块衬底上形成的栅极氧化物上的栅极导体，其中本体FET的栅极电介质具有相同的厚度，与SOI FET的掩埋绝缘层基本共面。在优选实施例中，通过在指定的大容量器件区域中与SOI层的有源区相邻的SOI层和SOI晶片的掩埋绝缘层形成体接触沟槽，从SOI晶片形成本体FET。邻近体接触沟槽的SOI层的有源区域形成体FET的栅极导体，其覆盖形成本体FET的栅极电介质的下层掩埋绝缘层的一部分。

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