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1. 发明申请

US20090221150A1 ETCH RATE AND CRITICAL DIMENSION UNIFORMITY BY SELECTION OF FOCUS RING MATERIAL 审中-公开
标题翻译：通过选择聚焦材料的蚀刻速率和关键尺寸均匀性
公开(公告)号：US20090221150A1
公开(公告)日：2009-09-03
申请号：US12395465
申请日：2009-02-27
申请人： Edward P. Hammond, IV , Jing Zou , Rodolfo P. Belen , Meihua Shen , Nicolas Gani , Andrew Nguyen , David Palagashvili , Michael D. Willwerth
发明人： Edward P. Hammond, IV , Jing Zou , Rodolfo P. Belen , Meihua Shen , Nicolas Gani , Andrew Nguyen , David Palagashvili , Michael D. Willwerth
IPC分类号： H01L21/3065 , C23F1/08
CPC分类号： H01J37/32642 , H01J37/321 , H01J37/3244 , H01J37/32623 , H01J2237/334 , H01L21/67069 , H01L21/68735
摘要： A method and apparatus are provided for plasma etching a substrate in a processing chamber. A focus ring assembly circumscribes a substrate support, providing uniform processing conditions near the edge of the substrate. The focus ring assembly comprises two rings, a first ring and a second ring, the first ring comprising quartz, and the second ring comprising monocrystalline silicon, silicon carbide, silicon nitride, silicon oxycarbide, silicon oxynitride, or combinations thereof. The second ring is disposed above the first ring near the edge of the substrate, and creates a uniform electric field and gas composition above the edge of the substrate that results in uniform etching across the substrate surface.
摘要翻译：提供了一种用于等离子体蚀刻处理室中的衬底的方法和装置。聚焦环组件围绕衬底支撑件，在衬底的边缘附近提供均匀的加工条件。聚焦环组件包括两个环，第一环和第二环，第一环包括石英，第二环包括单晶硅，碳化硅，氮化硅，碳氧化硅，氮氧化硅或其组合。第二环设置在基板边缘附近的第一环上方，并且在衬底的边缘上方产生均匀的电场和气体组成，导致穿过衬底表面的均匀蚀刻。

2. 发明申请

US20090221149A1 MULTIPLE PORT GAS INJECTION SYSTEM UTILIZED IN A SEMICONDUCTOR PROCESSING SYSTEM 审中-公开
标题翻译：在半导体处理系统中使用的多个端口气体注入系统
公开(公告)号：US20090221149A1
公开(公告)日：2009-09-03
申请号：US12039262
申请日：2008-02-28
申请人： Edward P. Hammond, IV , Rodolfo P. Belen , Nicolas Gani , Jing Zou , Meihua Shen , Michael D. Willwerth , David Palagashvili
发明人： Edward P. Hammond, IV , Rodolfo P. Belen , Nicolas Gani , Jing Zou , Meihua Shen , Michael D. Willwerth , David Palagashvili
IPC分类号： H01L21/306
CPC分类号： H01J37/32449 , H01J37/3244
摘要： An apparatus having a multiple gas injection port system for providing a high uniform etching rate across the substrate is provided. In one embodiment, the apparatus includes a nozzle in the semiconductor processing apparatus having a hollow cylindrical body having a first outer diameter defining a hollow cylindrical sleeve and a second outer diameter defining a tip, a longitudinal passage formed longitudinally through the body of the hollow cylindrical sleeve and at least partially extending to the tip, and a lateral passage formed in the tip coupled to the longitudinal passage, the lateral passage extending outward from the longitudinal passage having an opening formed on an outer surface of the tip.
摘要翻译：提供了一种具有多个气体注入端口系统的设备，用于在衬底上提供高均匀的蚀刻速率。在一个实施例中，该设备包括在半导体处理设备中的喷嘴，其具有中空圆柱体，其具有限定中空圆柱形套筒的第一外径和限定尖端的第二外径，纵向通道纵向穿过中空圆柱体并且至少部分地延伸到尖端，以及形成在连接到纵向通道的尖端中的侧向通道，从纵向通道向外延伸的侧向通道具有形成在尖端的外表面上的开口。

3. 发明申请

US20090004870A1 METHODS FOR HIGH TEMPERATURE ETCHING A HIGH-K MATERIAL GATE STRUCTURE 失效
标题翻译：高温蚀刻高K材料门结构的方法
公开(公告)号：US20090004870A1
公开(公告)日：2009-01-01
申请号：US12146303
申请日：2008-06-25
申请人： Wei Liu , Eiichi Matsusue , Meihua Shen , Shashank Deshmukh , Anh-Kiet Quang Phan , David Palagashvili , Michael D. Willwerth , Jong I. Shin , Barrett Finch , Yohei Kawase
发明人： Wei Liu , Eiichi Matsusue , Meihua Shen , Shashank Deshmukh , Anh-Kiet Quang Phan , David Palagashvili , Michael D. Willwerth , Jong I. Shin , Barrett Finch , Yohei Kawase
IPC分类号： H01L21/3065
CPC分类号： H01L21/3065 , H01L21/28282 , H01L21/31116 , H01L21/31122 , H01L21/32137
摘要： Methods for etching high-k material at high temperatures are provided. In one embodiment, a method etching high-k material on a substrate may include providing a substrate having a high-k material layer disposed thereon into an etch chamber, forming a plasma from an etching gas mixture including at least a halogen containing gas into the etch chamber, maintaining a temperature of an interior surface of the etch chamber in excess of about 100 degree Celsius while etching the high-k material layer in the presence of the plasma, and maintaining a substrate temperature between about 100 degree Celsius and about 250 degrees Celsius while etching the high-k material layer in the presence of the plasma.
摘要翻译：提供了在高温下蚀刻高k材料的方法。在一个实施例中，在衬底上蚀刻高k材料的方法可以包括提供其上设置有高k材料层的衬底到蚀刻室中，从包括至少含卤素气体的蚀刻气体混合物形成等离子体到蚀刻室，在蚀刻室的内部表面的温度保持超过约100摄氏度，同时在存在等离子体的同时蚀刻高k材料层，并将衬底温度保持在约100摄氏度至约250度之间摄氏度，同时在存在等离子体的同时蚀刻高k材料层。

4. 发明授权

US08501626B2 Methods for high temperature etching a high-K material gate structure 失效
标题翻译：高K蚀刻高K材料栅结构的方法
公开(公告)号：US08501626B2
公开(公告)日：2013-08-06
申请号：US12146303
申请日：2008-06-25
申请人： Wei Liu , Eiichi Matsusue , Meihua Shen , Shashank Deshmukh , Anh-Kiet Quang Phan , David Palagashvili , Michael D. Willwerth , Jong I. Shin , Barrett Finch , Yohei Kawase
发明人： Wei Liu , Eiichi Matsusue , Meihua Shen , Shashank Deshmukh , Anh-Kiet Quang Phan , David Palagashvili , Michael D. Willwerth , Jong I. Shin , Barrett Finch , Yohei Kawase
IPC分类号： H01L21/302 , H01L21/461 , C03C15/00 , C03C25/68
CPC分类号： H01L21/3065 , H01L21/28282 , H01L21/31116 , H01L21/31122 , H01L21/32137
摘要： Methods for etching high-k material at high temperatures are provided. In one embodiment, a method etching high-k material on a substrate may include providing a substrate having a high-k material layer disposed thereon into an etch chamber, forming a plasma from an etching gas mixture including at least a halogen containing gas into the etch chamber, maintaining a temperature of an interior surface of the etch chamber in excess of about 100 degree Celsius while etching the high-k material layer in the presence of the plasma, and maintaining a substrate temperature between about 100 degree Celsius and about 250 degrees Celsius while etching the high-k material layer in the presence of the plasma.
摘要翻译：提供了在高温下蚀刻高k材料的方法。在一个实施例中，在衬底上蚀刻高k材料的方法可以包括提供其上设置有高k材料层的衬底到蚀刻室中，从包括至少含卤素气体的蚀刻气体混合物形成等离子体到蚀刻室，在蚀刻室的内部表面的温度保持超过约100摄氏度，同时在存在等离子体的同时蚀刻高k材料层，并将衬底温度保持在约100摄氏度至约250度之间摄氏度，同时在存在等离子体的同时蚀刻高k材料层。

5. 发明申请

US20130087174A1 METHODS FOR IN-SITU CHAMBER CLEAN UTILIZED IN AN ETCHING PROCESSING CHAMBER 有权
标题翻译：在蚀刻加工室中使用的现场室清洁方法
公开(公告)号：US20130087174A1
公开(公告)日：2013-04-11
申请号：US13614365
申请日：2012-09-13
申请人： Noel Sun , Meihua Shen , Nicolas Gani , Chung Nang Liu , Radhika C. Mani
发明人： Noel Sun , Meihua Shen , Nicolas Gani , Chung Nang Liu , Radhika C. Mani
IPC分类号： B08B5/00
CPC分类号： B08B5/00 , B08B7/0035 , C23C16/4405 , H01J37/32449 , H01J37/32862 , Y10S438/905
摘要： Embodiments of the invention include methods for in-situ chamber dry cleaning a plasma processing chamber utilized for gate structure fabrication process in semiconductor devices. In one embodiment, a method for in-situ chamber dry clean includes supplying a first cleaning gas including at least a boron containing gas into a processing chamber in absence of a substrate disposed therein, supplying a second cleaning gas including at least a halogen containing gas into the processing chamber in absence of the substrate, and supplying a third cleaning gas including at least an oxygen containing gas into the processing chamber in absence of the substrate.
摘要翻译：本发明的实施例包括用于半导体器件中用于栅极结构制造工艺的等离子体处理室的原位室干洗的方法。在一个实施例中，一种用于原位室干洗的方法包括在不存在设置在其中的基板的情况下将包括至少含硼气体的第一清洁气体供应到处理室中，提供至少包含含卤素气体的第二清洁气体在没有基板的情况下进入处理室，并且在没有基板的情况下将至少包含含氧气体的第三清洁气体供应到处理室中。

6. 发明授权

US06599437B2 Method of etching organic antireflection coating (ARC) layers 失效
标题翻译：蚀刻有机抗反射涂层（ARC）层的方法
公开(公告)号：US06599437B2
公开(公告)日：2003-07-29
申请号：US09813392
申请日：2001-03-20
申请人： Oranna Yauw , Meihua Shen , Nicolas Gani , Jeffrey D. Chinn
发明人： Oranna Yauw , Meihua Shen , Nicolas Gani , Jeffrey D. Chinn
IPC分类号： H01L213213
CPC分类号： H01L21/0276 , H01L21/31138
摘要： A two-step method of etching an organic coating layer, in particular, an organic antireflection coating (ARC) layer, is disclosed. During the main etch step, the organic coating layer is etched using a plasma generated from a first source gas which includes a fluorocarbon and a non-carbon-containing, halogen-comprising gas. Etching is performed using a first substrate bias power. During the overetch step, residual organic coating material remaining after the main etch step is removed by exposing the substrate to a plasma generated from a second source gas which includes a chlorine-containing gas and an oxygen-containing gas, and which does not include a polymer-forming gas. The overetch step is performed using a second substrate bias power which is less than the first substrate bias power. The first source gas and first substrate bias power provide a higher etch rate in dense feature areas than in isolated feature areas during the main etch step, whereas the second source gas and second substrate bias power provide a higher etch rate in isolated feature areas than in dense feature areas during the overetch step, resulting in an overall balancing effect.
摘要翻译：公开了蚀刻有机涂层，特别是有机抗反射涂层（ARC）层的两步法。在主蚀刻步骤期间，使用由包括碳氟化合物和非含碳卤素气体的第一源气体产生的等离子体蚀刻有机涂层。使用第一衬底偏置功率进行蚀刻。在过蚀刻步骤期间，通过将衬底暴露于由包含含氯气体和含氧气体的第二源气体产生的等离子体而将主蚀刻步骤后剩余的残留有机涂层材料除去，并且不包括聚合物形成气体。使用小于第一衬底偏置功率的第二衬底偏置功率来执行过蚀刻步骤。在主蚀刻步骤期间，第一源气体和第一衬底偏置功率在致密特征区域中提供比在隔离特征区域中更高的蚀刻速率，而第二源气体和第二衬底偏置功率在隔离特征区域中提供比在在疏浚过程中密集的特征区域，导致整体平衡效果。

7. 发明授权

US09533332B2 Methods for in-situ chamber clean utilized in an etching processing chamber 有权
标题翻译：在蚀刻处理室中利用原位室清洁的方法
公开(公告)号：US09533332B2
公开(公告)日：2017-01-03
申请号：US13614365
申请日：2012-09-13
申请人： Noel Sun , Meihua Shen , Nicolas Gani , Chung Nang Liu , Radhika C. Mani
发明人： Noel Sun , Meihua Shen , Nicolas Gani , Chung Nang Liu , Radhika C. Mani
IPC分类号： B08B5/00 , B08B7/00 , B08B9/08 , C23C16/44 , H01J37/32
CPC分类号： B08B5/00 , B08B7/0035 , C23C16/4405 , H01J37/32449 , H01J37/32862 , Y10S438/905
摘要： Embodiments of the invention include methods for in-situ chamber dry cleaning a plasma processing chamber utilized for gate structure fabrication process in semiconductor devices. In one embodiment, a method for in-situ chamber dry clean includes supplying a first cleaning gas including at least a boron containing gas into a processing chamber in absence of a substrate disposed therein, supplying a second cleaning gas including at least a halogen containing gas into the processing chamber in absence of the substrate, and supplying a third cleaning gas including at least an oxygen containing gas into the processing chamber in absence of the substrate.
摘要翻译：本发明的实施例包括用于半导体器件中用于栅极结构制造工艺的等离子体处理室的原位室干洗的方法。在一个实施例中，一种用于原位室干洗的方法包括在不存在设置在其中的基板的情况下将包括至少含硼气体的第一清洁气体供应到处理室中，提供至少包含含卤素气体的第二清洁气体在没有基板的情况下进入处理室，并且在没有基板的情况下将至少包含含氧气体的第三清洁气体供应到处理室中。

8. 发明申请

US20100210112A1 METHOD FOR FABRICATING A SEMICONDUCTOR DEVICE HAVING A LANTHANUM-FAMILY-BASED OXIDE LAYER 失效
标题翻译：用于制备具有基于民族的氧化物层的半导体器件的方法
公开(公告)号：US20100210112A1
公开(公告)日：2010-08-19
申请号：US12371085
申请日：2009-02-13
申请人： Meihua Shen , Noel Sun , Nicolas Gani , Han-Hsiang Chen , Eric Pei , Weimin Zeng , Thorsten B. Lill , Uday Mitra , Ellie Y. Yieh
发明人： Meihua Shen , Noel Sun , Nicolas Gani , Han-Hsiang Chen , Eric Pei , Weimin Zeng , Thorsten B. Lill , Uday Mitra , Ellie Y. Yieh
IPC分类号： H01L21/3065
CPC分类号： H01L21/31122 , H01L21/28123 , H01L21/28167 , H01L21/31105 , H01L21/31111 , H01L21/32139 , H01L29/4966 , H01L29/513 , H01L29/517
摘要： Methods for fabricating a semiconductor device having a lanthanum-family-based oxide layer are described. A gate stack having a lanthanum-family-based oxide layer is provided above a substrate. At least a portion of the lanthanum-family-based oxide layer is modified to form a lanthanum-family-based halide portion. The lanthanum-family-based halide portion is removed with a water vapor treatment.
摘要翻译：描述了制造具有镧族氧化物层的半导体器件的方法。具有镧族氧化物层的栅极叠层设置在基板的上方。镧族氧化物层的至少一部分被改性以形成镧族卤化物部分。用水蒸气处理除去镧族卤化物部分。

9. 发明申请

US20070249182A1 ETCHING OF SiO2 WITH HIGH SELECTIVITY TO Si3N4 AND ETCHING METAL OXIDES WITH HIGH SELECTIVITY TO SiO2 AT ELEVATED TEMPERATURES WITH BCl3 BASED ETCH CHEMISTRIES 有权
标题翻译：对具有高选择性的Si 3 N 4的SiO 2和具有高选择性的金属氧化物的蚀刻在基于BCl3的蚀刻化学的高温下
公开(公告)号：US20070249182A1
公开(公告)日：2007-10-25
申请号：US11736562
申请日：2007-04-17
申请人： Radhika Mani , Nicolas Gani , Wei Liu , Meihua Shen , Shashank C. Deshmukh
发明人： Radhika Mani , Nicolas Gani , Wei Liu , Meihua Shen , Shashank C. Deshmukh
IPC分类号： H01L21/302 , H01L21/31
CPC分类号： H01L21/31116 , H01L21/31122 , H01L29/513 , H01L29/517 , H01L29/518
摘要： Wafers having a high K dielectric layer and an oxide or nitride containing layer are etched in an inductively coupled plasma processing chamber by applying a source power to generate an inductively coupled plasma, introducing into the chamber a gas including BCl3, setting the temperature of the wafer to be between 100° C. and 350° C., and etching the wafer with a selectivity of high K dielectric to oxide or nitride greater than 10:1. Wafers having an oxide layer and a nitride layer are etched in a reactive ion etch processing chamber by applying a bias power to the wafer, introducing into the chamber a gas including BCl3, setting the temperature of the wafer to be between 20° C. and 200° C., and etching the wafer with an oxide to nitride selectivity greater than 10:1. Wafers having an oxide layer and a nitride layer are etched in a an inductively coupled plasma processing chamber by applying a bias power to the wafer, applying a source power to generate an inductively coupled plasma, introducing into the chamber a gas including BCl3, setting the temperature of the wafer to be between 20° C. and 200° C., and etching the wafer with an oxide to nitride selectivity greater than 10:1.
摘要翻译：具有高K电介质层和含氧化物或氮化物的层的晶片在电感耦合等离子体处理室中被蚀刻，通过施加源功率以产生电感耦合等离子体，将包含BCl 3 >，将晶片的温度设置在100℃和350℃之间，并且以大于10:1的氧化物或氮化物的高K电介质的选择性蚀刻晶片。具有氧化物层和氮化物层的晶片通过向晶片施加偏置功率而在反应离子蚀刻处理室中进行蚀刻，将包含BCl 3 3的气体引入室中，设定晶片的温度在20℃和200℃之间，并且以大于10:1的氧化物至氮化物选择性蚀刻晶片。在电感耦合等离子体处理室中蚀刻具有氧化物层和氮化物层的晶片，通过向晶片施加偏置功率，施加源电力以产生电感耦合等离子体，将包括BCI 3，将晶片的温度设定在20℃至200℃之间，并以大于10:1的氧化物至氮化物选择性蚀刻晶片。

10. 发明授权

US06933243B2 High selectivity and residue free process for metal on thin dielectric gate etch application 失效
标题翻译：在薄介质栅极蚀刻应用上金属的高选择性和无残留的工艺
公开(公告)号：US06933243B2
公开(公告)日：2005-08-23
申请号：US10279320
申请日：2002-10-23
申请人： Meihua Shen , Yan Du , Nicolas Gani , Oranna Yauw , Hakeem M. Oluseyi
发明人： Meihua Shen , Yan Du , Nicolas Gani , Oranna Yauw , Hakeem M. Oluseyi
IPC分类号： H01L21/28 , H01L21/3213 , H01L29/49 , H01L21/302
CPC分类号： H01L21/28088 , H01L21/32136 , H01L29/4966
摘要： Methods for etching electrodes formed directly on gate dielectrics are provided. In one aspect, an etch process is provided which includes a main etch step, a soft landing step, and an over etch step. In another aspect, a method is described which includes performing a main etch having good etch rate uniformity and good profile uniformity, performing a soft landing step in which a metal/metal barrier interface can be determined, and performing an over etch step to selectively remove the metal barrier without negatively affecting the dielectric. In another aspect, a method is provided which includes a first non-selective etch chemistry for bulk removal of electrode material, a second intermediate selective etch chemistry with end point capability, and then a selective etch chemistry to stop on the gate dielectric.
摘要翻译：提供了直接形成在栅极电介质上的蚀刻电极的方法。在一个方面，提供了一种蚀刻工艺，其包括主蚀刻步骤，软着色步骤和过蚀刻步骤。在另一方面，描述了一种方法，其包括执行具有良好蚀刻速率均匀性和良好轮廓均匀性的主蚀刻，执行软着色步骤，其中可以确定金属/金属屏障界面，以及执行过蚀刻步骤以选择性地去除金属屏障，而不会对电介质产生负面影响。在另一方面，提供了一种方法，其包括用于大量去除电极材料的第一非选择性蚀刻化学品，具有端点能力的第二中间选择性蚀刻化学品，然后选择蚀刻化学物质停止在栅极电介质上。

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