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1. 发明授权

US5759427A Method and apparatus for polishing metal surfaces 失效
标题翻译：抛光金属表面的方法和设备
公开(公告)号：US5759427A
公开(公告)日：1998-06-02
申请号：US704193
申请日：1996-08-28
申请人： Edward Cibulsky , Gerald Andrew Kiballa , Voya Rista Markovich , Gary Leigh Newman , John Francis Prikazsky , Michael Wozniak
发明人： Edward Cibulsky , Gerald Andrew Kiballa , Voya Rista Markovich , Gary Leigh Newman , John Francis Prikazsky , Michael Wozniak
IPC分类号： B24B7/06 , B24B37/04 , B24B41/047 , C23F1/08 , H05K3/06 , H05K3/26 , C23F1/02 , C23F1/44
CPC分类号： B24B37/04 , B24B41/047 , B24B7/06 , C23F1/08 , H05K3/068 , H05K3/26 , H05K2203/025 , H05K2203/0346 , H05K2203/0353 , H05K2203/1509
摘要： A technique for chemically planarizing an exposed surface of metal on a substrate to a pre-determined thickness is provided. The substrate has an exposed metal surface such as copper circuitry on a dielectric substrate which is to be planarized. Typically, this will be circuitization extending above a photoresist layer. A planarizing head is rotated against the substrate, with the planarizing head in contact with the metal surface on the substrate. A chemical etchant, essentially free of abrasive material, is continuously supplied to the interface between the metal surface and the planarizing head. The planarizing continues until a predetermined thickness of the metal has been reached. In circuit board manufacturing, this will form a surface co-planar with the photoresist. In some instances where significant height reduction is required, thus requiring significant metal removal, several passes of the substrate may be required or a device with multiple heads may be used. On all but the last pass or last head, the planarizing head may include a film of polyester impregnated with very fine grit, such as 15.mu. or less silicon carbide (SiC). However, on the final pass or head, a relatively hard surface roll, e.g., rubber, free of added grit, is used to ensure a planar surface free of gouges.
摘要翻译：提供了一种用于将基板上的金属的暴露表面化学平坦化至预定厚度的技术。衬底具有暴露的金属表面，例如待平坦化的电介质衬底上的铜电路。通常，这将是在光致抗蚀剂层之上延伸的电路。平面化头相对于衬底旋转，平坦化头与衬底上的金属表面接触。基本上不含研磨材料的化学蚀刻剂被连续供应到金属表面和平坦化头部之间的界面。平面化继续，直到达到预定厚度的金属。在电路板制造中，这将形成与光致抗蚀剂共面的表面。在需要显着降低高度的一些情况下，因此需要显着的金属去除，可能需要多次通过基底，或者可以使用具有多个头部的装置。除了最后一次或最后一个头部之外，平坦化头可以包括浸渍有非常细的砂砾的聚酯薄膜，例如15微米或更少的碳化硅（SiC）。然而，在最后的通行或头部，使用相对硬的表面辊，例如没有添加砂砾的橡胶，以确保没有气刨的平面。

2. 发明授权

US5893983A Technique for removing defects from a layer of metal 失效
标题翻译：从金属层去除缺陷的技术
公开(公告)号：US5893983A
公开(公告)日：1999-04-13
申请号：US758272
申请日：1996-11-19
申请人： John Joseph Konrad , Voya Rista Markovich , George Frederick Reel , Jose Antonio Rios , Timothy Leroy Wells , Michael Wozniak
发明人： John Joseph Konrad , Voya Rista Markovich , George Frederick Reel , Jose Antonio Rios , Timothy Leroy Wells , Michael Wozniak
IPC分类号： B24B7/06 , B24B37/04 , B24B41/047 , C23F1/08 , H05K3/06 , H05K3/26 , C23F1/02 , C23F1/44
CPC分类号： C23F1/08 , B24B37/04 , B24B41/047 , B24B7/06 , H05K3/068 , H05K3/26 , H05K2203/025 , H05K2203/0346 , H05K2203/0353 , H05K2203/1509
摘要： A technique for polishing an exposed surface of metal on a substrate to remove defects from mechanical working of metals, such as burrs and pigtails resulting from drilling, and defects from plating, such as nodules and depressions, is provided. The substrate has an exposed metal surface such as copper thereon which is to be treated to remove defects. A planarizing or polishing head, preferably a rotating roller, is provided which is continuously rotating with respect to the substrate, with the head in contact with the metal surface on the substrate. A chemical etchant, essentially free of abrasive material, is continuously supplied to the interface between the metal surface and the head. The treating and polishing continues until the defects have been removed or reduced to an acceptable value. In some instances where significant height reduction is required, thus requiring significant metal removal, several passes of the substrate may be required or a device with multiple heads may be used. The polishing head preferably includes a film having a layer of very fine grit embedded therein, such as 5.mu.-15.mu. silicon carbide (SiC).
摘要翻译：提供了用于抛光基板上的金属暴露表面以去除金属机械加工的缺陷的技术，例如钻孔引起的毛刺和辫子以及电镀缺陷，例如结节和凹陷。基板具有暴露的金属表面，例如铜，其被处理以去除缺陷。提供平面化或抛光头，优选为旋转辊，其相对于衬底连续旋转，头部与衬底上的金属表面接触。基本上不含研磨材料的化学蚀刻剂被连续供应到金属表面和头部之间的界面。继续进行处理和抛光，直到缺陷被去除或降低到可接受的值。在需要显着降低高度的一些情况下，因此需要显着的金属去除，可能需要多次通过基底，或者可以使用具有多个头部的装置。抛光头优选包括具有嵌入其中的非常细的砂粒层的膜，例如5-15微米的碳化硅（SiC）。

3. 发明授权

US06547974B1 Method of producing fine-line circuit boards using chemical polishing 失效
标题翻译：使用化学抛光生产细线电路板的方法
公开(公告)号：US06547974B1
公开(公告)日：2003-04-15
申请号：US08495277
申请日：1995-06-27
申请人： Stanley Michael Albrechta , Christina Marie Boyko , Kathleen Lorraine Covert , Natalie Barbara Feilchenfeld , Voya Rista Markovich , William Earl Wilson , Michael Wozniak
发明人： Stanley Michael Albrechta , Christina Marie Boyko , Kathleen Lorraine Covert , Natalie Barbara Feilchenfeld , Voya Rista Markovich , William Earl Wilson , Michael Wozniak
IPC分类号： H01B1300
CPC分类号： H05K3/22 , H05K3/06 , H05K3/062 , H05K3/108 , H05K2203/025 , H05K2203/0346 , H05K2203/0353 , H05K2203/0392 , H05K2203/1476
摘要： A printed circuit board is produced by patterning a resist layer according to a circuit mask that defines desired circuit paths. The resist pattern layer is formed by removing the resist from the board in the desired circuit paths and a conductive material is plated onto the board in the resist voids defined by the circuit mask so that the height of the conductive material relative to the substrate equals or exceeds the height of the resist layer relative to the substrate. A low-reactive solution is applied over the conductive material and removes a surface portion of the conductive material. As the solution removes the conductive layer, it forms a film barrier and the solution composition changes, both of which substantially inhibits any further removal of the conductive material. Next, the film barrier is removed from the board allowing another film barrier to form stimulating the removal of further conductive material. The removal step is repeated until the conductive material is at a desired height relative to the height of the resist layer. The board is then finished using conventional circuit board fabrication techniques.
摘要翻译：通过根据限定所需电路路径的电路掩模图案化抗蚀剂层来制造印刷电路板。抗蚀剂图案层通过在所需的电路路径中从基板上去除抗蚀剂而形成，并且导电材料被电镀在由电路掩模限定的抗蚀剂空隙中的基板上，使得导电材料相对于基板的高度等于或等于超过抗蚀剂层相对于基底的高度。将低反应性溶液施加在导电材料上并除去导电材料的表面部分。当溶液去除导电层时，其形成膜阻挡层并且溶液组成发生变化，这两者基本上禁止任何进一步去除导电材料。接下来，从板上去除膜屏障，允许另一个膜屏障形成刺激去除另外的导电材料。重复去除步骤，直到导电材料相对于抗蚀剂层的高度处于期望的高度。然后使用常规电路板制造技术完成电路板。

4. 发明授权

US6093335A Method of surface finishes for eliminating surface irregularities and defects 失效
标题翻译：表面处理方法，用于消除表面不规则和缺陷
公开(公告)号：US6093335A
公开(公告)日：2000-07-25
申请号：US974210
申请日：1997-11-20
申请人： Ashwinkumar C. Bhatt , John Christopher Camp , Subahu Dhirubhai Desai , Voya Rista Markovich , Michael Wozniak
发明人： Ashwinkumar C. Bhatt , John Christopher Camp , Subahu Dhirubhai Desai , Voya Rista Markovich , Michael Wozniak
IPC分类号： B24B7/06 , B24B37/04 , B24B41/047 , C23F1/08 , H05K3/06 , H05K3/26 , B44C1/22
CPC分类号： B24B7/06 , B24B37/04 , B24B41/047 , C23F1/08 , H05K3/068 , H05K3/26 , H05K2203/025 , H05K2203/0346 , H05K2203/0353 , H05K2203/1509
摘要： A method for planarizing an exposed metal surface on a substrate is provided in which surface irregularities are eliminated. A photoresist layer is first removed from the substrate. Then a conformal planarizing head is placed in contact with the metal surface while chemical etchant essentially free of abrasives is supplied to an interface between the metal substrate and the planarizing head. The surface is then planarized until it is free of irregularties.
摘要翻译：提供了在基板上平坦化露出的金属表面的方法，其中消除了表面凹凸。首先从基底去除光致抗蚀剂层。然后将保形平面化头与金属表面接触，同时基本上没有磨料的化学蚀刻剂被提供给金属基底和平坦化头之间的界面。然后将表面平坦化，直到其没有不规则。

5. 发明授权

US06739048B2 Process of fabricating a circuitized structure 失效
标题翻译：制造电路化结构的工艺
公开(公告)号：US06739048B2
公开(公告)日：2004-05-25
申请号：US09491755
申请日：2000-01-27
申请人： Gerald Walter Jones , Ross William Keesler , Voya Rista Markovich , William John Rudik , James Warren Wilson , William Earl Wilson
发明人： Gerald Walter Jones , Ross William Keesler , Voya Rista Markovich , William John Rudik , James Warren Wilson , William Earl Wilson
IPC分类号： H01K310
CPC分类号： H05K3/388 , H01L21/4846 , H01L21/4857 , H05K3/0023 , H05K3/16 , H05K3/4602 , H05K2201/09536 , H05K2201/096 , H05K2203/1581 , Y10T29/49155 , Y10T29/49156 , Y10T29/49165
摘要： A process of fabricating a circuitized structure is provided. The process includes the steps of providing an organic substrate having circuitry thereon; applying a dielectric film on the organic substrate; forming microvias in the dielectric film; sputtering a metal seed layer on the dielectric film and the microvias; plating a metallic layer on the metal seed layer; and forming a circuit pattern thereon.
摘要翻译：提供了一种制造电路化结构的工艺。该方法包括提供其上具有电路的有机基底的步骤; 在有机基板上施加电介质膜; 在电介质膜中形成微孔; 在电介质膜和微孔上溅射金属种子层; 在金属籽晶层上镀金属层; 并在其上形成电路图案。

6. 发明授权

US6131279A Integrated manufacturing packaging process 失效
标题翻译：集成制造包装过程
公开(公告)号：US6131279A
公开(公告)日：2000-10-17
申请号：US5182
申请日：1998-01-08
申请人： Gerald Walter Jones , Ross William Keesler , Voya Rista Markovich , William John Rudik , James Warren Wilson , William Earl Wilson
发明人： Gerald Walter Jones , Ross William Keesler , Voya Rista Markovich , William John Rudik , James Warren Wilson , William Earl Wilson
IPC分类号： H01L21/48 , H05K3/00 , H05K3/16 , H05K3/38 , H05K3/46 , H01K3/10
CPC分类号： H05K3/388 , H01L21/4846 , H01L21/4857 , H05K3/4602 , H05K2201/09536 , H05K2201/096 , H05K2203/1581 , H05K3/0023 , H05K3/16 , Y10T29/49155 , Y10T29/49156 , Y10T29/49165
摘要： A process of fabricating a circuitized substrate is provided which comprising the steps of: providing an organic substrate having circuitry thereon; applying a dielectric film on the organic substrate; forming microvias in said dielectric film; sputtering a metal seed layer on the dielectric film and in said microvias; plating a metallic layer on the metal seed layer; and forming a circuit pattern thereon.
摘要翻译：提供一种制造电路化基板的工艺，其包括以下步骤：提供其上具有电路的有机基板; 在有机基板上施加电介质膜; 在所述介电膜中形成微孔; 在电介质膜上和所述微孔中溅射金属种子层; 在金属籽晶层上镀金属层; 并在其上形成电路图案。

7. 发明授权

US6114019A Circuit board assemblies having filled vias free from bleed-out 失效
标题翻译：电路板组件具有没有渗出的通孔
公开(公告)号：US6114019A
公开(公告)日：2000-09-05
申请号：US33456
申请日：1998-03-02
申请人： Anilkumar Chinuprasad Bhatt , Donald Herman Glatzel , Allen F. Moring , Voya Rista Markovich , Kostas Papathomas , David John Russell
发明人： Anilkumar Chinuprasad Bhatt , Donald Herman Glatzel , Allen F. Moring , Voya Rista Markovich , Kostas Papathomas , David John Russell
IPC分类号： H05K1/11 , H05K3/00 , H05K3/02 , H05K3/24 , H05K3/40 , H05K3/42 , H05K3/46 , B32B3/00
CPC分类号： H05K3/4652 , H05K1/113 , H05K3/4069 , H05K3/4602 , H01L2224/48091 , H01L2224/73204 , H01L2924/12044 , H05K2201/0347 , H05K2201/0355 , H05K2201/092 , H05K2201/0959 , H05K2203/0191 , H05K2203/025 , H05K2203/0278 , H05K2203/0338 , H05K2203/0554 , H05K3/0023 , H05K3/0094 , H05K3/025 , H05K3/246 , H05K3/429 , Y10S428/901 , Y10T29/49126 , Y10T29/4913 , Y10T29/49139 , Y10T29/49144 , Y10T29/49155 , Y10T29/49165 , Y10T428/24917 , Y10T428/24926 , Y10T428/24942 , Y10T428/249996
摘要： A circuit assembly that includes a circuitized substrate having a dielectric interior layer with a first surface and at least one hole therein. A filler material substantially fills the hole within the dielectric interior layer. A first wiring layer is positioned on the first surface of the dielectric interior layer, wherein the first wiring layer substantially covers the hole and assists in retaining the filler material within the hole in the dielectric interior layer. A first dielectric photoresist layer is positioned on the first wiring layer and on the first surface of the dielectric interior layer. The first dielectric photoresist layer also includes at least one hole therein. The filler material also substantially fills the hole within the first dielectric photoresist layer. A second wiring layer is positioned on the first dielectric photoresist layer and includes a plurality of conductive pads as part thereof. At least one external component can be electrically coupled to the conductive pads of the second wiring layer.
摘要翻译：一种电路组件，其包括具有电介质内层的电路化衬底，其具有第一表面和至少一个孔。填充材料基本上填充电介质内层内的孔。第一布线层位于电介质内层的第一表面上，其中第一布线层基本上覆盖孔，并有助于将填料保持在电介质内层的孔内。第一电介质光致抗蚀剂层定位在第一布线层上和电介质内层的第一表面上。第一电介质光致抗蚀剂层还包括至少一个孔。填充材料还基本上填充第一介电光致抗蚀剂层内的孔。第二布线层位于第一电介质光致抗蚀剂层上，并且包括多个导电焊盘作为其一部分。至少一个外部部件可以电耦合到第二布线层的导电焊盘。

8. 发明授权

US6106891A Via fill compositions for direct attach of devices and method for applying same 失效
标题翻译：用于直接附着装置的填充组合物和用于施加它们的方法
公开(公告)号：US6106891A
公开(公告)日：2000-08-22
申请号：US215992
申请日：1998-12-18
申请人： Joseph Duane Kulesza , Voya Rista Markovich , Kostas Papathomas , Joseph Gene Sabia
发明人： Joseph Duane Kulesza , Voya Rista Markovich , Kostas Papathomas , Joseph Gene Sabia
IPC分类号： B32B7/04 , C08G59/40 , C08G73/00 , C08L63/00 , C09D163/00 , H01B1/20 , H01B1/22 , H01B1/24 , H05K1/09 , H05K1/11 , H05K1/16 , H05K3/00 , H05K3/40 , H05K3/42
CPC分类号： H01B1/24 , B32B7/04 , H01B1/22 , H05K1/095 , H05K1/113 , H05K1/167 , H05K3/4053 , H05K3/4069 , H01L2224/16235 , H05K1/16 , H05K2201/0347 , H05K2201/09563 , H05K2201/10734 , H05K2203/0126 , H05K2203/0191 , H05K2203/0207 , H05K2203/0278 , H05K2203/0338 , H05K2203/0763 , H05K3/0023 , H05K3/0047 , H05K3/0094 , Y10S428/901 , Y10T29/49099 , Y10T29/49144 , Y10T29/49155 , Y10T29/49165 , Y10T428/24273 , Y10T428/24331 , Y10T428/24339 , Y10T428/24826 , Y10T428/24917 , Y10T428/24926 , Y10T428/25
摘要： The present invention permits solder joints to be made directly to via and through holes without the solder being wicked into the vias or through holes, by filling plated through holes with an epoxy or cyanate fill composition. When cured and overplated, the fill composition provides support for the solder joint and provides a flat solderable surface for the inter-connection. In certain embodiments, the cured fill compositions, offer a further advantage of being conductive. The invention also relates to several novel methods for filling through holes with such fill compositions, and to resistors located in through holes and vias.
摘要翻译：本发明允许焊接接头直接制成通孔和通孔，而不会通过用环氧树脂或氰酸盐填充组合物填充电镀通孔，焊料不会被弄脏到通孔或通孔中。当固化和过度镀覆时，填充组合物为焊接接头提供支撑，并为相互连接提供平坦的可焊接表面。在某些实施方案中，固化的填充组合物提供另外的导电性的优点。本发明还涉及用这种填充组合物填充通孔的几种新方法，以及位于通孔和通孔中的电阻器。

9. 发明授权

US5940729A Method of planarizing a curved substrate and resulting structure 失效
公开(公告)号：US5940729A
公开(公告)日：1999-08-17
申请号：US633984
申请日：1996-04-17
申请人： Francis Joseph Downes, Jr. , Stephen Joseph Fuerniss , Gary Ray Hill , Anthony Paul Ingraham , Voya Rista Markovich , Jaynal Abedin Molla
发明人： Francis Joseph Downes, Jr. , Stephen Joseph Fuerniss , Gary Ray Hill , Anthony Paul Ingraham , Voya Rista Markovich , Jaynal Abedin Molla
IPC分类号： H01L21/60 , H01L23/13 , H01L23/498 , H05K1/03 , H05K1/11 , H05K3/00 , H05K3/34 , H05K3/46 , H01L21/44
CPC分类号： H01L23/49833 , H01L23/13 , H01L24/16 , H01L24/81 , H01L24/83 , H01L24/90 , H01L2224/0401 , H01L2224/05557 , H01L2224/13099 , H01L2224/16225 , H01L2224/2919 , H01L2224/81052 , H01L2224/81191 , H01L2224/81385 , H01L2224/81801 , H01L2224/8319 , H01L2224/838 , H01L2924/01006 , H01L2924/01029 , H01L2924/01033 , H01L2924/01044 , H01L2924/01045 , H01L2924/01046 , H01L2924/01074 , H01L2924/01076 , H01L2924/01077 , H01L2924/01078 , H01L2924/014 , H01L2924/0665 , H01L2924/14 , H01L2924/15174 , H01L2924/15312 , H01L2924/15787 , H05K1/0306 , H05K1/112 , H05K3/0023 , H05K3/3436 , H05K3/4644
摘要： According to the present invention a technique for providing a planarized substrate with dendritic connections of solder balls, especially a multi-layer ceramic substrate is provided. In the case where the substrate has a raised central portion on the top surface on which are disposed top surface metallurgy pads, a layer of conformable photoimagable material is placed over the top surface.The photoimagable material is exposed and developed in a pattern corresponding to the pattern of the top surface metallurgy pads to form vias in the photoimagable material. Copper is plated in the vias in contact with the top surface metallurgy pads. The exposed surface of the photoimagable surface is then planarized, preferably by mechanical polishing to form a flat planar surface, with the ends of the vias exposed. Dendritic connector pads are then grown on the exposed ends of the vias to which solder ball connections of an I/C chip are releasably connected.

10. 发明授权

US5659256A Method and apparatus for testing integrated circuit chips 失效
公开(公告)号：US5659256A
公开(公告)日：1997-08-19
申请号：US601923
申请日：1996-02-15
申请人： Richard Gordon Charlton , George Charles Correia , Mark Andrew Couture , Gary Ray Hill , Kibby Barth Horsford , Anthony Paul Ingraham , Michael David Lowell , Voya Rista Markovich , Gordon Charles Osborne, Jr. , Mark Vincent Pierson
发明人： Richard Gordon Charlton , George Charles Correia , Mark Andrew Couture , Gary Ray Hill , Kibby Barth Horsford , Anthony Paul Ingraham , Michael David Lowell , Voya Rista Markovich , Gordon Charles Osborne, Jr. , Mark Vincent Pierson
IPC分类号： G01R1/04 , G01R1/073 , G01R31/28
CPC分类号： G01R1/0483 , G01R1/07307 , G01R31/2863 , G01R31/2886
摘要： A method and apparatus for testing semi-conductor chips is disclosed. The individual semiconductor chips have I/O contacts. The apparatus is provided with an interposer that has contacts corresponding to the contacts on the semiconductor chip. Both the chip and the interposer contacts can be any known type including metal ball, bumps, or tabs or may be provided with dendritic surfaces. The chip contacts are first brought into relative loose temporary contact with the contacts on the interposer and then a compressive force greater that 5 grams per chip contact is applied to the chip to force the chip contacts into good electrical contact with the interposer contacts. Testing of the chip is then performed. The tests may include heating of the chip as well as the application of signals to the chip contacts. After testing the chip is removed from the substrate.

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