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1. 发明授权

US07450415B2 Phase-change memory device 有权
标题翻译：相变存储器件
公开(公告)号：US07450415B2
公开(公告)日：2008-11-11
申请号：US11640956
申请日：2006-12-19
申请人： Du-eung Kim , Chang-soo Lee , Woo-yeong Cho , Beak-hyung Cho , Byung-gil Choi
发明人： Du-eung Kim , Chang-soo Lee , Woo-yeong Cho , Beak-hyung Cho , Byung-gil Choi
IPC分类号： G11C11/00
CPC分类号： G11C8/12 , G11C11/5678 , G11C13/0004 , G11C13/0023 , G11C2213/72 , G11C2213/79 , H01L27/2409 , H01L27/2463 , H01L45/06 , H01L45/1233 , H01L45/143 , H01L45/144 , H01L45/148
摘要： A phase-change memory device is provided. The phase-change memory device includes a phase-change memory cell array including a first memory block having a plurality of phase-change memory cells each connected between each of a plurality of bit lines and a first word line, a second memory block having a plurality of phase-change memory cells each connected between each of the plurality of bit lines and a second word line, and first and second pull-down transistors pulling-down each voltage level of the first and the second word lines and sharing a node and a row driver including a first and a second pull-up transistor pulling-up each voltage level of the first and the second word lines.
摘要翻译：提供了相变存储器件。相变存储器件包括相变存储器单元阵列，该相变存储单元阵列包括具有连接在多个位线和第一字线中的每一个之间的多个相变存储单元的第一存储器块，具有第多个相变存储单元，分别连接在多个位线和第二字线之间，第一和第二下拉晶体管下拉第一和第二字线的每个电压电平并共享一个节点;以及行驱动器，包括第一和第二上拉晶体管，其拉出第一和第二字线的每个电压电平。

2. 发明授权

US07881103B2 Phase-change memory device and method of fabricating the same 有权
标题翻译：相变存储器件及其制造方法
公开(公告)号：US07881103B2
公开(公告)日：2011-02-01
申请号：US12574783
申请日：2009-10-07
申请人： Du-eung Kim , Chang-soo Lee , Woo-yeong Cho , Byung-gil Choi
发明人： Du-eung Kim , Chang-soo Lee , Woo-yeong Cho , Byung-gil Choi
IPC分类号： G11C11/00
CPC分类号： G11C13/0004 , G11C2213/72 , H01L27/2409 , H01L27/2472 , H01L45/06 , H01L45/1233 , H01L45/143 , H01L45/144 , H01L45/1675 , Y10S977/754
摘要： A phase-change memory device includes a semiconductor substrate, a bit line and a word line arranged on the semiconductor substrate to intersect each other, and a phase-change material strip interposed between the bit line and the word line and extending lengthwise in a direction that is substantially parallel to at least a portion of the word line.
摘要翻译：相变存储器件包括半导体衬底，布置在半导体衬底上的位线和字线彼此相交的相变存储器件，以及插入位线和字线之间的相变材料带，并且沿相对方向其基本上平行于字线的至少一部分。

3. 发明申请

US20070086235A1 Phase-change memory device and method of fabricating the same 有权
标题翻译：相变存储器件及其制造方法
公开(公告)号：US20070086235A1
公开(公告)日：2007-04-19
申请号：US11529323
申请日：2006-09-29
申请人： Du-eung Kim , Chang--soo Lee , Woo-yeong Cho , Byung-gil Choi
发明人： Du-eung Kim , Chang--soo Lee , Woo-yeong Cho , Byung-gil Choi
IPC分类号： G11C11/00
CPC分类号： G11C13/0004 , G11C2213/72 , H01L27/2409 , H01L27/2472 , H01L45/06 , H01L45/1233 , H01L45/143 , H01L45/144 , H01L45/1675 , Y10S977/754
摘要： A phase-change memory device includes a semiconductor substrate, a bit line and a word line arranged on the semiconductor substrate to intersect each other, and a phase-change material strip interposed between the bit line and the word line and extending lengthwise in a direction that is substantially parallel to at least a portion of the word line.
摘要翻译：相变存储器件包括半导体衬底，布置在半导体衬底上的位线和字线彼此相交的相变存储器件，以及插入位线和字线之间的相变材料带，并且沿相对方向其基本上平行于字线的至少一部分。

4. 发明申请

US20100019217A1 PHASE-CHANGE MEMORY DEVICE AND METHOD OF FABRICATING THE SAME 有权
标题翻译：相变存储器件及其制造方法
公开(公告)号：US20100019217A1
公开(公告)日：2010-01-28
申请号：US12574783
申请日：2009-10-07
申请人： Du-eung Kim , Chang-soo Lee , Woo-yeong Cho , Byung-gil Choi
发明人： Du-eung Kim , Chang-soo Lee , Woo-yeong Cho , Byung-gil Choi
IPC分类号： H01L47/00 , H01L21/06
CPC分类号： G11C13/0004 , G11C2213/72 , H01L27/2409 , H01L27/2472 , H01L45/06 , H01L45/1233 , H01L45/143 , H01L45/144 , H01L45/1675 , Y10S977/754
摘要： A phase-change memory device includes a semiconductor substrate, a bit line and a word line arranged on the semiconductor substrate to intersect each other, and a phase-change material strip interposed between the bit line and the word line and extending lengthwise in a direction that is substantially parallel to at least a portion of the word line.
摘要翻译：相变存储器件包括半导体衬底，布置在半导体衬底上的位线和字线彼此相交的相变存储器件，以及插入位线和字线之间的相变材料带，并且沿相对方向其基本上平行于字线的至少一部分。

5. 发明授权

US07613037B2 Phase-change memory device and method of fabricating the same 有权
标题翻译：相变存储器件及其制造方法
公开(公告)号：US07613037B2
公开(公告)日：2009-11-03
申请号：US11529323
申请日：2006-09-29
申请人： Du-eung Kim , Chang-soo Lee , Woo-yeong Cho , Byung-gil Choi
发明人： Du-eung Kim , Chang-soo Lee , Woo-yeong Cho , Byung-gil Choi
IPC分类号： G11C11/00
CPC分类号： G11C13/0004 , G11C2213/72 , H01L27/2409 , H01L27/2472 , H01L45/06 , H01L45/1233 , H01L45/143 , H01L45/144 , H01L45/1675 , Y10S977/754
摘要： A phase-change memory device includes a semiconductor substrate, a bit line and a word line arranged on the semiconductor substrate to intersect each other, and a phase-change material strip interposed between the bit line and the word line and extending lengthwise in a direction that is substantially parallel to at least a portion of the word line.
摘要翻译：相变存储器件包括半导体衬底，布置在半导体衬底上的位线和字线彼此相交的相变存储器件，以及插入位线和字线之间的相变材料带，并且沿相对方向其基本上平行于字线的至少一部分。

6. 发明申请

US20070153616A1 Phase-change memory device 有权
标题翻译：相变存储器件
公开(公告)号：US20070153616A1
公开(公告)日：2007-07-05
申请号：US11640956
申请日：2006-12-19
申请人： Du-eung Kim , Chang-soo Lee , Woo-yeong Cho , Beak-hyung Cho , Byung-gil Choi
发明人： Du-eung Kim , Chang-soo Lee , Woo-yeong Cho , Beak-hyung Cho , Byung-gil Choi
IPC分类号： G11C11/00 , G11C8/00
CPC分类号： G11C8/12 , G11C11/5678 , G11C13/0004 , G11C13/0023 , G11C2213/72 , G11C2213/79 , H01L27/2409 , H01L27/2463 , H01L45/06 , H01L45/1233 , H01L45/143 , H01L45/144 , H01L45/148
摘要： A phase-change memory device is provided. The phase-change memory device includes a phase-change memory cell array including a first memory block having a plurality of phase-change memory cells each connected between each of a plurality of bit lines and a first word line, a second memory block having a plurality of phase-change memory cells each connected between each of the plurality of bit lines and a second word line, and first and second pull-down transistors pulling-down each voltage level of the first and the second word lines and sharing a node and a row driver including a first and a second pull-up transistor pulling-up each voltage level of the first and the second word lines.
摘要翻译：提供了相变存储器件。相变存储器件包括相变存储器单元阵列，该相变存储单元阵列包括具有连接在多个位线和第一字线中的每一个之间的多个相变存储单元的第一存储器块，具有第多个相变存储单元，分别连接在多个位线和第二字线之间，第一和第二下拉晶体管下拉第一和第二字线的每个电压电平并共享一个节点;以及行驱动器，包括第一和第二上拉晶体管，其拉出第一和第二字线的每个电压电平。

7. 发明申请

US20070159878A1 Phase change memory device 有权
标题翻译：相变存储器件
公开(公告)号：US20070159878A1
公开(公告)日：2007-07-12
申请号：US11648558
申请日：2007-01-03
申请人： Byung-gil Choi , Du-eung Kim , Woo-yeong Cho
发明人： Byung-gil Choi , Du-eung Kim , Woo-yeong Cho
IPC分类号： G11C5/06 , G11C11/00 , G11C8/00
CPC分类号： G11C7/18 , G11C8/12 , G11C13/0004 , G11C2213/72 , G11C2213/79
摘要： A phase change memory device includes a semiconductor substrate which includes a plurality of phase change memory cells, a plurality of local bit lines extending over the semiconductor substrate, each of the plurality of local bit lines being coupled to the plurality of phase change memory cells, and a plurality of global bit lines extending over the plurality of local bit lines, each of the plurality of global bit lines being selectively coupled to the plurality of local bit lines. The plurality of global bit lines are located at two or more different wiring line levels over the semiconductor substrate.
摘要翻译：相变存储器件包括：半导体衬底，其包括多个相变存储器单元;多个局部位线，其延伸在所述半导体衬底上;所述多个局部位线中的每一个耦合到所述多个相变存储器单元; 以及在所述多个局部位线上延伸的多个全局位线，所述多个全局位线中的每一条选择性地耦合到所述多个局部位线。多个全局位线位于半导体衬底上的两个或更多个不同的布线层上。

8. 发明授权

US07405965B2 Phase change memory device 有权
标题翻译：相变存储器件
公开(公告)号：US07405965B2
公开(公告)日：2008-07-29
申请号：US11648558
申请日：2007-01-03
申请人： Byung-gil Choi , Du-eung Kim , Woo-yeong Cho
发明人： Byung-gil Choi , Du-eung Kim , Woo-yeong Cho
IPC分类号： G11C11/22
CPC分类号： G11C7/18 , G11C8/12 , G11C13/0004 , G11C2213/72 , G11C2213/79
摘要： A phase change memory device includes a semiconductor substrate which includes a plurality of phase change memory cells, a plurality of local bit lines extending over the semiconductor substrate, each of the plurality of local bit lines being coupled to the plurality of phase change memory cells, and a plurality of global bit lines extending over the plurality of local bit lines, each of the plurality of global bit lines being selectively coupled to the plurality of local bit lines. The plurality of global bit lines are located at two or more different wiring line levels over the semiconductor substrate.
摘要翻译：相变存储器件包括：半导体衬底，其包括多个相变存储器单元;多个局部位线，其延伸在所述半导体衬底上;所述多个局部位线中的每一个耦合到所述多个相变存储器单元; 以及在所述多个局部位线上延伸的多个全局位线，所述多个全局位线中的每一条选择性地耦合到所述多个局部位线。多个全局位线位于半导体衬底上的两个或更多个不同的布线层上。

9. 发明授权

US07573766B2 Phase change random access memory and method of testing the same 有权
标题翻译：相变随机存取存储器和测试方法相同
公开(公告)号：US07573766B2
公开(公告)日：2009-08-11
申请号：US11898125
申请日：2007-09-10
申请人： Byung-gil Choi , Beak-hyung Cho , Du-eung Kim , Chang-han Choi , Yu-hwan Ro
发明人： Byung-gil Choi , Beak-hyung Cho , Du-eung Kim , Chang-han Choi , Yu-hwan Ro
IPC分类号： G11C29/00
CPC分类号： G11C13/0004 , G11C29/50 , G11C2029/1204 , G11C2029/5006
摘要： Provided is a method of testing a phase change random access memory (PRAM). The method may include providing a plurality of PRAM cells each coupled between each of a plurality of first lines and each of a plurality of second lines intersecting the first lines, selecting at least one of the plurality of first lines while deselecting the remaining first lines and the plurality of second lines, pre-charging the selected at least one of the plurality of first lines to a predetermined or given voltage level, and sensing a change in the voltage level of the selected first line while supplying a monitoring voltage to the selected first line.
摘要翻译：提供了一种测试相变随机存取存储器（PRAM）的方法。该方法可以包括提供多个PRAM单元，每个PRAM单元分别耦合在多个第一线中的每一条与多条第一线相交的多条第二线中的每条之间，同时选择多条第一条线中的至少一条，同时取消选择其余的第一条线，所述多个第二线路将所选择的所述多个第一线路中的至少一个预充电到预定或给定的电压电平，并且感测所选择的第一线路的电压电平的变化，同时向所选择的第一线路提供监视电压线。

10. 发明申请

US20070195591A1 Layout method of a semiconductor memory device 有权
标题翻译：半导体存储器件的布局方法
公开(公告)号：US20070195591A1
公开(公告)日：2007-08-23
申请号：US11790444
申请日：2007-04-25
申请人： Beak-hyung Cho , Du-eung Kim , Byung-gil Choi , Choong-keun Kwak
发明人： Beak-hyung Cho , Du-eung Kim , Byung-gil Choi , Choong-keun Kwak
IPC分类号： G11C5/06 , G11C5/02 , G11C11/00
CPC分类号： G11C7/18 , G11C5/025 , G11C13/0004
摘要： The layout method for a semiconductor device includes locating a plurality of first bit line selection circuits at a first side of a variable resistive memory cell block, and locating a plurality of second bit line selection circuits at a second side of the variable resistive memory cell block opposite the first side. The method further includes connecting the first bit line selection circuits with respective odd-numbered local bit lines of the variable resistive memory cell block, and connecting the second bit line selection circuits with respective even-numbered local bit lines of the variable resistive memory cell block. The method still further includes selectively connecting respective odd-numbered local bit lines to a global bit line using the first bit line selection circuits, and selectively connecting respective even-numbered local bit lines to the global bit line using the second bit line selection circuits.
摘要翻译：半导体器件的布局方法包括在可变电阻存储器单元块的第一侧定位多个第一位线选择电路，并且将多个第二位线选择电路定位在可变电阻存储器单元块的第二侧第一面相反该方法还包括将第一位线选择电路与可变电阻存储单元块的相应奇数本地位线连接，并将第二位线选择电路与可变电阻存储单元块的各个偶数本地位线连接。该方法还包括使用第一位线选择电路选择性地将相应的奇数本地位线连接到全局位线，并且使用第二位线选择电路选择性地将各偶数本地位线连接到全局位线。

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