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1. 发明授权

US08572420B2 Power managed USB for computing applications using a controller 有权
标题翻译：电源管理USB用于使用控制器计算应用程序
公开(公告)号：US08572420B2
公开(公告)日：2013-10-29
申请号：US11071961
申请日：2005-03-04
申请人： Drew J. Dutton , James R. MacDonald , Henry Wurzburg
发明人： Drew J. Dutton , James R. MacDonald , Henry Wurzburg
IPC分类号： G06F3/00
CPC分类号： G06K19/07732 , G06K7/0013 , G06K7/0086 , G06K19/0701
摘要： In various embodiments, a computer system may include a computer controller to send and/or receive sideband signals to/from a USB device. In some embodiments, the USB device may include a USB controller to send/receive sideband signals to/from the computer controller. The computer controller and USB controller may allow communications between the computer system and the USB device when either of the computer system or USB device is in a low power state. The sideband signal sent between the computer system and the USB device may trigger the other of the computer system or USB device to enter a normal power state. In some embodiments, the computer controller and/or USB controller may be further coupled to a memory to buffer data to be sent to the computer system or USB device after the computer system or USB device returns to a normal power state.
摘要翻译：在各种实施例中，计算机系统可以包括计算机控制器来向/从USB设备发送和/或接收边带信号。在一些实施例中，USB设备可以包括用于向计算机控制器发送/接收边带信号的USB控制器。当计算机系统或USB设备中的任一个处于低功率状态时，计算机控制器和USB控制器可以允许计算机系统和USB设备之间的通信。在计算机系统和USB设备之间发送的边带信号可能触发计算机系统或USB设备中的另一个进入正常的电源状态。在一些实施例中，计算机控制器和/或USB控制器可以进一步耦合到存储器，以在计算机系统或USB设备恢复到正常功率状态之后缓冲要发送到计算机系统或USB设备的数据。

2. 发明授权

US07685450B2 Power management of computer peripheral devices which determines non-usage of a device through usage detection of other devices 有权
标题翻译：通过其他设备的使用检测来确定设备不使用的计算机外围设备的电源管理
公开(公告)号：US07685450B2
公开(公告)日：2010-03-23
申请号：US11674450
申请日：2007-02-13
申请人： Drew J. Dutton , James R. MacDonald , Stephen Cox
发明人： Drew J. Dutton , James R. MacDonald , Stephen Cox
IPC分类号： G06F1/00
CPC分类号： G06F1/3215
摘要： A system and method for monitoring usage of peripheral devices and placing a second peripheral device in a low power state when the usage indicates that a second peripheral device is not being used. For example, if a computer system detects that a user's current typing rate indicates the user probably has both hands on a keyboard, the computer system may generate a signal to the computer mouse to enter a low power state. The computer system may use prior usage for a user to determine when current usage indicates that the second peripheral device is not being used. After the second peripheral device is placed in a low power state, the computer system may generate a signal to the second peripheral device to return to a normal power state when the computer system determines that the user no longer has both hands occupied.
摘要翻译：一种用于监视外围设备的使用并且当使用指示没有使用第二外围设备时将第二外围设备置于低功率状态的系统和方法。例如，如果计算机系统检测到用户的当前打字率指示用户可能在键盘上具有双手，则计算机系统可以向计算机鼠标生成信号以进入低功率状态。计算机系统可以使用用户的先前使用来确定当前使用情况何时指示第二外围设备未被使用。在第二外围设备处于低功率状态之后，当计算机系统确定用户不再具有双手时，计算机系统可以向第二外围设备产生信号以返回到正常的功率状态。

3. 发明授权

US06825786B1 Associative noise attenuation 失效
标题翻译：相关噪声衰减
公开(公告)号：US06825786B1
公开(公告)日：2004-11-30
申请号：US10430863
申请日：2003-05-06
申请人： James R. MacDonald , Drew J. Dutton , Stephen Cox
发明人： James R. MacDonald , Drew J. Dutton , Stephen Cox
IPC分类号： H03M166
CPC分类号： G10K11/178 , G10K2210/11 , G10K2210/3033 , G11B20/10009
摘要： A system may include a memory configured to store an attenuation waveform and control logic. The control logic is configured to receive a synchronizing signal indicative of an operating characteristic of a noise source. In response to a value of a characteristic (e.g., frequency) of the synchronizing signal, the control logic is configured to output the attenuation waveform from the memory if the attenuation waveform is associated with that value of the characteristic of the synchronizing signal. An attenuating noise generated dependent on the attenuation waveform attenuates a noise generated by the noise source.
摘要翻译：系统可以包括被配置为存储衰减波形和控制逻辑的存储器。控制逻辑被配置为接收指示噪声源的操作特性的同步信号。响应于同步信号的特性（例如，频率）的值，如果衰减波形与同步信号的特性值相关联，则控制逻辑被配置为从存储器输出衰减波形。根据衰减波形产生的衰减噪声会衰减由噪声源产生的噪声。

4. 发明授权

US07222252B2 Power management of computer peripheral devices which determines non-usage of a device through usage detection of other devices 有权
标题翻译：通过其他设备的使用检测来确定设备不使用的计算机外围设备的电源管理
公开(公告)号：US07222252B2
公开(公告)日：2007-05-22
申请号：US10366189
申请日：2003-02-13
申请人： Drew J. Dutton , James R. MacDonald , Stephen Cox
发明人： Drew J. Dutton , James R. MacDonald , Stephen Cox
IPC分类号： G06F1/00 , G06F1/32
CPC分类号： G06F1/3215
摘要： A system and method for monitoring usage of peripheral devices and placing a second peripheral device in a low power state when the usage indicates that a second peripheral device is not being used. For example, if a computer system detects that a user's current typing rate indicates the user probably has both hands on a keyboard, the computer system may generate a signal to the computer mouse to enter a low power state. The computer system may use prior usage for a user to determine when current usage indicates that the second peripheral device is not being used. After the second peripheral device is placed in a low power state, the computer system may generate a signal to the second peripheral device to return to a normal power state when the computer system determines that the user no longer has both hands occupied.
摘要翻译：一种用于监视外围设备的使用并且当使用指示没有使用第二外围设备时将第二外围设备置于低功率状态的系统和方法。例如，如果计算机系统检测到用户的当前打字率指示用户可能在键盘上具有双手，则计算机系统可以向计算机鼠标生成信号以进入低功率状态。计算机系统可以使用用户的先前使用来确定当前使用情况何时指示第二外围设备未被使用。在第二外围设备处于低功率状态之后，当计算机系统确定用户不再具有双手时，计算机系统可以向第二外围设备产生信号以返回到正常的功率状态。

5. 发明授权

US07310498B2 Communication protocol for personal computer system human interface devices over a low bandwidth, bi-directional radio frequency link 有权
标题翻译：用于个人计算机系统人机接口设备的通信协议，通过低带宽，双向射频链路
公开(公告)号：US07310498B2
公开(公告)日：2007-12-18
申请号：US10410088
申请日：2003-04-09
申请人： Trenton B. Henry , Klaas Wortel , Guy A. Stewart , Henry Wurzburg , James R. MacDonald
发明人： Trenton B. Henry , Klaas Wortel , Guy A. Stewart , Henry Wurzburg , James R. MacDonald
IPC分类号： H04B7/00
CPC分类号： H04W36/06 , H04W8/005 , H04W48/08
摘要： A system and method for maintaining communications with a radio frequency (RF) peripheral device such as an RF input device and an RF output device. A computer may search for an RF peripheral device by transmitting a signal request on available channels until a response is received from an RF peripheral device. If the RF channel becomes busy and/or jammed, the RF peripheral device may tune into a predetermined channel while the computer scans for another channel to use. Once the computer finds a better channel, the computer may go to the predetermined channel and broadcast the new channel location to the RF peripheral device. In addition, if an RF signal arrives incomplete or corrupt, the computer may transmit a negative acknowledgement to the RF peripheral device, which may retransmit the previous RF signal.
摘要翻译：用于维持与诸如RF输入设备和RF输出设备的射频（RF）外围设备的通信的系统和方法。计算机可以通过在可用信道上发送信号请求来搜索RF外围设备，直到从RF外围设备接收到响应。如果RF信道变得忙和/或卡住，则RF外围设备可以调谐到预定信道中，同时计算机扫描另一个信道使用。一旦计算机找到更好的信道，则计算机可以进入预定信道并将新的信道位置广播到RF外围设备。此外，如果RF信号到达不完整或损坏，则计算机可以向RF外围设备发送否定确认，RF外设可以重传先前的RF信号。

6. 发明授权

US5784627A Integrated timer for power management and watchdog functions 失效
标题翻译：集成定时器，用于电源管理和看门狗功能
公开(公告)号：US5784627A
公开(公告)日：1998-07-21
申请号：US590967
申请日：1996-01-24
申请人： James R. MacDonald
发明人： James R. MacDonald
IPC分类号： G06F1/14 , G06F1/32
CPC分类号： G06F1/14
摘要： A variety of clock intensive functions, such as interval timers, real-time clocks, and resettable timers for triggering watchdog reset and power management mode transitions, are provided using a single counter and timer event control logic. Such an integrated timer provides multiple time-based event signals from a single sequence of states. The integrated timer circuit includes sequential logic with a plurality of bit outputs, first and second configuration registers, and timer event control logic. The sequential logic supplies a sequence of states at the bit outputs in response to a clock signal. Variations of the sequential logic include a free-running binary counter, ripple counter, or gray code counter. State detection logic is coupled to the bit outputs of the sequential logic and coupled to the first and second configuration registers to receive first and second event descriptors. When the bit outputs of the sequential logic correspond to the first event descriptor, the state detection logic supplies a first state detection signal. When the bit outputs of the sequential logic correspond to the second event descriptor, the state detection logic supplies a second state detection signal. Masking logic selectively masks a first count of successive first state detection signals and supplies the first event signal in response to a subsequent one of the first state detection signals. The masking logic also selectively masks a second count of successive second state detection signals and supplies the second event signal in response to a subsequent one of the second state detection signals.
摘要翻译：使用单个计数器和定时器事件控制逻辑提供各种时钟密集功能，例如间隔定时器，实时时钟和用于触发看门狗复位和电源管理模式转换的可复位定时器。这种集成定时器提供来自单个状态序列的多个基于时间的事件信号。集成定时器电路包括具有多个位输出的顺序逻辑，第一和第二配置寄存器以及定时器事件控制逻辑。顺序逻辑响应于时钟信号在位输出端提供状态序列。顺序逻辑的变化包括自由运行的二进制计数器，纹波计数器或灰色代码计数器。状态检测逻辑耦合到顺序逻辑的位输出并耦合到第一和第二配置寄存器以接收第一和第二事件描述符。当顺序逻辑的位输出对应于第一事件描述符时，状态检测逻辑提供第一状态检测信号。当顺序逻辑的位输出对应于第二事件描述符时，状态检测逻辑提供第二状态检测信号。屏蔽逻辑选择性地屏蔽连续的第一状态检测信号的第一计数，并响应于第一状态检测信号中的后续一个提供第一事件信号。屏蔽逻辑还选择性地屏蔽连续第二状态检测信号的第二计数，并响应于后续的第二状态检测信号提供第二事件信号。

7. 发明授权

US5774544A Method an apparatus for encrypting and decrypting microprocessor serial numbers 失效
标题翻译：方法一种加密和解密微处理器序列号的装置
公开(公告)号：US5774544A
公开(公告)日：1998-06-30
申请号：US623024
申请日：1996-03-28
申请人： Sherman Lee , James R. MacDonald , Michael T. Wisor
发明人： Sherman Lee , James R. MacDonald , Michael T. Wisor
IPC分类号： G06F11/00 , G06F12/14 , G06F21/00 , H04L9/00
CPC分类号： H04L63/062 , G06F11/006 , G06F21/121 , G06F21/73 , G06F21/74 , H04L63/0428 , H04L63/0876 , H04L9/0897 , H04L9/3236 , G06F12/1408 , G06F2207/7219 , G06F2211/007 , G06F2221/0737 , G06F2221/2101 , G06F2221/2105 , G06F2221/2129 , G06F2221/2139 , H04L2209/12 , H04L2209/34 , H04L2463/062
摘要： A method and apparatus for encrypting and decrypting a microprocessor serial number. First and second encryption keys and a serial number are provided in microprocessor machine specific registers. The serial number is encrypted using the first key. The encrypted serial number is encrypted using the second key. The first encryption key may be encrypted along with the serial number using the second key. The double encrypted serial number is then stored in memory provided for that purpose.
摘要翻译：一种用于加密和解密微处理器序列号的方法和装置。微处理器专用寄存器中提供第一和第二加密密钥和序列号。使用第一个密钥对序列号进行加密。使用第二个密钥对加密的序列号进行加密。第一加密密钥可以使用第二密钥与序列号一起被加密。然后将双加密序列号存储在为此目的提供的存储器中。

8. 发明授权

US5630099A Non-volatile memory array controller capable of controlling memory banks having variable bit widths 失效
标题翻译：能够控制具有可变位宽度的存储体的非易失性存储器阵列控制器
公开(公告)号：US5630099A
公开(公告)日：1997-05-13
申请号：US166124
申请日：1993-12-10
申请人： James R. MacDonald , Douglas D. Gephardt
发明人： James R. MacDonald , Douglas D. Gephardt
IPC分类号： G06F12/06 , G06F13/40 , G06F12/04
CPC分类号： G06F13/4018
摘要： A non-volatile memory controller is provided which is connectable directly to the local bus of a computer system and which allows access to one or more 32-bit banks of ROM and to an 8-bit bank of non-volatile memory. The 8-bit bank of non-volatile memory may be used, for example, to store BIOS code, and may be implemented using a ROM or flash memory device. The non-volatile memory controller includes a data router, a sequencer, and a set of output latches for routing the 8-bit BIOS code (stored within the 8-bit bank) to selected byte lanes of the local bus and for converting the 8-bit data to 32-bit local bus data. The non-volatile memory controller further supports high performance, 32-bit accesses to the user software stored within the 32-bit banks. If the system designer or user instead must maximize the memory capacity of the computer system, the 8-bit bank of memory may be replaced with a larger 32-bit bank of memory. In this configuration, a control signal is provided to the non-volatile memory controller to indicate that a 32-bit bank is connected rather than an 8-bit bank. The control signal causes the sequencer and the data router to be disabled. When a memory access to the 32-bit bank is executed, the non-volatile memory controller accesses the data within the 32-bit bank and drives the data directly on the CPU local bus.
摘要翻译：提供了一种非易失性存储器控制器，其可直接连接到计算机系统的本地总线，并且允许访问一个或多个32位的ROM组和8位非易失性存储器组。 8位非易失性存储器组可以用于例如存储BIOS代码，并且可以使用ROM或闪速存储器件来实现。非易失性存储器控制器包括数据路由器，定序器和一组输出锁存器，用于将8位BIOS代码（存储在8位存储区中）路由到本地总线的选定字节通道，并用于转换8 位数据传输到32位本地总线数据。非易失性存储器控制器还支持对存储在32位存储区中的用户软件的高性能32位访问。如果系统设计人员或用户必须最大化计算机系统的内存容量，则8位存储器组可能会被更大的32位存储器组替换。在该配置中，向非易失性存储器控制器提供控制信号以指示连接32位存储体而不是8位存储体。控制信号使定序器和数据路由器被禁用。当执行对32位存储区的存储器访问时，非易失性存储器控制器访问32位存储区中的数据，并直接在CPU本地总线上驱动数据。

9. 发明授权

US5557757A High performance integrated processor architecture including a sub-bus control unit for generating signals to control a secondary, non-multiplexed external bus 失效
标题翻译：高性能集成处理器架构，包括用于产生信号以控制次级非多路复用外部总线的子总线控制单元
公开(公告)号：US5557757A
公开(公告)日：1996-09-17
申请号：US190647
申请日：1994-02-02
申请人： Douglas D. Gephardt , Dan S. Mudgett , James R. MacDonald
发明人： Douglas D. Gephardt , Dan S. Mudgett , James R. MacDonald
IPC分类号： G06F13/36 , G06F13/40 , G06F13/42 , G06F13/38
CPC分类号： G06F13/423 , G06F13/4027
摘要： An integrated processor that employs a bus interface unit to accommodate high performance data transfers via an external peripheral interconnect bus with multiplexed address/data lines. The peripheral interconnect bus, which may be a PCI standard bus, accommodates data transfers between an internal bus of the integrated processor and PCI peripheral devices. The integrated processor further includes a sub-bus control unit that generates a set of side-band control signals that allow the external derivation of a lower performance secondary bus, such as an ISA bus, without requiring a complete set of external pins for the secondary bus on the integrated processor. The derivation of the secondary bus is accomplished with an external data buffer and an external address latch which are controlled by the side-band control signals. Separate address and data lines from the integrated processor for the secondary bus are not required. Accordingly, high performance peripheral devices are supported by the integrated processor as well as lower performance, lower-cost peripherals without a significant increase in the pin-count of the integrated processor. Accordingly, overall cost of the integrated processor is kept low while a wide range of peripheral devices are supported.
摘要翻译：集成处理器，采用总线接口单元，通过外部外部互连总线与复用的地址/数据线进行高性能数据传输。可以是PCI标准总线的外围互连总线适应在集成处理器的内部总线与PCI外围设备之间的数据传输。集成处理器还包括一个子总线控制单元，该子总线控制单元产生一组边带控制信号，这些边带控制信号允许诸如ISA总线的较低性能辅助总线的外部导出，而不需要用于次级的完整的一组外部引脚总线上的集成处理器。辅助总线的推导是通过由边带控制信号控制的外部数据缓冲器和外部地址锁存来实现的。不需要用于辅助总线的集成处理器的独立地址和数据线。因此，高性能外围设备由集成处理器以及性能更低，成本更低的外设支持，而不会显着增加集成处理器的引脚数。因此，在支持广泛的外围设备的情况下，集成处理器的整体成本保持较低。

10. 发明授权

US06550059B1 Method for generating optimized vector instructions from high level programming languages 有权
标题翻译：从高级编程语言生成优化矢量指令的方法
公开(公告)号：US06550059B1
公开(公告)日：2003-04-15
申请号：US09412030
申请日：1999-10-04
申请人： Gwangwoo “Johnny” Choe , James R. MacDonald , Paul B. Mann
发明人： Gwangwoo “Johnny” Choe , James R. MacDonald , Paul B. Mann
IPC分类号： G06F945
CPC分类号： G06F8/447
摘要： A method for compiling source code to produce vector instructions, wherein parallel operands are placed in adjacent locations in memory and wherein the realignment of the operands is minimized. One embodiment generates two-element vector instructions from generalized (e.g., non-loop) source instructions. Memory locations are assigned to the corresponding operands based on the operations which are selected for parallel execution, so that parallel operations operate on data which are adjacent in memory. The memory locations are assigned in a way which minimizes realignment of the data (i.e., swapping positions of two operands.) Another embodiment comprises a software program (e.g., a vectorizing compiler) which examines a block of program code, analyzes the operators within the code and generates vectorized code in accordance with the foregoing method.
摘要翻译：用于编译源代码以产生向量指令的方法，其中并行操作数被放置在存储器中的相邻位置，并且其中操作数的重新对准最小化。一个实施例从广义（例如，非循环）源指令生成双元素向量指令。基于为并行执行选择的操作，将存储器位置分配给相应的操作数，使得并行操作对存储器中相邻的数据进行操作。以最小化数据重新对准（即，两个操作数的交换位置）的方式分配存储器位置。另一实施例包括检查程序代码块的软件程序（例如，向量化编译器），分析程序代码块内的操作符代码并根据前述方法产生矢量化代码。

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