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    • 7. 发明授权
      US5784627A Integrated timer for power management and watchdog functions 失效
    • Integrated timer for power management and watchdog functions
    • 集成定时器，用于电源管理和看门狗功能
    • US5784627A
    • 1998-07-21
    • US590967
    • 1996-01-24
    • James R. MacDonald
    • James R. MacDonald
    • G06F1/14 , G06F1/32
    • G06F1/14
    • A variety of clock intensive functions, such as interval timers, real-time clocks, and resettable timers for triggering watchdog reset and power management mode transitions, are provided using a single counter and timer event control logic. Such an integrated timer provides multiple time-based event signals from a single sequence of states. The integrated timer circuit includes sequential logic with a plurality of bit outputs, first and second configuration registers, and timer event control logic. The sequential logic supplies a sequence of states at the bit outputs in response to a clock signal. Variations of the sequential logic include a free-running binary counter, ripple counter, or gray code counter. State detection logic is coupled to the bit outputs of the sequential logic and coupled to the first and second configuration registers to receive first and second event descriptors. When the bit outputs of the sequential logic correspond to the first event descriptor, the state detection logic supplies a first state detection signal. When the bit outputs of the sequential logic correspond to the second event descriptor, the state detection logic supplies a second state detection signal. Masking logic selectively masks a first count of successive first state detection signals and supplies the first event signal in response to a subsequent one of the first state detection signals. The masking logic also selectively masks a second count of successive second state detection signals and supplies the second event signal in response to a subsequent one of the second state detection signals.
    • 使用单个计数器和定时器事件控制逻辑提供各种时钟密集功能，例如间隔定时器，实时时钟和用于触发看门狗复位和电源管理模式转换的可复位定时器。 这种集成定时器提供来自单个状态序列的多个基于时间的事件信号。 集成定时器电路包括具有多个位输出的顺序逻辑，第一和第二配置寄存器以及定时器事件控制逻辑。 顺序逻辑响应于时钟信号在位输出端提供状态序列。 顺序逻辑的变化包括自由运行的二进制计数器，纹波计数器或灰色代码计数器。 状态检测逻辑耦合到顺序逻辑的位输出并耦合到第一和第二配置寄存器以接收第一和第二事件描述符。 当顺序逻辑的位输出对应于第一事件描述符时，状态检测逻辑提供第一状态检测信号。 当顺序逻辑的位输出对应于第二事件描述符时，状态检测逻辑提供第二状态检测信号。 屏蔽逻辑选择性地屏蔽连续的第一状态检测信号的第一计数，并响应于第一状态检测信号中的后续一个提供第一事件信号。 屏蔽逻辑还选择性地屏蔽连续第二状态检测信号的第二计数，并响应于后续的第二状态检测信号提供第二事件信号。
    • 基本信息 添加关注 加入工作空间 PDF全文 PDF下载 全文下载 相似专利 双屏查看 权利要求书 说明书全文 Global Dossier Espacenet 法律信息 同族专利 专利引用
    • 8. 发明授权
      US5630099A Non-volatile memory array controller capable of controlling memory banks having variable bit widths 失效
    • Non-volatile memory array controller capable of controlling memory banks having variable bit widths
    • 能够控制具有可变位宽度的存储体的非易失性存储器阵列控制器
    • US5630099A
    • 1997-05-13
    • US166124
    • 1993-12-10
    • James R. MacDonald , Douglas D. Gephardt
    • James R. MacDonald , Douglas D. Gephardt
    • G06F12/06 , G06F13/40 , G06F12/04
    • G06F13/4018
    • A non-volatile memory controller is provided which is connectable directly to the local bus of a computer system and which allows access to one or more 32-bit banks of ROM and to an 8-bit bank of non-volatile memory. The 8-bit bank of non-volatile memory may be used, for example, to store BIOS code, and may be implemented using a ROM or flash memory device. The non-volatile memory controller includes a data router, a sequencer, and a set of output latches for routing the 8-bit BIOS code (stored within the 8-bit bank) to selected byte lanes of the local bus and for converting the 8-bit data to 32-bit local bus data. The non-volatile memory controller further supports high performance, 32-bit accesses to the user software stored within the 32-bit banks. If the system designer or user instead must maximize the memory capacity of the computer system, the 8-bit bank of memory may be replaced with a larger 32-bit bank of memory. In this configuration, a control signal is provided to the non-volatile memory controller to indicate that a 32-bit bank is connected rather than an 8-bit bank. The control signal causes the sequencer and the data router to be disabled. When a memory access to the 32-bit bank is executed, the non-volatile memory controller accesses the data within the 32-bit bank and drives the data directly on the CPU local bus.
    • 提供了一种非易失性存储器控制器，其可直接连接到计算机系统的本地总线，并且允许访问一个或多个32位的ROM组和8位非易失性存储器组。 8位非易失性存储器组可以用于例如存储BIOS代码，并且可以使用ROM或闪速存储器件来实现。 非易失性存储器控制器包括数据路由器，定序器和一组输出锁存器，用于将8位BIOS代码（存储在8位存储区中）路由到本地总线的选定字节通道，并用于转换8 位数据传输到32位本地总线数据。 非易失性存储器控制器还支持对存储在32位存储区中的用户软件的高性能32位访问。 如果系统设计人员或用户必须最大化计算机系统的内存容量，则8位存储器组可能会被更大的32位存储器组替换。 在该配置中，向非易失性存储器控制器提供控制信号以指示连接32位存储体而不是8位存储体。 控制信号使定序器和数据路由器被禁用。 当执行对32位存储区的存储器访问时，非易失性存储器控制器访问32位存储区中的数据，并直接在CPU本地总线上驱动数据。
    • 基本信息 添加关注 加入工作空间 PDF全文 PDF下载 全文下载 相似专利 双屏查看 权利要求书 说明书全文 Global Dossier Espacenet 法律信息 同族专利 专利引用
    • 9. 发明授权
      US5557757A High performance integrated processor architecture including a sub-bus control unit for generating signals to control a secondary, non-multiplexed external bus 失效
    • High performance integrated processor architecture including a sub-bus control unit for generating signals to control a secondary, non-multiplexed external bus
    • 高性能集成处理器架构，包括用于产生信号以控制次级非多路复用外部总线的子总线控制单元
    • US5557757A
    • 1996-09-17
    • US190647
    • 1994-02-02
    • Douglas D. Gephardt , Dan S. Mudgett , James R. MacDonald
    • Douglas D. Gephardt , Dan S. Mudgett , James R. MacDonald
    • G06F13/36 , G06F13/40 , G06F13/42 , G06F13/38
    • G06F13/423 , G06F13/4027
    • An integrated processor that employs a bus interface unit to accommodate high performance data transfers via an external peripheral interconnect bus with multiplexed address/data lines. The peripheral interconnect bus, which may be a PCI standard bus, accommodates data transfers between an internal bus of the integrated processor and PCI peripheral devices. The integrated processor further includes a sub-bus control unit that generates a set of side-band control signals that allow the external derivation of a lower performance secondary bus, such as an ISA bus, without requiring a complete set of external pins for the secondary bus on the integrated processor. The derivation of the secondary bus is accomplished with an external data buffer and an external address latch which are controlled by the side-band control signals. Separate address and data lines from the integrated processor for the secondary bus are not required. Accordingly, high performance peripheral devices are supported by the integrated processor as well as lower performance, lower-cost peripherals without a significant increase in the pin-count of the integrated processor. Accordingly, overall cost of the integrated processor is kept low while a wide range of peripheral devices are supported.
    • 集成处理器，采用总线接口单元，通过外部外部互连总线与复用的地址/数据线进行高性能数据传输。 可以是PCI标准总线的外围互连总线适应在集成处理器的内部总线与PCI外围设备之间的数据传输。 集成处理器还包括一个子总线控制单元，该子总线控制单元产生一组边带控制信号，这些边带控制信号允许诸如ISA总线的较低性能辅助总线的外部导出，而不需要用于次级的完整的一组外部引脚 总线上的集成处理器。 辅助总线的推导是通过由边带控制信号控制的外部数据缓冲器和外部地址锁存来实现的。 不需要用于辅助总线的集成处理器的独立地址和数据线。 因此，高性能外围设备由集成处理器以及性能更低，成本更低的外设支持，而不会显着增加集成处理器的引脚数。 因此，在支持广泛的外围设备的情况下，集成处理器的整体成本保持较低。
    • 基本信息 添加关注 加入工作空间 PDF全文 PDF下载 全文下载 相似专利 双屏查看 权利要求书 说明书全文 Global Dossier Espacenet 法律信息 同族专利 专利引用
    • 10. 发明授权
      US06550059B1 Method for generating optimized vector instructions from high level programming languages 有权
    • Method for generating optimized vector instructions from high level programming languages
    • 从高级编程语言生成优化矢量指令的方法
    • US06550059B1
    • 2003-04-15
    • US09412030
    • 1999-10-04
    • Gwangwoo “Johnny” Choe , James R. MacDonald , Paul B. Mann
    • Gwangwoo “Johnny” Choe , James R. MacDonald , Paul B. Mann
    • G06F945
    • G06F8/447
    • A method for compiling source code to produce vector instructions, wherein parallel operands are placed in adjacent locations in memory and wherein the realignment of the operands is minimized. One embodiment generates two-element vector instructions from generalized (e.g., non-loop) source instructions. Memory locations are assigned to the corresponding operands based on the operations which are selected for parallel execution, so that parallel operations operate on data which are adjacent in memory. The memory locations are assigned in a way which minimizes realignment of the data (i.e., swapping positions of two operands.) Another embodiment comprises a software program (e.g., a vectorizing compiler) which examines a block of program code, analyzes the operators within the code and generates vectorized code in accordance with the foregoing method.
    • 用于编译源代码以产生向量指令的方法，其中并行操作数被放置在存储器中的相邻位置，并且其中操作数的重新对准最小化。 一个实施例从广义（例如，非循环）源指令生成双元素向量指令。 基于为并行执行选择的操作，将存储器位置分配给相应的操作数，使得并行操作对存储器中相邻的数据进行操作。 以最小化数据重新对准（即，两个操作数的交换位置）的方式分配存储器位置。另一实施例包括检查程序代码块的软件程序（例如，向量化编译器），分析程序代码块内的操作符 代码并根据前述方法产生矢量化代码。
    • 基本信息 添加关注 加入工作空间 PDF全文 PDF下载 全文下载 相似专利 双屏查看 权利要求书 说明书全文 Espacenet 法律信息 同族专利 专利引用
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