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1. 发明授权

US06550059B1 Method for generating optimized vector instructions from high level programming languages 有权
标题翻译：从高级编程语言生成优化矢量指令的方法
公开(公告)号：US06550059B1
公开(公告)日：2003-04-15
申请号：US09412030
申请日：1999-10-04
申请人： Gwangwoo “Johnny” Choe , James R. MacDonald , Paul B. Mann
发明人： Gwangwoo “Johnny” Choe , James R. MacDonald , Paul B. Mann
IPC分类号： G06F945
CPC分类号： G06F8/447
摘要： A method for compiling source code to produce vector instructions, wherein parallel operands are placed in adjacent locations in memory and wherein the realignment of the operands is minimized. One embodiment generates two-element vector instructions from generalized (e.g., non-loop) source instructions. Memory locations are assigned to the corresponding operands based on the operations which are selected for parallel execution, so that parallel operations operate on data which are adjacent in memory. The memory locations are assigned in a way which minimizes realignment of the data (i.e., swapping positions of two operands.) Another embodiment comprises a software program (e.g., a vectorizing compiler) which examines a block of program code, analyzes the operators within the code and generates vectorized code in accordance with the foregoing method.
摘要翻译：用于编译源代码以产生向量指令的方法，其中并行操作数被放置在存储器中的相邻位置，并且其中操作数的重新对准最小化。一个实施例从广义（例如，非循环）源指令生成双元素向量指令。基于为并行执行选择的操作，将存储器位置分配给相应的操作数，使得并行操作对存储器中相邻的数据进行操作。以最小化数据重新对准（即，两个操作数的交换位置）的方式分配存储器位置。另一实施例包括检查程序代码块的软件程序（例如，向量化编译器），分析程序代码块内的操作符代码并根据前述方法产生矢量化代码。

2. 发明授权

US06484193B1 Fully pipelined parallel multiplier with a fast clock cycle 有权
标题翻译：完全流水线的并行乘法器，具有快速的时钟周期
公开(公告)号：US06484193B1
公开(公告)日：2002-11-19
申请号：US09365160
申请日：1999-07-30
申请人： Gwangwoo Johnny Choe , James R. MacDonald
发明人： Gwangwoo Johnny Choe , James R. MacDonald
IPC分类号： G06F752
CPC分类号： G06F7/5318 , G06F2207/3884
摘要： A fully pipelined parallel multiplier with a fast clock cycle. The pipelined parallel multiplier contains three units: a bit-product matrix unit, a reduction unit, and an addition unit. The bit-product matrix is configured to receive two binary numbers, a multiplier and a multiplicand. A bit-product matrix is formed based on these two numbers. The bit-product matrix unit forms a first pipeline stage. The bit-product matrix is latched to the reduction unit using d-type latch circuits. The reduction unit includes a plurality of reduction stages, with each reduction stage acting as a pipeline stage. The reduction unit reduces the matrix down to a two-row matrix. Intermediate results are latched from one stage to the next using d-type latch circuits. The reduction unit also contains a plurality of half-adder and full-adder circuits. The final two-row matrix formed by the reduction unit is then latched to an addition unit. The addition unit includes one or more stages of addition, with each stage also acting as a pipeline stage. Carry lookahead adder (CLA) circuits are cascaded to perform the addition, with one CLA per addition stage. Results from each addition stage are latched to the next stage using d-type latch circuits. The output from the final stage is the final product of the multiplication.
摘要翻译：具有快速时钟周期的完全流水线并行乘法器。流水线并行乘法器包含三个单元：位乘矩阵单元，还原单元和加法单元。位产品矩阵被配置为接收两个二进制数，乘数和被乘数。基于这两个数字形成位产品矩阵。位产品矩阵单元形成第一流水线阶段。使用d型锁存电路将位产品矩阵锁存到还原单元。还原单元包括多个还原阶段，每个还原阶段用作流水线段。缩小单元将矩阵降低到两行矩阵。使用d型锁存电路将中间结果从一个级锁存到下一级。还原单元还包含多个半加法器和全加器电路。然后将由还原单元形成的最后的两行矩阵锁存到加法单元。添加单元包括一个或多个添加阶段，每个阶段也用作流水线阶段。进位前置加法器（CLA）电路级联以执行相加，每个加法阶段有一个CLA。使用d型锁存电路将每个加法级的结果锁存到下一级。最终阶段的产出是乘法的最终产物。

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