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1. 发明授权

US07256611B2 Cross-bar matrix with LCD functionality 失效
标题翻译：带有LCD功能的横杆矩阵
公开(公告)号：US07256611B2
公开(公告)日：2007-08-14
申请号：US11005700
申请日：2004-12-07
申请人： Douglas R. Holberg , Kenneth W. Fernald
发明人： Douglas R. Holberg , Kenneth W. Fernald
IPC分类号： H03K19/177
CPC分类号： H03K19/1731
摘要： A cross-bar matrix includes a plurality of matrix cells arranged in rows and columns wherein each row of cells is associated with a signal input and each column of cells is associated with a common signal output. An enable input controls whether at least a portion of the cells couple a signal on the associated common signal input to a signal output associated with a cell or couple an LCD signal to a signal output and exclude control of the at least portion of said plurality of cells by the control input.
摘要翻译：交叉矩阵矩阵包括以行和列排列的多个矩阵单元，其中每行单元与信号输入相关联，并且每列单元与公共信号输出相关联。使能输入控制是否至少一部分单元将相关联的公共信号输入上的信号耦合到与单元相关联的信号输出或将LCD信号耦合到信号输出，并且排除对所述多个单元由控制输入。

2. 发明授权

US07504900B2 Integrated circuit package including programmable oscillators 有权
标题翻译：集成电路封装，包括可编程振荡器
公开(公告)号：US07504900B2
公开(公告)日：2009-03-17
申请号：US11694624
申请日：2007-03-30
申请人： Donald E. Alfano , Danny J. Allred , Douglas S. Piasecki , Kenneth W. Fernald , Ka Y. Leung , Brian Caloway , Alan Storvik , Paul Highley , Douglas R. Holberg
发明人： Donald E. Alfano , Danny J. Allred , Douglas S. Piasecki , Kenneth W. Fernald , Ka Y. Leung , Brian Caloway , Alan Storvik , Paul Highley , Douglas R. Holberg
IPC分类号： G06F1/04 , H03B5/00 , H03B5/12 , H03B5/24 , H03B5/36
CPC分类号： G06F13/385 , G06F1/08 , G06F15/7814 , H03M1/122 , H03M1/183 , H03M1/462 , Y02D10/12 , Y02D10/13 , Y02D10/14 , Y02D10/151
摘要： An integrated circuit package includes a processing core and an internal oscillator. The processing core operates on a set of instructions to carry out predefined processes. The internal oscillator provides a system clock for the integrated circuit package. The internal oscillator has associated therewith an internal control register for controlling the operation of the internal oscillator responsive to control bits of the internal oscillator controlled by the processing core.
摘要翻译：集成电路封装包括处理核心和内部振荡器。处理核心通过一组指令来执行预定义的过程。内部振荡器为集成电路封装提供系统时钟。内部振荡器具有与其相关联的内部控制寄存器，用于响应于由处理核心控制的内部振荡器的控制位来控制内部振荡器的操作。

3. 发明授权

US07660968B2 Reconfigurable interface for coupling functional input/output blocks to limited number of I/O pins 有权
标题翻译：可重构接口，用于将功能输入/输出块耦合到有限数量的I / O引脚
公开(公告)号：US07660968B2
公开(公告)日：2010-02-09
申请号：US11772184
申请日：2007-06-30
申请人： Donald E. Alfano , Danny J. Allred , Douglas S. Piasecki , Kenneth W. Fernald , Ka Y. Leung , Brian Caloway , Alan Storvik , Paul Highley , Douglas R. Holberg
发明人： Donald E. Alfano , Danny J. Allred , Douglas S. Piasecki , Kenneth W. Fernald , Ka Y. Leung , Brian Caloway , Alan Storvik , Paul Highley , Douglas R. Holberg
IPC分类号： G06F13/00
CPC分类号： G06F13/385 , G06F1/08 , G06F15/7814 , H03M1/122 , H03M1/183 , H03M1/462 , Y02D10/12 , Y02D10/13 , Y02D10/14 , Y02D10/151
摘要： A reconfigurable processor includes a processor core for operating on a set of instructions to carry out predefined processes and includes a plurality of input/output pins in addition to a plurality of functional input/output blocks. These functional blocks allow the processing core to interface with the plurality of input/output pins, each of the functional input/output blocks having an associated and predetermined functionality. This functionality comprises the output as a function of the input, the function defined by the functionality. Each of the functional input/output blocks has a requirement for a defined number of the plurality of input/output pins wherein the total of the defined number for all of the plurality of functional input/output blocks exceeds the number of the plurality of input/output pins and wherein the processor core is interfaced with one of the input or output of each of the functional blocks. A reconfigurable interface selectively interfaces between the other of the input or output of the functional blocks and a select one or ones of the plurality of input/output pins, such that the processor core can be interfaced with the select one or ones of the input/output pins. The reconfigurable interface is operable to define how each of the plurality of input/output pins interfaces with the select ones of the plurality of functional blocks and the associated functionality in accordance with configuration information. A non-volatile memory is provided for storing information for use in association with the configuration information, such that the stored information can be altered.
摘要翻译：可重构处理器包括用于在一组指令上操作以执行预定义的处理的处理器核心，并且除了多个功能输入/输出块之外还包括多个输入/输出引脚。这些功能块允许处理核与多个输入/输出引脚相连接，每个功能输入/输出块具有相关联的和预定的功能。该功能包括作为输入的功能的输出，功能定义的功能。每个功能输入/输出块对多个输入/输出引脚的定义数量要求，其中所有多个功能输入/输出块中的所有定义数目的总数超过多个输入/ 输出引脚，并且其中处理器核心与每个功能块的输入或输出中的一个接口。可重配置接口选择性地在功能块的输入或输出中的另一个与多个输入/输出引脚中的选择一个或多个输入/输出引脚之间进行接口，使得处理器核可以与选择的一个或多个输入/ 输出引脚。可重配置接口可操作以根据配置信息定义多个输入/输出引脚中的每一个如何与多个功能块中的选择功能块和相关联的功能接口。提供非易失性存储器用于存储与配置信息相关联使用的信息，使得可以改变所存储的信息。

4. 发明授权

US07171542B1 Reconfigurable interface for coupling functional input/output blocks to limited number of i/o pins 失效
标题翻译：用于将功能输入/输出块耦合到有限数量的I / O引脚的可重新配置的接口
公开(公告)号：US07171542B1
公开(公告)日：2007-01-30
申请号：US09885459
申请日：2001-06-19
申请人： Donald E. Alfano , Danny Allred , Douglas S. Piasecki , Kenneth W. Fernald , Ka Y Leung , Brian Caloway , Alvin Storvik , Paul Highley , Douglas R Holberg
发明人： Donald E. Alfano , Danny Allred , Douglas S. Piasecki , Kenneth W. Fernald , Ka Y Leung , Brian Caloway , Alvin Storvik , Paul Highley , Douglas R Holberg
IPC分类号： G06F13/00
CPC分类号： G06F13/385 , G06F1/08 , G06F15/7814 , H03M1/122 , H03M1/183 , H03M1/462 , Y02D10/12 , Y02D10/13 , Y02D10/14 , Y02D10/151
摘要： A reconfigurable processor system n an intergrated circuit includes a processor core that operates on a set of instructions to carry out predefined processes. A plurality of input/output pins are provided for interfacing with external signals. A reconfigurable interface interfaces between the processor core and the input/output pins through select ones of a plurality of functional blocks. The reconfigurable interface is operable to define how each of the plurality of input/output pins interfaces with the processor core an the functionality associated therewith. The functional blocks provide the interface of the processor core with the input/output pins.
摘要翻译：集成电路中的可重构处理器系统包括对一组指令进行操作以执行预定义的处理的处理器核心。提供多个输入/输出引脚用于与外部信号进行接口。可重新配置的接口通过多个功能块中的选择的接口在处理器核心和输入/输出引脚之间进行接口。可重构接口可操作以定义多个输入/输出引脚中的每一个如何与处理器核心与处理器核心相连接的功能。功能块提供处理器内核与输入/输出引脚的接口。

5. 发明授权

US07498962B2 Analog-to-digital converter with low power track-and-hold mode 有权
标题翻译：具有低功率跟踪和保持模式的模数转换器
公开(公告)号：US07498962B2
公开(公告)日：2009-03-03
申请号：US11618644
申请日：2006-12-29
申请人： Donald E. Alfano , Danny J. Allred , Douglas S. Piasecki , Kenneth W. Fernald , Ka Y. Leung , Brian Caloway , Alvin Storvik , Paul Highley , Douglas R. Holberg
发明人： Donald E. Alfano , Danny J. Allred , Douglas S. Piasecki , Kenneth W. Fernald , Ka Y. Leung , Brian Caloway , Alvin Storvik , Paul Highley , Douglas R. Holberg
IPC分类号： H03M1/00
CPC分类号： G06F13/385 , G06F1/08 , G06F15/7814 , H03M1/122 , H03M1/183 , H03M1/462 , Y02D10/12 , Y02D10/13 , Y02D10/14 , Y02D10/151
摘要： A method for converting analog data to digital data includes operating an analog-to-digital data converter in a tracking mode to sample an input signal and in a convert mode to convert the sampled input signal after sampling to a digital signal. The analog-to-digital data converter is controlled with a controller to operate in different modes of operation by providing at least one step wherein the tracking mode of operation is controlled to initiate at a predetermined time to begin the sampling operation.
摘要翻译：一种将模拟数据转换为数字数据的方法包括以跟踪模式操作模拟数字数据转换器，以对输入信号进行采样，并以转换模式将采样后的采样输入信号转换为数字信号。模拟数字数据转换器由控制器控制，以通过提供至少一个步骤操作在不同的操作模式，其中跟踪操作模式被控制以在预定时间开始以开始采样操作。

6. 发明授权

US07613901B2 Comparators in IC with programmably controlled positive / negative hysteresis level and open-drain / push-pull output coupled to crossbar switch or rising / falling edge interrupt generation 有权
标题翻译： IC中的比较器具有可编程控制的正/负滞后电平和开漏/推挽输出，连接到交叉开关或上升/下降沿中断产生
公开(公告)号：US07613901B2
公开(公告)日：2009-11-03
申请号：US11694629
申请日：2007-03-30
申请人： Donald E. Alfano , Danny J. Allred , Douglas S. Piasecki , Kenneth W. Fernald , Ka Y. Leung , Brian Caloway , Alvin Storvik , Paul Highley , Douglas R. Holberg
发明人： Donald E. Alfano , Danny J. Allred , Douglas S. Piasecki , Kenneth W. Fernald , Ka Y. Leung , Brian Caloway , Alvin Storvik , Paul Highley , Douglas R. Holberg
IPC分类号： G06F19/00 , H03K5/22
CPC分类号： G06F13/385 , G06F1/08 , G06F15/7814 , H03M1/122 , H03M1/183 , H03M1/462 , Y02D10/12 , Y02D10/13 , Y02D10/14 , Y02D10/151
摘要： An integrated circuit package includes a processing core for operating on a set of instructions to carry out predefined processes. A plurality of comparators perform compare operations within the integrated circuit package. At least one control register is associated with each of the plurality of comparators, and each of the plurality of comparators are software programmable to control a hysteresis of the comparators responsive to control bits established in the at least one control register of the comparator by the processing core. An amount of positive hysteresis is programmed via a first group of the control bits and an amount of negative hysteresis is programmed via a second group of the control bits.
摘要翻译：集成电路封装包括用于对一组指令进行操作以执行预定义的处理的处理核心。多个比较器执行集成电路封装内的比较操作。至少一个控制寄存器与多个比较器中的每个比较器相关联，并且多个比较器中的每一个可软件编程以响应于通过处理在比较器的至少一个控制寄存器中建立的控制位来控制比较器的滞后核心。通过第一组控制位来编程正滞后量，经由第二组控制位来编程负滞后量。

7. 发明授权

US08914624B2 Changing the reset state of a processor 有权
标题翻译：更改处理器的复位状态
公开(公告)号：US08914624B2
公开(公告)日：2014-12-16
申请号：US12976263
申请日：2010-12-22
申请人： Kenneth W. Fernald , Paul I. Zavalney
发明人： Kenneth W. Fernald , Paul I. Zavalney
IPC分类号： G06F1/24 , G06F13/00 , G06F9/44 , G06F9/30
CPC分类号： G06F13/00 , G06F1/24 , G06F9/24 , G06F9/30 , G06F9/44 , G06F9/4403
摘要： An apparatus includes a memory, a processor and a controller. The processor is adapted to begin executing instructions based on content stored starting at a predetermined address in the memory upon reset of the processor. The controller is adapted to, in response to the reset of the processor, provide to the processor content for the predetermined address other than the content that is stored starting at the predetermined address.
摘要翻译：一种装置包括存储器，处理器和控制器。处理器适于在处理器复位时，基于存储器中预定地址开始存储的内容开始执行指令。控制器适于响应于处理器的复位，向除了从预定地址开始存储的内容之外的预定地址提供给处理器内容。

8. 发明授权

US08638081B2 Active droop current sharing 有权
标题翻译：主动下垂电流共享
公开(公告)号：US08638081B2
公开(公告)日：2014-01-28
申请号：US13526791
申请日：2012-06-19
申请人： Douglas E. Heineman , Kenneth W. Fernald
发明人： Douglas E. Heineman , Kenneth W. Fernald
IPC分类号： H02J7/34
CPC分类号： H02M3/1584 , G06F1/26 , H02J1/08 , H02M2001/008 , Y10T307/422
摘要： Point-of-load (POL) regulators may be configured as multiphase POL DC-to-DC (direct current to direct current) converters, operating in a multiphase configuration in order to boost the total current available to a system. Current balancing may be performed by utilizing an active low bandwidth current sharing algorithm that uses matched artificial line resistance (droop resistance) while maintaining multi-loop stability during both steady-state and dynamic transient states. The current sharing algorithm may be facilitated through digital communication between the devices, where the digital bus may be a single wire bus, a parallel bus or a clock-and-data bus.
摘要翻译：负载点（POL）调节器可以配置为多相POL DC-DC（直流到直流电）转换器，以多相配置运行，以提高系统可用的总电流。可以通过利用使用匹配的人造线路电阻（下降电阻）的有源低带宽电流共享算法同时在稳态和动态瞬态状态期间保持多环路稳定性来执行电流平衡。可以通过设备之间的数字通信来促进当前共享算法，其中数字总线可以是单线总线，并行总线或时钟和数据总线。

9. 发明申请

US20130321183A1 CODER WITH SNOOP MODE 有权
标题翻译：编码器与SNOOP模式
公开(公告)号：US20130321183A1
公开(公告)日：2013-12-05
申请号：US13485711
申请日：2012-05-31
申请人： Kenneth W. Fernald
发明人： Kenneth W. Fernald
IPC分类号： H03M13/00
CPC分类号： G06F13/4027 , H03M13/09
摘要： Techniques are disclosed relating to coding data in an apparatus. In one embodiment, the apparatus includes a coder circuit coupled to a data bus, where the coder circuit is configured to receive an indication that data is being transmitted over the data bus from a first circuit to a second circuit. The coder circuit is configured to perform a coding operation on the data in response to receiving the indication. In some embodiments, the coder circuit is configured to operate in a mode in which the coder circuit captures data of a data transmission via the data bus without being specified as a participant of the data transmission. When the coder circuit is not operating in the mode, the coder circuit is not configured to capture data of a data transmission without being specified as a participant of the data transmission.
摘要翻译：公开了与装置中的编码数据有关的技术。在一个实施例中，该装置包括耦合到数据总线的编码器电路，其中编码器电路被配置为接收数据正在数据总线上从第一电路传输到第二电路的指示。编码器电路被配置为响应于接收到指示而对数据执行编码操作。在一些实施例中，编码器电路被配置为在编码器电路经由数据总线捕获数据传输的数据而不被指定为数据传输的参与者的模式下操作。当编码器电路不在该模式下操作时，编码器电路不被配置为捕获数据传输的数据而不被指定为数据传输的参与者。

10. 发明申请

US20120262141A1 Active Droop Current Sharing 有权
标题翻译：主动下垂电流共享
公开(公告)号：US20120262141A1
公开(公告)日：2012-10-18
申请号：US13526791
申请日：2012-06-19
申请人： Douglas E. Heineman , Kenneth W. Fernald
发明人： Douglas E. Heineman , Kenneth W. Fernald
IPC分类号： G05F1/46
CPC分类号： H02M3/1584 , G06F1/26 , H02J1/08 , H02M2001/008 , Y10T307/422
摘要： Point-of-load (POL) regulators may be configured as multiphase POL DC-to-DC (direct current to direct current) converters, operating in a multiphase configuration in order to boost the total current available to a system. Current balancing may be performed by utilizing an active low bandwidth current sharing algorithm that uses matched artificial line resistance (droop resistance) while maintaining multi-loop stability during both steady-state and dynamic transient states. The current sharing algorithm may be facilitated through digital communication between the devices, where the digital bus may be a single wire bus, a parallel bus or a clock-and-data bus.
摘要翻译：负载点（POL）调节器可以配置为多相POL DC-DC（直流到直流电）转换器，以多相配置运行，以提高系统可用的总电流。可以通过利用使用匹配的人造线路电阻（下降电阻）的有源低带宽电流共享算法同时在稳态和动态瞬态状态期间保持多环路稳定性来执行电流平衡。可以通过设备之间的数字通信来促进当前共享算法，其中数字总线可以是单线总线，并行总线或时钟和数据总线。

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