专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US06200866B1 Use of silicon germanium and other alloys as the replacement gate for the fabrication of MOSFET 有权
标题翻译：使用硅锗等合金作为制造MOSFET的替代栅极
公开(公告)号：US06200866B1
公开(公告)日：2001-03-13
申请号：US09410346
申请日：1999-09-30
申请人： Yanjun Ma , Douglas J. Tweet , David R. Evans , Yoshi Ono
发明人： Yanjun Ma , Douglas J. Tweet , David R. Evans , Yoshi Ono
IPC分类号： H01L21338
CPC分类号： H01L21/31053 , H01L21/2807 , H01L21/28194 , H01L21/28202 , H01L21/76801 , H01L21/76804 , H01L21/76834 , H01L29/41733 , H01L29/41775 , H01L29/41783 , H01L29/4908 , H01L29/51 , H01L29/517 , H01L29/518 , H01L29/665 , H01L29/66545 , H01L29/66575 , H01L29/66772 , H01L29/78684
摘要： A method of fabricating a MOSFET is provided, including: depositing an oxide layer on a silicon substrate for device isolation; forming a silicon based alloy island above a gate region in the substrate, wherein the silicon based alloy comprises a silicon germanium alloy or a silicon tin alloy or another alloy of Group IV-B elements; building a sidewall about the silicon based alloy island; forming a source region and a drain region in the substrate; removing the silicon based alloy island, thereby leaving a void over the gate region; filing the void and the areas over the source region and the drain region; and planarizing the upper surface of the structure by chemical mechanical polishing. Alternative embodiments providing conventional and raised source/drain structures are disclosed.
摘要翻译：提供一种制造MOSFET的方法，包括：在硅衬底上沉积氧化层用于器件隔离; 在所述基板的栅极区域的上方形成硅基合金岛，其中所述硅基合金包含硅锗合金或硅锡合金或第IV-B族元素的另一种合金; 围绕硅基合金岛构建侧壁; 在衬底中形成源区和漏区; 去除硅基合金岛，从而在栅极区域上留下空隙; 填充空隙和源区域和漏区域上的区域; 并通过化学机械抛光对结构的上表面进行平面化。公开了提供常规和凸起的源极/漏极结构的替代实施例。

2. 发明授权

US06573134B2 Dual metal gate CMOS devices and method for making the same 失效
公开(公告)号：US06573134B2
公开(公告)日：2003-06-03
申请号：US09817834
申请日：2001-03-27
申请人： Yanjun Ma , Yoshi Ono , David R. Evans , Sheng Teng Hsu
发明人： Yanjun Ma , Yoshi Ono , David R. Evans , Sheng Teng Hsu
IPC分类号： H01L218238
CPC分类号： H01L21/823842 , H01L27/092
摘要： A method of fabricating a dual metal gate CMOS includes forming a gate oxide in a gate region and depositing a place-holder gate in each of a n-well and p-well; removing the place-holder gate and gate oxide; depositing a high-k dielectric in the gate region; depositing a first metal in the gate region of the p-well; depositing a second metal in the gate region of each of the n-well and p-well; and insulating and metallizing the structure. A dual metal gate CMOS of the invention includes PMOS transistor and a NMOS transistor. In the NMOS, a gate includes a high-k cup, a first metal cup formed in the high-k cup, and a second metal gate formed in the first metal cup. In the PMOS, a gate includes a high-k cup and a second metal gate formed in the high-k cup.

3. 发明授权

US06403453B1 Dose control technique for plasma doping in ultra-shallow junction formations 有权
标题翻译：用于等离子体掺杂在超浅结结构中的剂量控制技术
公开(公告)号：US06403453B1
公开(公告)日：2002-06-11
申请号：US09626837
申请日：2000-07-27
申请人： Yoshi Ono , Yanjun Ma , Sheng Teng Hsu
发明人： Yoshi Ono , Yanjun Ma , Sheng Teng Hsu
IPC分类号： H01L2126
CPC分类号： H01L21/2236
摘要： A method of plasma doping substrates is provided. The substrate is covered with photoresist and placed within a plasma chamber. A doping gas is introduced into the chamber and ionized. A dilutant gas is also introduced to provide better control of the total amount of dosage associated with a given duration of exposure. The dilutant gas is preferably monatomic to reduce, or eliminate, affects associated with pressure variations within the chamber caused by dissociation of elements within the plasma chamber. The dilutant gas preferably contains lighter elements so as to reduce, or eliminate, damage to the photoresist caused by ion impacts. The dilutant gas is preferably neon or helium. The present method provides a means to better control the dosage and reduce photoresist damage and contamination.
摘要翻译：提供了一种等离子体掺杂衬底的方法。衬底被光致抗蚀剂覆盖并置于等离子体室内。将掺杂气体引入室并离子化。还引入稀释气体以更好地控制与给定的暴露持续时间相关的剂量的总量。稀释气体优选是单原子的，以减少或消除由等离子体室内的元素解离引起的室内压力变化的影响。稀释气体优选含有较轻的元素，以便减少或消除由离子冲击引起的光致抗蚀剂的损伤。稀释气体优选为氖气或氦气。本方法提供了更好地控制剂量并减少光致抗蚀剂损伤和污染的方法。

4. 发明授权

US06348373B1 Method for improving electrical properties of high dielectric constant films 失效
标题翻译：改善高介电常数膜电性能的方法
公开(公告)号：US06348373B1
公开(公告)日：2002-02-19
申请号：US09538017
申请日：2000-03-29
申请人： Yanjun Ma , Yoshi Ono
发明人： Yanjun Ma , Yoshi Ono
IPC分类号： H01L218242
CPC分类号： H01L21/28185 , H01L21/28194 , H01L21/31155 , H01L21/31604 , H01L21/31691 , H01L29/517
摘要： A method of improving the electrical properties of high dielectric constant films by depositing an initial film and implanting oxygen ions to modify the film by decreasing the oxygen deficiency of the film while reducing or eliminating formation of an interfacial silicon dioxide layer. An initial high dielectric constant material is deposited over a silicon substrate by means of CVD, reactive sputtering or evaporation. Oxygen ions are preferably implanted using plasma ion immersion (PIII), although other methods are also provided. Following implantation the substrate is annealed to condition the high dielectric constant film.
摘要翻译：通过沉积初始膜和注入氧离子以改善膜的氧缺陷，同时减少或消除界面二氧化硅层的形成来改善高介电常数膜的电性能的方法。初始高介电常数材料通过CVD，反应溅射或蒸发沉积在硅衬底上。尽管还提供了其他方法，但优选使用等离子体离子浸渍（PIII）来注入氧离子。在注入后，将衬底退火以调节高介电常数膜。

5. 发明授权

US6060755A Aluminum-doped zirconium dielectric film transistor structure and deposition method for same 有权
标题翻译：掺铝锆电介质膜晶体管结构及其沉积方法相同
公开(公告)号：US6060755A
公开(公告)日：2000-05-09
申请号：US356470
申请日：1999-07-19
申请人： Yanjun Ma , Yoshi Ono
发明人： Yanjun Ma , Yoshi Ono
IPC分类号： C23C14/08 , C23C14/14 , C23C14/58 , C23C16/06 , C23C16/56 , H01B3/12 , H01L21/02 , H01L21/28 , H01L21/316 , H01L21/8232 , H01L29/51 , H01L29/78 , H01L29/76
CPC分类号： H01L21/28185 , H01L21/28194 , H01L29/513 , H01L29/517 , H01L28/56
摘要： A high-k dielectric film is provided which remains amorphous at relatively high annealing temperatures. The high-k dielectric film is a metal oxide of either Zr or Hf, doped with a trivalent metal, such as Al. Because the film resists the formation of a crystalline structure, interfaces to adjacent films have fewer irregularities. When used as a gate dielectric, the film can be made thin to support smaller transistor geometries, while the surface of the channel region can be made smooth to support high electron mobility. Also provided are CVD, sputtering, and evaporation deposition methods for the above-mentioned, trivalent metal doped high dielectric films.
摘要翻译：提供了一种高k电介质膜，其在相对高的退火温度下保持非晶态。高k电介质膜是掺杂有三价金属如Al的Zr或Hf的金属氧化物。由于膜抵抗晶体结构的形成，与相邻膜的界面具有较少的不规则性。当用作栅极电介质时，可以使膜变薄以支持更小的晶体管几何形状，同时沟道区域的表面可以被制成平滑的以支持高电子迁移率。还提供了用于上述三价金属掺杂的高介电膜的CVD，溅射和蒸发沉积方法。

6. 发明授权

US06407435B1 Multilayer dielectric stack and method 有权
标题翻译：多层电介质叠层及方法
公开(公告)号：US06407435B1
公开(公告)日：2002-06-18
申请号：US09502420
申请日：2000-02-11
申请人： Yanjun Ma , Yoshi Ono
发明人： Yanjun Ma , Yoshi Ono
IPC分类号： H01L2976
CPC分类号： H01L21/28185 , H01L21/28194 , H01L21/28202 , H01L29/513 , H01L29/517 , H01L29/518 , H01L29/66583
摘要： A multilayer dielectric stack is provided which has alternating layers of a high-k material and an interposing material. The presence of the interposing material and the thinness of the high-k material layers reduces or eliminate effects of crystallization within the high-k material, even at relatively high annealing temperatures. The high-k dielectric layers are a metal oxide of preferably zirconium or hafnium. The interposing layers are preferably amorphous aluminum oxide, aluminum nitride, or silicon nitride. Because the layers reduce the effects of crystalline structures within individual layers, the overall tunneling current is reduced. Also provided are atomic layer deposition, sputtering, and evaporation as methods of depositing desired materials for forming the above-mentioned multilayer dielectric stack.
摘要翻译：提供了具有高k材料和插入材料的交替层的多层电介质叠层。插入材料的存在和高k材料层的薄度降低或消除了高k材料内的结晶效应，即使在较高的退火温度下也是如此。高k电介质层是优选锆或铪的金属氧化物。插层优选为无定形氧化铝，氮化铝或氮化硅。因为这些层减少了单个层内晶体结构的影响，所以整个隧穿电流降低。还提供了作为沉积用于形成上述多层电介质叠层的所需材料的方法的原子层沉积，溅射和蒸发。

7. 发明授权

US06297539B1 Doped zirconia, or zirconia-like, dielectric film transistor structure and deposition method for same 失效
标题翻译：掺杂的氧化锆或氧化锆样的电介质膜晶体管结构和沉积方法相同
公开(公告)号：US06297539B1
公开(公告)日：2001-10-02
申请号：US09611356
申请日：2000-07-06
申请人： Yanjun Ma , Yoshi Ono
发明人： Yanjun Ma , Yoshi Ono
IPC分类号： H01L2976
CPC分类号： H01L21/28185 , C23C14/083 , C23C16/405 , H01L21/28194 , H01L21/28211 , H01L21/31604 , H01L21/31641 , H01L21/31645 , H01L28/56 , H01L29/513 , H01L29/517
摘要： A high-k dielectric films is provided, which is doped with divalent or trivalent metals to vary the electron affinity, and consequently the electron and hole barrier height. The high-k dielectric film is a metal oxide of either zirconium (Zr) or hafnium (Hf), doped with a divalent metal, such as calcium (Ca) or strontium (Sr), or a trivalent metal, such as aluminum (Al), scandium (Sc), lanthanum (La), or yttrium (Y). By selecting either a divalent or trivalent doping metal, the electron affinity of the dielectric material can be controlled, while also providing a higher dielectric constant material then silicon dioxide. Preferably, the dielectric material will also be amorphous to reduce leakage caused by grain boundaries. Also provided are sputtering, CVD, Atomic Layer CVD, and evaporation deposition methods for the above-mentioned, doped high dielectric films.
摘要翻译：提供了高k电介质膜，其掺杂有二价或三价金属以改变电子亲和力，从而电子和空穴势垒高度。高k电介质膜是掺杂有二价金属如钙（Ca）或锶（Sr）的锆（Zr）或铪（Hf）的金属氧化物，或三价金属如铝（Al ），钪（Sc），镧（La）或钇（Y）。通过选择二价或三价掺杂金属，可以控制介电材料的电子亲和力，同时还提供较高的介电常数材料，然后是二氧化硅。优选地，电介质材料也将是非晶体的，以减少由晶界引起的泄漏。还提供了用于上述掺杂的高介电膜的溅射，CVD，原子层CVD和蒸发沉积方法。

8. 发明授权

US06627503B2 Method of forming a multilayer dielectric stack 失效
公开(公告)号：US06627503B2
公开(公告)日：2003-09-30
申请号：US10137567
申请日：2002-04-30
申请人： Yanjun Ma , Yoshi Ono
发明人： Yanjun Ma , Yoshi Ono
IPC分类号： H01L21336
CPC分类号： H01L21/28185 , H01L21/28194 , H01L21/28202 , H01L29/513 , H01L29/517 , H01L29/518 , H01L29/66583
摘要： A multilayer dielectric stack is provided which has alternating layers of a high-k material and an interposing material. The presence of the interposing material and the thinness of the high-k material layers reduces or eliminate effects of crystallization within the high-k material, even at relatively high annealing temperatures. The high-k dielectric layers are a metal oxide of preferably zirconium or hafnium. The interposing layers are preferably amorphous aluminum oxide, aluminum nitride, or silicon nitride. Because the layers reduce the effects of crystalline structures within individual layers, the overall tunneling current is reduced. Also provided are atomic layer deposition, sputtering, and evaporation as methods of depositing desired materials for forming the above-mentioned multilayer dielectric stack.

9. 发明授权

US06207589B1 Method of forming a doped metal oxide dielectric film 有权
标题翻译：形成掺杂金属氧化物电介质膜的方法
公开(公告)号：US06207589B1
公开(公告)日：2001-03-27
申请号：US09515743
申请日：2000-02-29
申请人： Yanjun Ma , Yoshi Ono
发明人： Yanjun Ma , Yoshi Ono
IPC分类号： H01L2131
CPC分类号： H01L21/28185 , H01L21/28194 , H01L28/56 , H01L29/513 , H01L29/517
摘要： A high-k dielectric film is provided which remains amorphous at relatively high annealing temperatures. The high-k dielectric film is a metal oxide of either Zr or Hf, doped with a trivalent metal, such as Al. Because the film resists the formation of a crystalline structure, interfaces to adjacent films have fewer irregularities. When used as a gate dielectric, the film can be made thin to support smaller transistor geometries, while the surface of the channel region can be made smooth to support high electron mobility. Also provided are CVD, sputtering, and evaporation deposition methods for the above-mentioned, trivalent metal doped high dielectric films.
摘要翻译：提供了一种高k电介质膜，其在相对高的退火温度下保持非晶态。高k电介质膜是掺杂有三价金属如Al的Zr或Hf的金属氧化物。由于膜抵抗晶体结构的形成，与相邻膜的界面具有较少的不规则性。当用作栅极电介质时，可以使膜变薄以支持更小的晶体管几何形状，同时沟道区域的表面可以被制成平滑的以支持高电子迁移率。还提供了用于上述三价金属掺杂的高介电膜的CVD，溅射和蒸发沉积方法。

10. 发明授权

US06632731B2 Structure and method of making a sub-micron MOS transistor 失效
标题翻译：制造亚微米MOS晶体管的结构和方法
公开(公告)号：US06632731B2
公开(公告)日：2003-10-14
申请号：US09783760
申请日：2001-02-14
申请人： Yanjun Ma , David Russell Evans , Yoshi Ono , Sheng Teng Hsu
发明人： Yanjun Ma , David Russell Evans , Yoshi Ono , Sheng Teng Hsu
IPC分类号： H01L213205
CPC分类号： H01L29/6659 , H01L21/28088 , H01L21/28097 , H01L21/76895 , H01L21/76897 , H01L21/82385 , H01L29/42376 , H01L29/4966 , H01L29/4975 , H01L29/66545
摘要： A method of fabricating a sub-micron MOS transistor includes preparing a substrate, including isolating an active region therein; depositing a gate oxide layer; depositing a first selective etchable layer over the gate oxide layer; depositing a second selective etchable layer over the first selective etchable layer; etching the structure to undercut the first selective etchable layer; implanting ions in the active region to form a source region and a drain region; depositing and planarizing the oxide; removing the remaining first selective etchable layer and the second selective etchable layer; depositing a gate electrode; and depositing oxide and metallizing the structure. A sub-micron MOS transistor includes a substrate; and an active region, including a gate region having a length of less than one micron; a source region including a LDD source region; and a drain region including a LDD drain region.
摘要翻译：制造亚微米MOS晶体管的方法包括制备衬底，包括在其中分离有源区; 沉积栅氧化层; 在所述栅极氧化物层上沉积第一选择性可蚀刻层; 在第一选择性可蚀刻层上沉积第二选择性可蚀刻层; 蚀刻结构以切割第一选择性可蚀刻层; 在有源区中注入离子以形成源区和漏区; 沉积和平坦化氧化物; 去除剩余的第一选择性可蚀刻层和第二选择性可蚀刻层; 沉积栅电极; 并沉积氧化物并金属化该结构。亚微米MOS晶体管包括基板; 和有源区，包括具有小于1微米长度的栅区; 源区域，包括LDD源区域; 以及包括LDD漏极区域的漏极区域

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式