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    • 9. 发明专利
    • Nonvolatile memory device having vertical channel and manufacturing method of the same
    • 具有垂直通道的非易失性存储器件及其制造方法
    • JP2008010868A
    • 2008-01-17
    • JP2007163103
    • 2007-06-20
    • Samsung Electronics Co Ltd三星電子株式会社Samsung Electronics Co.,Ltd.
    • YANG SEUNG-JINHAN JEONG-UKCHOI YONG-SUKKWON HYOK-KI
    • H01L21/8247H01L27/115H01L29/788H01L29/792
    • H01L27/11582
    • PROBLEM TO BE SOLVED: To provide a semiconductor flash memory cell pair having a vertical channel.
      SOLUTION: A semiconductor flash memory cell pair includes a semiconductor substrate; first and second source lines formed in the semiconductor substrate; a semiconductor pillar extended from the semiconductor substrate between the first and second source lines; first and second charge storage structures formed on the facing surfaces of the semiconductor pillar and operating together with the first and second source lines; first and second trench structures formed adjacent to the semiconductor pillar and electrically separating the first and second charge storage structures; a first word line formed adjacent to the first charge storage structure; a second word line formed adjacent to the second charge storage structure; and a common drain contact formed on an upper surface of the semiconductor pillar.
      COPYRIGHT: (C)2008,JPO&INPIT
    • 要解决的问题:提供具有垂直通道的半导体闪存单元对。 解决方案:半导体闪存单元对包括半导体衬底; 形成在半导体衬底中的第一和第二源极线; 在所述第一和第二源极线之间从所述半导体衬底延伸的半导体柱; 第一和第二电荷存储结构,形成在半导体柱的相对表面上并与第一和第二源极线一起操作; 第一和第二沟槽结构,形成在与半导体柱相邻并且电分离第一和第二电荷存储结构; 与第一电荷存储结构相邻形成的第一字线; 与第二电荷存储结构相邻形成的第二字线; 以及形成在半导体柱的上表面上的公共漏极接触。 版权所有(C)2008,JPO&INPIT
    • 10. 发明专利
    • Split gate-type nonvolatile semiconductor memory device and manufacturing method of same
    • 分离栅型非易失性半导体存储器件及其制造方法
    • JP2005268804A
    • 2005-09-29
    • JP2005077986
    • 2005-03-17
    • Samsung Electronics Co Ltd三星電子株式会社Samsung Electronics Co.,Ltd.
    • JEON HEE-SEOGYOON SEUNG-BEOMKIN RYUTAICHOI YONG-SUK
    • H01L21/8247H01L21/28H01L21/336H01L27/115H01L29/423H01L29/51H01L29/788H01L29/792
    • H01L27/115H01L21/28273H01L27/11521H01L29/42324H01L29/513H01L29/7881
    • PROBLEM TO BE SOLVED: To provide a split gate-type nonvolatile semiconductor memory device and a manufacturing method of the same.
      SOLUTION: A gate insulating layer and a floating gate conductive layer are formed on a semiconductor substrate, a mask layer pattern is formed, a first sacrifice spacer is formed on both walls thereof, an inter-gate insulating layer is formed on the floating gate insulating conductive layer, the first sacrifice spacer is removed, etching is performed on the floating gate conductive layer with the mask layer pattern and inter-gate insulating layer as the masks, a tunneling insulating layer is formed on an exposed portion thereof, a control gate conductive layer is formed on the entire surface of the semiconductor substrate, a second sacrifice spacer is formed thereon, etching is performed on the control gate conductive layer with it as a mask to form the control gate, and etching is performed on the remaining mask layer pattern, inter-gate insulating layer and exposed floating gate conductive layer to form the floating gate.
      COPYRIGHT: (C)2005,JPO&NCIPI
    • 解决的问题:提供一种分离式栅型非易失性半导体存储器件及其制造方法。 解决方案:在半导体衬底上形成栅极绝缘层和浮栅导电层,形成掩模层图案,在其两个壁上形成第一牺牲隔离物,在栅极绝缘层上形成栅极间绝缘层 浮置栅极绝缘导电层,去除第一牺牲间隔物,以掩模层图案和栅极间绝缘层为掩模对浮栅导电层进行蚀刻,在其暴露部分上形成隧道绝缘层, 控制栅极导电层形成在半导体衬底的整个表面上,在其上形成第二牺牲衬垫,以控制栅极导电层作为掩模进行蚀刻,形成控制栅极,并对剩余的栅极进行蚀刻 掩模层图案,栅极间绝缘层和暴露的浮栅导电层以形成浮栅。 版权所有(C)2005,JPO&NCIPI